JPH0722921A - Delay circuit - Google Patents

Abstract

PURPOSE:To improve the level of integration of a semiconductor integrated circuit by forming the circuit by plural inverters for which a cascade connection is performed and compressing the occupancy area of the delay circuit of the circuit. CONSTITUTION:A delay circuit is respectively and individually connected between the inputs/outputs of specified inverters 12 and 14 included in plural inverters and is provided with capacitance 13 and 15 presenting feedback actions in the delay circuit by a semiconductor integrated circuit formed by performing a cascade connection for plural inverters 11, 12, 14 and 16. By reducing the number of stages of the inverter and reducing the sum of required capacitance values by increasing the delay time of each stage by the feedback actions by these capacitance 13 and 15, the occupancy area of the delay circuit is compressed and the level of integration of the semiconductor integrated circuit is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit, and more particularly to a delay circuit used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As a delay circuit used in a conventional semiconductor integrated circuit, as shown in FIG. 2A, inverters 21, 23, 25 and 27 and capacitors 22, 2 are provided.
Many are configured with 4 and 26. When a CMOS inverter is used as the inverter in FIG. 2A, the inverter is
As shown in (b), P corresponding to the power supply voltage V _DD
MOS transistor 28 and NMOS transistor 2
9 and the power supply voltage V _DD = 5V,
When the input voltage to the inverter is 0V, the PMOS
The transistor 28 turns on, and the NMOS transistor 29
Is turned off, the capacity connected to the output terminal of the inverter is charged, and finally the voltage V _DD = 5V equal to the power supply voltage is reached. When the input voltage to the inverter is 5V, the PMOS transistor 28 is turned off and the NMOS transistor 29 is turned on to discharge the electric charge of the capacitor connected to the output terminal of the inverter, and its terminal voltage becomes 0 potential. Thus, the capacitance 2 connected to the output terminals of the inverters 21, 23 and 25 respectively
The function as a delay circuit is obtained by utilizing the transmission delay action due to the charging time and the discharging time in 2, 24 and 26.

In the delay circuit configured as described above, in order to obtain a required delay time, it is necessary to set the number of connecting stages of the inverter and the capacitor to be appropriately increased. In order to reduce the delay time, a method of increasing the delay time in each stage by increasing the capacitance value connected to each inverter is performed. Figure 2 (c) shows
It is a figure which shows the signal waveform of each stage in the delay circuit of 4 stages shown to Fig.2 (a), and the input signal 2 in FIG.2 (a).
01, node N ₁ , node N ₂ , node N ₃ and output signal 2
Each 02 signal waveform is clearly shown. In this conventional example, the total sum of the capacitance values used is 15 pF, and a delay time of about 7.4 ns is obtained as the total delay circuit.

[0004]

In the above-mentioned conventional delay circuit, in order to obtain the necessary delay time, the number of inverter stages is increased or the capacitance value loaded on the output side of each inverter is increased. It is necessary to adopt any one of these methods, but even if any of these methods is adopted, as a result, the occupied area of the semiconductor integrated circuit forming the delay circuit is increased and the semiconductor integrated circuit It has the drawback of degrading the degree of integration.

[0005]

SUMMARY OF THE INVENTION A delay circuit according to the present invention is a delay circuit comprising a semiconductor integrated circuit formed by cascade-connecting a plurality of inverters, and between the input and output of a specific inverter included in the plurality of inverters. It is characterized in that the capacitors are individually connected to each other, and each of the capacitors has an individual feedback function.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1A is a block diagram showing an embodiment of the present invention. As shown in FIG. 1A, in this embodiment, the inverters 11, 12, 14 and 16 and the capacitor 1 are used.
And 3 and 15. The difference between this embodiment and the above-mentioned conventional example is clear from the comparison with the conventional example of FIG.
Is connected between a node N ₁ located at the output end of the inverter 11 and a node N ₂ located at the output end of the inverter 12, and the capacitor 15 has a node N ₂ located at the output end of the inverter 12. Is connected to the node N ₃ located at the output terminal of the inverter 14, and each capacitor is not individually connected to the ground point at each node as in the conventional example. These capacities 13 and 15 are
The inverter 12 and the inverter 14 respectively have a function as a feedback circuit, and the feedback action of this capacitance increases the delay time of each stage in the inverter 12 and the inverter 14.

FIG. 1B is a diagram showing the signal waveform of each stage in the four-stage delay circuit shown in FIG. 1A. The input signal 101, the node N ₁ , and the node in FIG. 1A are shown. The signal waveforms of N ₂ , node N ₃ and output signal 102 are clearly shown. In this embodiment, the capacitors 13 and 1
The sum of the capacitance values including 5 is 10 pF, and a delay time of about 12.5 ns is obtained for the delay circuit as a whole. Therefore, in this embodiment, in comparison with the above-mentioned conventional example,
In addition to reducing the total capacitance value from 15 pF to 10 pF, the delay time is from 7.4 ns to 10.5
The great effect of being increased to ns is obtained.

[0009]

As described above, according to the present invention, it is possible to increase the delay time per stage by connecting a capacitor having a feedback function between the input and output of each stage inverter. Moreover, since the total sum of required capacitance values can be reduced, the area occupied by the semiconductor integrated circuit can be effectively compressed, and the degree of integration of the semiconductor integrated circuit can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention and a signal waveform diagram of each section.

FIG. 2 is a block diagram showing a conventional example and a signal waveform diagram of each part.

[Explanation of symbols]

11, 12, 14, 16, 21, 23, 25, 27
Inverter 13, 15, 22, 24, 26 Capacitance 28 PMOS transistor 29 NMOS transistor

Claims (1)

[Claims] 1. A delay circuit comprising a semiconductor integrated circuit formed by cascading a plurality of inverters, wherein the delay circuits are individually connected between the input and output of specific inverters included in the plurality of inverters, respectively. A delay circuit characterized in that each of them has a capacitance that exhibits a feedback action.