JPH03101159A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To operate all circuits inside a semiconductor chip at the same speed and to suppress the irregularity in the speed by a method wherein the semiconductor chip is divided into a plurality of blocks, source voltage is adjusted at each block and the delay time is made constant. CONSTITUTION:A semiconductor chip 10 of which integrated circuits are constituted is divided into a plurality of blocks; a common power supply line 15 is arranged and installed for individual blocks B1 to B4. An electric current is applied simultaneously from the power supply line 15; a source voltage which is applied to the individual blocks is adjusted by a source voltage correction circuits 11 to 14 in such a way that it is controlled by delay time evaluation circuits inside the blocks and that the delay time inside the blocks becomes constant. Thereby, the source voltage can be set independently at the individual blocks; all circuits inside the chip can be operated at the same speed; irregularity in the speed is suppressed; the characteristic can be enhanced.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a semiconductor integrated circuit, particularly a power supply circuit thereof in which delay time is corrected, the power supply voltage is corrected so that the delay time of each part within the chip does not deviate much from a predetermined value. For the purpose of Each block is provided with a power supply voltage correction circuit that supplies within the block a power supply voltage adjusted so that the intra-block delay time becomes constant.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit, and more particularly to a power supply circuit thereof with delay time correction.

In recent years, as semiconductor integrated circuits have become more highly integrated and faster, it has become essential to guarantee the delay time of circuits within semiconductor chips.

[Conventional technology]

In a semiconductor integrated circuit, a power supply wiring connected to a terminal pin to which an external power supply is applied is usually arranged on a semiconductor chip, and each circuit element on the chip is supplied with power from the power supply wiring.

For example, a power supply wiring is provided in a circular shape around the chip, the wiring is connected to one or more power supply terminal bins, and a power supply circuit of a circuit element within the chip is connected to the wiring.

However, due to the increased integration and speed of semiconductor integrated circuits,
A power supply voltage drop occurs in a part of the circuit within the chip, which causes fluctuations in signal propagation delay time. This poses a problem, such as erroneous output in high-speed logic gates, for example. Causes of variations in the power supply voltage of various parts within the chip include increased load on the power supply line due to the operation of circuit elements, changes in characteristics due to temperature, and variations in characteristics due to the manufacturing process.

[Problem to be solved by the invention]

In a system where the power supply wiring on the chip is used as a common power supply wiring and each circuit element within the chip receives power from this wiring, there is a risk that a local power supply voltage drop occurs during the operation of the semiconductor integrated circuit, resulting in speed variations. be.

An object of the present invention is to improve this point and correct the power supply voltage so that the delay time of each part within the chip does not exceed a predetermined value.

[Means for Solving the Problems] As shown in FIG. 1, in the present invention, the semiconductor chip 10 is divided into a plurality of blocks, in this example, four blocks 81 to B4, and a common power supply line 15 is provided to each block. , power supply voltage correction circuits 11 to 14 are provided in each block.

Although not shown, the power line 15 is connected to one or more external power terminal bins and is supplied with power from the external power source.

The power supply voltage correction circuits 11 to 14 are supplied with power from the power supply line 15, and are controlled by the intra-block delay time evaluation circuit to supply voltages adjusted so that the intra-block delay time becomes constant to each circuit element within the block. Power lines 16 to 19 supply the adjusted voltage into the block.

FIG. 2 shows the configuration of the power supply voltage correction circuits 11 to 14, and includes variable voltage regulators 21. It includes an F/V converter 22 and a delay correction circuit (delay time evaluation circuit) 23.

It is possible to prevent variations in the

[Effect]

In this circuit, circuit elements in blocks B1 to B4 are supplied with power supply voltage through power supply lines 16 to 19.

This supply path is the common power supply line 15, the variable voltage regulator 21 of the power supply voltage correction circuit 11 of block B, and the block-specific power supply line 16 (other blocks also follow this).
The supplied power supply voltage is a voltage obtained by adjusting the voltage of the common power supply line 15 by a variable voltage regulator 21 controlled by a delay correction circuit 23 and an F/■ converter 22.

The delay correction circuit 23 is, for example, a ring oscillator supplied with power from the block-specific power supply line 16, and changes its oscillation frequency as the power supply voltage fluctuates. In this way, variations in the intra-block delay time are detected isometrically, and this variation in oscillation frequency is F/V (frequency/voltage) converted by the converter 22, and the regulator 21 is controlled by negative feedback using the output voltage. This prevents variations in the delay time within the block and reduces the delay time on the chimp [Example] Variable voltage regulator 21. Specific examples of the F/V converter 22 and the delay correction circuit 23 are not shown in FIG.

As shown in FIG. 3(a), the delay correction circuit 23 is a ring oscillator formed by connecting an odd number of inverters 11 to I5, five in this example, in a ring. When the input of inverter 11 is H, the output of 11 (input of 1□) is high, the output of Iz (input of 13) is the same as H1 and below, and the output of 15 is L, and the dirt is 1. When added to , the output of 11 becomes H, the output of I2 becomes H, etc., which is the opposite of the above. These are repeated and the circuit oscillates. The oscillation period is the sum of the signal propagation delay times of each inverter, and the circuit resistance,
Affected by parasitic capacitance, power supply voltage, etc. Therefore, if the power supply for this circuit is taken from the block-specific power supply line (16, etc.), the oscillation period (oscillation frequency) can represent the delay time and its fluctuation of the circuit elements of the block.

As shown in FIG. 3(b), the F/V converter is composed of a Schmitt circuit 22a, an integrator 22b, R2, 02, etc., and the input is the oscillation output A of the ring oscillator 23. This turns transistor Q on and off, and the transistor Q
discharges capacitor C1, which is charged through resistor R1, when on.

After the voltage of the capacitor CI is shaped by the Schmitt circuit 22a, the switch SW is switched to the contact a side and the contact b side to charge/discharge the integrating circuit. The output voltage B of this integrating circuit is proportional to the input frequency A.

As shown in FIG. 3(C), the variable voltage regulator 21 is composed of a differential amplifier 21a and resistors R3 and R4. F/
It receives the output voltage B of the V converter and generates an output voltage C proportional to it, which is applied to the block-specific power supply line (16, etc.). The power supply for the differential amplifier 21a is obtained from the common power supply line 15.

This allows the entire circuit within the chip to operate at the same speed, suppressing variations in speed and contributing to improved characteristics.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram of a power supply voltage correction circuit, and FIG. 3 is a circuit diagram showing a specific example of each part of FIG. 2. In FIG. 1, IO is a semiconductor chip, II-14 are power supply voltage correction circuits, 15 is a common power line, and 16-19 are block-specific power lines.

Claims (1)

[Claims] 1. A semiconductor chip (10) that constitutes an integrated circuit is divided into a plurality of blocks, and a common power line (15) is provided to each block (B_1 to B_4), and power is supplied from the common power line, and the blocks Each block is provided with a power supply voltage correction circuit (11 to 14) that is controlled by an internal delay time evaluation circuit (23) and supplies a power supply voltage adjusted so that the internal delay time becomes constant within the block. Features of semiconductor integrated circuits.