JPH0685622A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To secure the output of an oscillation signal of the natural frequency through an oscillation circuit even with the change of the time constant or the fluctuation of the power voltage. CONSTITUTION:An oscillation circuit part 1 is connected to a point between a power supply VCC and the ground GND and outputs an oscillation signal of the natural frequency based on the time constant and the voltage value which are previously set. An LPF 2 integrates the oscillation signal of the part 1 and outputs the comparison output Vo. A reference voltage generating circuit 3 generates the reference voltage Vref in accordance with the oscillation signal of the natural frequency. A comparator 4 compares the voltage Vo with the voltage Vref and outputs the control voltage Vi to reduce and increase the frequency of the oscillation signal when the voltage Vo is larger and smaller than the voltage Vref respectively. A correction circuit 5 corrects the oscillation frequency of the part 1 into the natural frequency based on the voltage Vi of the comparator 4.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to an oscillator circuit. In recent years, with the miniaturization of semiconductor devices (LSIs), lower power consumption of LSIs has been demanded. In order to meet this requirement, there is a demand for an oscillator circuit that can operate at a low voltage and that is unlikely to cause frequency drift due to temperature changes or power supply voltage changes.

[0002]

2. Description of the Related Art A conventional CR oscillator circuit is shown in FIG. On the semiconductor chip T, an odd number of stages (three stages in this case) of CMOS
Inverters 41a to 41c and a waveform shaping CMOS inverter 42 are provided. Hereinafter, the CMOS inverter is simply referred to as an inverter. Inverters 41a to 41
c and the waveform shaping inverter 42 are connected in series. The input side of the inverter 41a is connected to the input terminal 43 of the semiconductor chip T. In addition, the inverter 41
The output side of c is connected to the input / output terminal 44 of the semiconductor chip T. A time constant circuit 45 including a resistor R and a capacitor C is provided between the input terminal 43 and the input / output terminal 44.
Are connected.

The input of the inverter 41a is L level, that is, the charging voltage of the capacitor C is the inverter 41a.
In the state of being less than the threshold voltage of, the output of the inverter 41c becomes H level. Then, the input / output terminal 44 and the resistor R
The capacitor C is charged via the. Since the output of the inverter 41c is at the H level during this charging, the output of the waveform shaping inverter 42 becomes at the L level.

When the input of the inverter 41a is at H level, that is, when the charging voltage of the capacitor C reaches the threshold voltage of the inverter 41a, the output of the inverter 41c becomes L level. Then, the charge charged in the capacitor C is discharged through the resistor R, the input / output terminal 44 and the inverter 41c. Since the output of the inverter 41c is at the L level during this discharge, the output of the waveform shaping inverter 42 becomes at the H level.

Therefore, in this oscillator circuit, the inverters 41a to 41a-4 are driven by the delay time determined by the time constant of the time constant circuit 45 and the delay of each of the inverters 41a to 41c.
The output level of 1c is inverted. And the inverter 4
The output of 1c is shaped into a square wave by the waveform shaping inverter 42, so that the oscillation signal F0 having a natural frequency is output.

[0006]

However, the above-mentioned C
In the R oscillator circuit, when the temperature changes, the resistance value of the resistor R changes, and the time constant of the time constant circuit 45 changes. When the power supply voltage changes, the delay times of the inverters 41a to 41c and the waveform shaping inverter 42 change. Therefore, the oscillation signal F changes due to temperature changes and power supply voltage changes.
There is a problem that the frequency of 0 fluctuates from the natural frequency.

That is, for example, when the temperature rises, the resistance value of the resistor R increases and the charging / discharging time of the capacitor C, that is, the delay time becomes longer. As a result, the frequency of the oscillation signal F0 output from the waveform shaping inverter 42 decreases from the natural frequency.

Further, when the power supply voltage drops, the delay time of each of the inverters 41a to 41c and the waveform shaping inverter 42 becomes longer. Therefore, the charging / discharging time of the capacitor C,
That is, the delay time becomes long, and the waveform shaping inverter 4
The frequency of the oscillation signal F0 output from 2 decreases from the natural frequency. In particular, when a battery is used as the power supply voltage, the power supply voltage drops, so that frequency fluctuations are likely to occur.

The present invention has been made in order to solve the above problems, and it is possible to output an oscillation signal of a natural frequency even if the time constant changes or the power supply voltage changes. The purpose is to provide a circuit.

[0010]

FIG. 1 is a diagram for explaining the principle of the present invention. The oscillating circuit section 1 is connected between the power supply Vcc and the ground GND and is configured to output an oscillating signal having a natural frequency based on a preset time constant and a preset voltage value. The low-pass filter 2 integrates the oscillation signal of the oscillation circuit unit 1 and outputs a comparison voltage Vo. The reference voltage generating circuit 3 generates a reference voltage Vref corresponding to an oscillation signal having a natural frequency. The comparator 4 compares the comparison voltage Vo with the reference voltage Vref, and the comparison voltage Vo is compared with the reference voltage Vref.
When it is larger than ref, the frequency of the oscillation signal is lowered, and when the comparison voltage Vo is smaller than the reference voltage Vref, the control voltage Vi for increasing the frequency of the oscillation signal is output. The correction circuit 5 corrects the oscillation frequency of the oscillation circuit unit 1 to the natural frequency based on the control voltage Vi of the comparator 4.

In the second aspect of the invention, the odd-numbered CMOS inverters connected in series and the time constant circuit connected between the input side of the first-stage CMOS inverter and the output side of the final-stage CMOS inverter are provided. The oscillator circuit section was constructed. Also, the power supply is connected as an operating power supply, and the comparator is configured by a comparator in which the reference voltage is input to the non-inverting input terminal and the comparison voltage is input to the inverting input terminal. Further, a plurality of correction PMOS transistors connected between each CMOS inverter and the power supply,
A plurality of correction NMOS transistors connected between each CMOS inverter and the ground, and a gate voltage supplied to each correction PMOS transistor is reduced as the control voltage is increased, and is supplied to each correction NMOS transistor. And a bias generation circuit for increasing the gate voltage supplied to each correction PMOS transistor as the control voltage decreases and decreasing the gate voltage supplied to each correction NMOS transistor. Configured the circuit.

[0012]

Therefore, in the first invention, when the oscillation frequency of the oscillation circuit section 1 changes from the natural frequency due to the change of the time constant or the change of the power supply voltage, the comparison voltage V of the low-pass filter 2 is changed.
o does not match the reference voltage Vref. Therefore, the comparator 4 outputs the control voltage Vi for decreasing or increasing the frequency of the oscillation signal. Then, this control voltage Vi
Based on the above, the frequency of the oscillation signal of the oscillation circuit unit 1 is corrected to the natural frequency by the correction circuit 5.

In the second aspect of the invention, for example, when the oscillation frequency of the oscillation circuit section decreases from the natural frequency, the control voltage of the comparator increases. Then, the bias generator circuit lowers the gate voltage supplied to the correcting PMOS transistor and increases the gate voltage supplied to the correcting NMOS transistor. Therefore, the impedances of the correcting PMOS and the correcting NMOS transistor are reduced. As a result, the delay time of each CMOS inverter is reduced, and the oscillation frequency of the oscillation circuit section is corrected to the natural frequency. Moreover, when the oscillation frequency of the oscillation circuit section increases from the natural frequency, the control voltage of the comparator decreases. Then, the bias generation circuit increases the gate voltage supplied to the correction PMOS transistor and decreases the gate voltage supplied to the correction NMOS transistor. For this reason, the impedance of the correction PMOS and the correction NMOS transistor increases. As a result, the delay time of each CMOS inverter increases, and the oscillation frequency of the oscillation circuit section is corrected to the natural frequency.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. The same components as those in FIG. 1 will be described with the same reference numerals.

As shown in FIG. 2, the oscillator circuit includes a voltage controlled oscillator (hereinafter referred to as VCO) 11, a frequency divider 12, a low-pass filter (hereinafter referred to as LP) provided on a semiconductor chip T.
A reference voltage generation circuit (hereinafter referred to as F) 13, a reference voltage generation circuit (hereinafter referred to as a reference circuit) 14, and a comparator 15. VCO 11 is an input terminal 1 of the semiconductor chip T
6 and the input / output terminal 17. Further, the oscillator circuit includes a time constant circuit 18 externally attached via the input terminal 16 and the input / output terminal 17. The time constant circuit 18 is composed of a resistor R1 and a capacitor C1.

The VCO 11 is shown in FIG. Odd stage (three stages in this embodiment) CMOS inverters 20 to 2
Reference numeral 2 is composed of PMOS and NMOS transistors (hereinafter, transistors are referred to as Tr) 23 and 24, respectively.
The CMOS inverters 20 to 22 are connected in series, and CM
A waveform shaping CMOS inverter 25 is connected to the OS inverter 22. Hereinafter, the CMOS inverter is simply referred to as an inverter.

The input side of the inverter 20 and the inverter 22
The input terminal 16 and the input / output terminal 1 are connected to the output side of the
A time constant circuit 18 is connected via 7. In this embodiment, the inverters 20 to 22 and the waveform shaping inverter 2
5, and the time constant circuit 18 constitutes the oscillation circuit unit 1. Correction PMOSTrs 26a to 26c are connected between the inverters 20 to 22 and the power supply Vcc.
Further, correction NMOSTrs 27a to 27c are connected between the inverters 20 to 22 and the ground GND.
Each correction PMOSTr26a-26c and each correction NM
The OSTrs 27a to 27c are always operating.

Therefore, when the input of the inverter 20 is L level, the output of the inverter 20 is H level, the output of the inverter 21 is L level, and the output of the inverter 22 is H level. Therefore, the correction PMOSTr2
6c, PMOS Tr23 of the inverter 22 and resistor R1
The capacitor C1 is charged via the. Further, since the output of the inverter 22 is at the H level, the output of the waveform shaping inverter 25 is at the L level.

The charging voltage of the capacitor C1 is the inverter 2
When the threshold voltage of 0 is reached and H level is reached, the output of the inverter 20 becomes L level, the output of the inverter 21 becomes H level, and the output of the inverter 22 becomes L level.
Therefore, the resistor R1 and the NMOSTr2 of the inverter 22 are
4 and the capacitor C via the correction NMOSTr27c
The charge of 1 is discharged. Further, since the output of the inverter 22 is L level, the output of the waveform shaping inverter 25 is H level.

As the capacitor C1 is repeatedly charged and discharged in this manner, the waveform shaping inverter 25 alternately outputs the H or L level, and the oscillation circuit unit 1 outputs the oscillation signal F0. When the operating temperature is the set temperature and the power supply VCC has the set voltage value, the frequency of the oscillation signal F0 becomes the natural frequency. The natural frequency is determined based on the delay time of each inverter 20 to 22, the time constant determined by the resistance value set in the resistor R1 and the capacity set in the capacitor C1, and the voltage value of the power supply VCC.

Further, there is a P between the power supply VCC and the ground GND.
MOSTr28, control NMOSTr29, NMOST
Bias generation circuit 31 in which r30 and resistor R5 are connected in series
Is provided. The gate terminal of the PMOSTr28 is connected to the drain terminal of the control NMOSTr29,
The gate terminal of the OSTr30 is connected to the source terminal of the control NMOSTr29.

The gate terminal of the control NMOS Tr29 is connected to the output of the comparator 15 to be described later to receive the control voltage Vi. The drain terminal of the control NMOS Tr 29 is connected to the correction P via the first bias line 32.
It is connected to the gate terminals of the MOSTrs 26a to 26c. The source terminal of the control NMOSTr 29 is connected to the correction NMOSTr 27 via the second bias line 33.
It is connected to the gate terminals of a to 27c.

In this embodiment, the PMO for each correction is
The correction circuit 5 is configured by the STr 26, each correction NMOSTr 27, and the bias generation circuit 31. N for control
When the control voltage Vi is (Vcc / 2), the MOSTr 29 generates bias voltages V32 and V33 whose natural frequency is the oscillation frequency of the oscillation circuit section 1. Control NMOST
When the control voltage Vi is higher than (Vcc / 2), the impedance of r29 becomes small, which lowers the bias voltage V32 and increases the bias voltage V33. The control NMOS Tr29 has a control voltage Vi of (VCC /
If it is smaller than 2), the impedance becomes large, increasing the bias voltage V32 and increasing the bias voltage V3.
Decrease 3.

The impedances of the correction PMOSTrs 26a to 26c and the correction NMOSTrs 27a to 27c become preset values when the bias voltages V32 and V33 based on the control voltage Vi of (Vcc / 2) are input, and the inverters 20 to 20. The delay time of 22 is set to a preset value. The impedances of the correction PMOSTrs 26a to 26c and the correction NMOSTrs 27a to 27c become small when the bias voltages V32 and V33 based on the control voltage Vi larger than (Vcc / 2) are input, and the delay times of the inverters 20 to 22 are set in advance. Make it smaller than the set value. Furthermore, the correction PMOSTrs 26a to 26
c and the correction NMOSTrs 27a to 27c are (Vcc /
2) Bias voltage V3 based on smaller control voltage Vi
When 2, V33 is input, the impedance becomes large, and the delay time of the inverters 20 to 22 is made larger than a preset value.

The frequency divider 12 divides the oscillation signal F0 of the VCO 11 into a preset division ratio and outputs it to the LPF 13. That is, the frequency divider 12 includes a frequency division ratio setting register (not shown), and by setting the frequency division ratio n (n is an arbitrary natural number) from the outside, the oscillation signal F0 is reduced to 1 / n. The frequency is divided, and the divided signal F1 is output.

The LPF 13 includes resistors R2 and R connected in series.
3 and a capacitor C2 having one end grounded and the other end connected between the resistors R2 and R3. And
The LPF 13 integrates the frequency-divided signal F1 of the frequency divider 12 and outputs a comparison voltage Vcom to the comparator 15.

The reference circuit 14 includes resistors R4 and PNP.
It consists of a bandgap bias circuit with a transistor T1. One end of the resistor R4 is connected to the power supply Vcc, and the other end is connected to the emitter of the transistor T1. The base and collector of the transistor T1 are grounded. Then, the reference circuit 14 outputs the reference voltage Vref corresponding to the oscillation signal F0 of the natural frequency from the node a between the resistor R4 and the transistor T1.

The reference voltage Vref is input to the non-inverting input terminal of the comparator 15, and the comparison voltage Vcom is input to the inverting input terminal. The comparator 15 is connected between the power source Vcc and the ground GND, and uses the power source Vcc as an operating power source. The comparator 15 compares the comparison voltage Vcom with the reference voltage Vref. And the comparator 1
When the comparison and reference voltages Vcom and Vref match each other, the reference numeral 5 outputs the control voltage Vi of (VCC / 2) shown in FIG. Further, when the comparison voltage Vcom is higher than the reference voltage Vref, the comparator 15 outputs a control voltage Vi less than (VCC / 2) corresponding to the difference between the two voltages Vcom and Vref. Furthermore, the comparator 15 compares the comparison voltage Vcom with the reference voltage Vre.
If it is smaller than f, a control voltage Vi larger than (VCC / 2) corresponding to the difference between the two voltages Vcom and Vref is output.

Next, the operation of the oscillation circuit configured as described above will be described. Now, assuming that the operating temperature of the oscillation circuit is the set temperature and the power supply VCC has the set voltage value, the frequency of the oscillation signal F0 of the oscillation circuit unit 1 becomes the natural frequency. While the oscillation signal F0 having the natural frequency is being output, the frequency division signal F1 of the frequency divider 12 also has a constant frequency. The frequency-divided signal F1 is integrated by the LPF 13 and output as the comparison voltage Vcom. This comparison voltage Vcom is held in the same state as the reference voltage Vref of the reference circuit 14. Therefore, the control voltage Vi of the comparator 15 is
Becomes (VCC / 2). Control NMOST of VCO 11
By r29, bias voltages V32 and V33 whose natural frequency is the frequency of the oscillation signal F0 are generated based on the control voltage Vi of (Vcc / 2).

Therefore, the correction PMOSTrs 26a-26
The impedances of c and the correction NMOS Trs 27a to 27c are adjusted to preset values, and the delay times of the respective inverters 20 to 22 of the oscillation circuit unit 1 also become preset values. As a result, the frequency of the oscillation signal F0 of the oscillation circuit unit 1 is held at the natural frequency.

Here, for example, if the resistance value of the resistor R1 increases due to temperature rise, it becomes difficult for a current to flow through the resistor R1 and the charging / discharging of the capacitor C1 is delayed. Therefore, the transition time of the input of the inverter 20 becomes long, and the frequency of the oscillation signal F0 decreases from the natural frequency. The frequency of the divided signal F1 also decreases, and as shown in FIG.
com becomes lower than the reference voltage Vref. Therefore, the control voltage Vi increases from (VCC / 2), and the control NMOST
The impedance of r29 becomes small. Therefore, the bias voltage V32 is lowered and the bias voltage V33 is increased.

As a result, the correction PMOSTrs 26a ...
26c and the correction NMOSTrs 27a to 27c are adjusted to have small impedances. Therefore, the delay time of each inverter 20-22 is also reduced. As a result, the frequency of the oscillation signal F0 is adjusted to increase, that is, corrected to the natural frequency side.

Due to the delay time of the inverters 20 to 22, the change of the comparison voltage Vcom is delayed with respect to the change of the control voltage Vi as shown in FIG. Therefore, the control voltage V
When i rises to a value at which the oscillation frequency becomes the natural frequency, the oscillation frequency is still below the natural frequency, and the comparison voltage Vcom is also below the reference voltage Vref.

Therefore, the control voltage Vi becomes higher than the value for correcting the oscillation frequency to the natural frequency. Therefore, the oscillation frequency also rises to a value higher than the natural frequency, and the comparison voltage V
com rises to a value higher than the reference voltage Vref. Therefore, the control voltage Vi becomes less than (Vcc / 2), the impedance of the control NMOS Tr 29 decreases, the bias voltage V32 increases, and the bias voltage V33 decreases.

As a result, the correction PMOSTr 26a ...
26c and the correction NMOS Trs 27a to 27c are adjusted to have a large impedance. Therefore, the delay time of each inverter 20-22 also becomes large. As a result, the frequency of the oscillation signal F0 is adjusted so as to decrease, that is, corrected to the natural frequency side.

The correction is repeatedly executed as described above, and the frequency of the oscillation signal F0 converges on the natural frequency. When the voltage value of the power supply Vcc decreases from the set value, the delay time of each inverter 20 to 22 increases and the oscillation signal F
The frequency of 0 decreases from the natural frequency. Also in this case,
In the same manner as described above, the impedances of the power supply Vcc side and the ground GND side of the inverters 20 to 22 are adjusted, and the frequency of the oscillation signal F0 is corrected to the natural frequency.

As described above, in this embodiment, the oscillation signal F0 of the VCO 11 is divided by the frequency divider 12, the LPF 13 outputs it as the comparison voltage Vcom, and the comparator 15 compares it with the reference voltage Vref to control the voltage. It was made to return to VCO11 as Vi. Then, based on the control voltage Vi, the correction circuit 5 adjusts the impedances of the power supply VCC side and the ground GND side of the inverters 20 to 22 to correct the oscillation frequency of the oscillation circuit unit 1 to the natural frequency. As a result, the change in the resistance value of the resistor R1 or the power supply VCC
Even if the oscillation frequency changes due to the fluctuation of the voltage of 1, the oscillation frequency can be set as the natural frequency.

Further, in this embodiment, the frequency divider 12 for dividing the oscillation frequency of the VCO 11 by 1 / n is provided. Therefore, by changing the frequency division ratio of the frequency divider 12, the rate of change of the comparison voltage Vcom of the LPF 13 can be adjusted.
The response time for adjusting the oscillation frequency can be adjusted by adjusting the rate of change of the control voltage Vi.

In this embodiment, the time constant circuit 18 is composed of the resistor R1 and the capacitor C1, but instead of this,
It may be only a capacitor or a coil, or may be composed of a coil and a capacitor.

[0040]

As described in detail above, according to the present invention,
Even if the time constant changes or the power supply voltage changes, there is an excellent effect that the oscillation signal of the natural frequency can be output.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an oscillator circuit according to an embodiment.

FIG. 3 is a circuit diagram showing details of a VCO.

FIG. 4 is a waveform diagram showing the operation of one embodiment.

FIG. 5 is a circuit diagram showing a conventional oscillator circuit.

[Explanation of symbols]

 1 Oscillation circuit part 2 Low pass filter (LPF) 3 Reference voltage generation circuit 4 Comparator 5 Correction circuit 15 Comparator 18 Time constant circuit 20-22 CMOS inverters 26a-26c Correction PMOS transistor 27a-27c Correction NMOS transistor 31 Bias generation circuit GND Ground VCC Power supply Vi Control voltage Vcom, Vo Comparison voltage Vref Reference voltage

Claims (2)

[Claims] 1. An oscillation connected between a power supply (VCC) and a ground (GND) and configured to output an oscillation signal of a natural frequency based on a preset time constant and a preset voltage value. A circuit section (1), a low-pass filter (2) that integrates the oscillation signal of the oscillation circuit section (1) and outputs a comparison voltage (Vo), and a reference voltage (Vref) corresponding to the oscillation signal of the natural frequency.
) Is compared with the reference voltage (Vref) and the reference voltage (Vref). When the comparison voltage (Vo) is larger than the reference voltage (Vref), the frequency of the oscillation signal is compared. Control voltage (Vo) for decreasing the frequency of the oscillation signal when the comparison voltage (Vo) is smaller than the reference voltage (Vref).
a comparator (4) for outputting i), and a correction circuit (5) for correcting the oscillation frequency of the oscillation circuit section (1) to a natural frequency based on the control voltage (Vi) of the comparator (4). An oscillator circuit comprising: 2. An odd-numbered stage CMOS inverter (20 to 22) and a first-stage CMOS inverter (2) connected in series.
0) and a time constant circuit (18) connected between the input side of the final stage CMOS inverter (20) and the time constant circuit (18). And the reference voltage (Vref) is input to the non-inverting input terminal and the comparator voltage (Vcom) is input to the inverting input terminal to configure the comparator, and the CMOS inverters (20-22) and power supply (VC
C) Multiple compensation PMOSs connected between
The transistors (26a to 26c) and a plurality of correction NMOS transistors (2) respectively connected between the CMOS inverters (20 to 22) and the ground (GND).
7a to 27c), the gate voltage supplied to each of the correction PMOS transistors (26a to 26c) is decreased with an increase in the control voltage (Vi), and each correction N
The gate voltage supplied to the MOS transistors (27a to 27c) is increased, and the gate voltage supplied to each correction PMOS transistor (26a to 26c) is increased as the control voltage (Vi) is decreased. N
The oscillation circuit according to claim 1, wherein the correction circuit is configured to include a bias generation circuit (31) that lowers a gate voltage supplied to the MOS transistors (27a to 27c).