JP4833455B2 - Constant voltage generation circuit and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a voltage stabilization technique, and can particularly quickly recover and stabilize the output voltage when an overshoot or undershoot occurs.ConstantThe present invention relates to a voltage generation circuit and a semiconductor device.
[0002]
[Prior art]
FIG. 9 is a diagram for explaining the configuration of a conventional general constant voltage circuit.
As shown in the figure, the conventional general constant voltage circuit includes an error amplifier A31, a P-type output transistor Q35, and a resistor R33. The gate of the output transistor Q35 is connected to the output of the error amplifier A31. The source of the output transistor Q35 is connected to the power supply Vdd, and the drain of the output transistor Q35 is connected to the ground Vss via the resistor R33 and is connected to the non-inverting input terminal (+) of the error amplifier A31. The internal reference voltage Vref is input to the inverting input terminal (−) of the error amplifier A31. Further, a load circuit including a capacitor C33 is connected to the drain of the output transistor Q35.
[0003]
In the constant voltage circuit having the above configuration, when the load consumes power at an arbitrary time, the output voltage Vout to the load circuit including the capacitor C33 varies, and this output voltage Vout is non-inverted by the error amplifier A31. The internal reference voltage Vref input to the input terminal (+) and input to the inverting input terminal (−) is compared, and the gate potential of the output transistor Q35 is raised or lowered according to the comparison result to control the on-resistance of the output transistor Q35. I am doing so. As a result, the output voltage Vout can be made substantially equal to Vref, and as a result, the output voltage Vout can be made constant.
[0004]
FIG. 10 is a diagram for explaining a circuit configuration example of an internal voltage down converting circuit, a wiring equivalent circuit, and a load circuit disclosed in Japanese Patent No. 3085562 “Reference voltage generating circuit and internal voltage down converting circuit”. What is disclosed in this publication relates to a circuit that steps down an external power supply voltage to generate an internal power supply voltage.
[0005]
As shown in FIG. 10, the internal step-down circuit 40 disclosed in this publication is composed of an error amplifier (differential amplifier) A41 and an output transistor Q45, and outputs between the internal power supply line Vout and the gate of the output transistor Q45. A feedback capacitor C41 having a capacitance value greater than or equal to the gate capacitance of the transistor Q45 is connected. The wiring equivalent circuit 50 includes a resistor R54, two capacitors C53 and C54, and the load circuit 60 includes a P-type transistor Q66, an N-type transistor Q67, a load capacitor C65, and a resistor R63 whose gates are controlled by a signal φ. It is configured.
[0006]
In the configuration of FIG. 10, when the load capacitance C65 is controlled by causing the P-type transistor Q66 and the N-type transistor Q67 to perform a high-speed switching operation by the signal φ, the change of the output voltage Vout is delayed via capacitive coupling by the feedback capacitance C41. Therefore, the internal power supply voltage Vout can be prevented from oscillating due to a response delay.
[0007]
FIG. 11 is a diagram for explaining a configuration of a semiconductor integrated circuit including a voltage auxiliary circuit disclosed in Japanese Unexamined Patent Publication No. 2000-47740 “Voltage Auxiliary Circuit and Semiconductor Integrated Circuit Device”. An auxiliary circuit 70 and a load circuit (internal circuit) 90 are shown.
[0008]
In the figure, an internal step-down circuit 80 includes an error amplifier (comparator) A81 and an output transistor Q85, and a voltage auxiliary circuit 70 includes a constant current source I71 and P-type transistors Q71 to Q73, a comparator A72, and a capacitor C71. .
[0009]
In the voltage auxiliary circuit 70, the P-type transistor Q71 is connected between the power supply Vdd and the inverting input terminal (−) of the comparator A72. The gate of the P-type transistor Q71 is connected to the inverting input terminal (−) of the comparator A72. The constant current source I71 is connected between the node Z71 and the ground Vss. Due to the series connection configuration of constant current source I71 and P-type transistor Q71, a constant voltage is generated at node Z71 with respect to power supply voltage Vdd.
[0010]
P-type transistor Q72 is connected between power supply Vdd and node Z72. P type transistor Q72 has its gate connected to node Z72. The capacitor C71 and the P-type transistor Q72 are connected in series to form a voltage dividing circuit. P-type transistor Q72 is turned on / off in response to the potential of node Z72.
[0011]
P-type transistor Q73 is connected between power supply Vdd and output node Z70. The gate of P-type transistor Q73 is connected to the output of comparator A72. The comparator A72 inputs the voltage of the node Z71 and the voltage of the node Z72 and compares them. The P-type transistor Q73 is controlled to be turned on / off in response to the comparison result between the voltage at the node Z71 and the voltage at the node Z72 by the comparator A72.
[0012]
In this configuration, the node Z72 is set to have a higher potential than the node Z71 in a steady state. In this state, for example, if the output voltage Vout suddenly decreases due to the operation of the load circuit 90, the potential of the node Z72, that is, the potential of the non-inverting input terminal (+) of the comparator A72 decreases due to the coupling of the capacitor C71. As a result, the output of the comparator A72 becomes L level, and the P-type transistor Q73 is turned on.
[0013]
As a result, the output node Z70 is charged, and the potential of the non-inverting input terminal (+) of the comparator A72 is also charged through the P-type transistor Q72, so that the output of the comparator A72 is recovered to the H level, and a series of charging is performed. The operation ends. In this way, the voltage auxiliary circuit 70 charges the output terminal in response to only the differential component when the output voltage Vout suddenly decreases. This publication (Japanese Patent Laid-Open No. 2000-47740) also mentions a voltage auxiliary circuit to the ground side using an N-type transistor.
[0014]
[Problems to be solved by the invention]
In the conventional general constant voltage circuit shown in FIG. 9, the current flowing through the resistor R33 connected between the drain of the output transistor Q35 and the ground Vss affects the overall current consumption as a steady leakage current. In a system such as a terminal device, the resistor R33 is generally selected to have a value on the order of several MΩ to several tens of MΩ. In addition, the current drive capability of the output transistor Q35 is determined by improving the rising characteristics of the constant voltage circuit and the maximum value of the current supply capability required by the load circuit, so that it is designed to obtain a large drive capability. Depending on the system, it can reach the order of several tens of mA to several hundred mA.
[0015]
In order to satisfy the two requirements of suppressing the steady consumption current and maintaining the high current supply capability, there has conventionally been a method of combining the resistor R33 having a high resistance value and the output transistor Q35 having a high drive capability. It has been adopted. On the other hand, wiring capacitance is parasitic on the output voltage wiring of the constant voltage circuit, and a stabilization capacitor C33 is often connected to the output terminal as a part of the load circuit in order to remove noise components due to its nature.
[0016]
Here, in such a system, there is a problem that the transient response characteristic is significantly deteriorated due to the capacitor C33 connected to the output terminal due to the large difference in the current drive capability between the resistor R33 and the output transistor Q35.
[0017]
That is, if sudden noise is superimposed on the power supply Vdd or positive noise is generated on the internal reference voltage Vref, the output voltage Vout becomes higher than the specified value. In addition, when the output current rapidly decreases due to the operation of the load circuit, the output voltage Vout causes an overshoot due to the operation delay of the control loop of the drain voltage-error amplifier-output transistor Q35. This state is indicated by a broken line in FIGS. 3 and 5 described later.
[0018]
As shown by the broken lines in FIGS. 3 and 5, the capacitor C33 is charged with the high drive capability of the output transistor Q35. Once such a charge is charged, the path for discharging the charge is now a high resistance. Since only the value R33 exists, a phenomenon occurs in which the output voltage Vout is maintained high for a long time due to the charge charged in the capacitor C33. In addition, when such an external factor for increasing the output voltage is applied in a short cycle, there is a problem that the output voltage Vout constantly increases.
[0019]
On the other hand, in the circuit disclosed in Japanese Patent No. 3085562 as shown in FIG. 10, the output voltage Vout is obtained through capacitive coupling by the feedback capacitor C41 connected between the output node (Vout) and the gate of the output transistor Q45. Is transmitted to the gate of the output transistor Q45 without delay, so that it is possible to suppress the oscillation of the internal power supply voltage Vout due to the response delay.
[0020]
However, the feedback capacitor C41 connected in this case needs to be larger than the gate capacitance of the output transistor Q45, the load circuit 60 to be processed is a semiconductor memory device, and the capacitor C53 that is always connected is very small (pF order). It is effective when there is a steady output current, but it cannot be handled in a case where the output current fluctuates from 0 A to several tens of mA and the capacitance C53 reaches the μF order. That is, in such a situation, there is no means for easily generating an overshoot and discharging an extra voltage.
[0021]
Further, in the circuit disclosed in Japanese Patent Application Laid-Open No. 2000-47740 as shown in FIG. 11, an abrupt change in output voltage (Vout) is input to the non-inverting input terminal (+) of the comparator A72 via the capacitor C71. Then, by comparing this input voltage with the input voltage of the inverting input terminal (−) which is the second reference voltage, a circuit for charging or discharging the output node only when the output voltage (Vout) fluctuates rapidly is proposed. is doing. However, in this case, the circuit configuration is complicated and the occupation area is large, and the feedback system similar to the conventional constant voltage circuit is used. Therefore, compared with the main constant voltage circuit due to the response delay problem inherent in the system. It is impossible to react even faster.
[0022]
Furthermore, in the circuit of FIG. 11, current always flows through the comparator A72 and the second reference voltage source, and the response speed of the comparator A72 is determined by the amount of current. It is necessary to ensure the amount of current. On the other hand, the steady voltage relationship between both input terminals of the comparator A72 is required to be set so that the charging transistor (Q73) is inactive. This is combined with the offset problem due to manufacturing variations of the comparator A72. This is a matter to be considered.
[0023]
Accordingly, the applicant of the present application has previously filed Japanese Patent Application No. 2000-138489 “Voltage generation method, voltage generation circuit, voltage regulator, and portable terminal device using them” (filed on May 11, 2000). This application proposes a reference voltage generating circuit (prior invention) with improved transient response.
[0024]
FIG. 12 is a diagram for explaining an example of the reference voltage generating circuit according to the prior invention.
In the figure, a reference voltage generating circuit 100 includes a charging circuit composed of a P-type transistor Q101 and a first resistor R101 connected in series, and a discharging circuit composed of a second resistor R102 and an N-type transistor Q102 connected in series. Have.
[0025]
The input of the reference voltage Vref from the internal reference voltage circuit 120 is supplied to the inverting input terminal (−) of the first error amplifier A101 and grounded via the third diode D103 and the resistor R103. This is supplied to the inverting input terminal (−) of the second error amplifier A102. The output voltage Vout is supplied to the non-inverting input terminal (+) of the first error amplifier A101 and the second error amplifier A102.
[0026]
The output of the first error amplifier A101 is supplied to the gate of the P-type transistor Q101, and the output of the second error amplifier A102 is supplied to the gate of the N-type transistor Q102.
[0027]
In addition, a fourth diode D104 is provided between the second resistor R102 and the N-type transistor Q102, in which two diodes that are conductive from the power supply terminal Vdd to the ground Vss are connected in series, and the fourth diode D104 is output from the output voltage Vout. A first diode D101 and a second diode D102 are connected in antiparallel to both ends of the first and second diodes D102 and D102.
[0028]
Further, the gate of the P-type transistor Q104 connected in parallel with the second resistor R102 having a high resistance value is connected to the first power supply terminal Vdd via the gate resistor R104, and further to the second resistor R102 via the gate capacitor C104. And a connection point of the fourth diode D104. That is, the gate resistor R104 and the gate capacitor C104 connected to the gate of the P-type transistor Q104 constitute a high-pass filter. By the high-pass filter constituted by the gate resistor R104 and the gate capacitor C104, the voltage is applied to the gate resistor R104 at the moment when the output voltage Vout decreases, and the P-type transistor Q104 is turned on.
[0029]
Since the transistor Q101 secures the high speed of the output voltage Vout, the transistor Q102 secures the drop of the output voltage Vout, and the differential component of the fluctuation of the output voltage Vout is transmitted to the N-type transistor Q104. Only when the Vout temporarily drops below the set voltage, the N-type transistor Q104 is turned on, and the drop in the output voltage Vout can be suppressed and stabilized without time delay.
[0030]
However, since the above-mentioned prior invention does not consider canceling the threshold value Vth of the transistor Q104 combined with the high-pass filter composed of the gate resistor R104 and the gate capacitor C104, the threshold value Vth of the transistor Q104 is Although effective in the case of 0 V, the effect is generally not sufficient in the configuration as it is. Alternatively, when a transistor with a low threshold (Vth≈0V) is combined, there is a problem that the transistor Q104 is always turned on due to manufacturing variations and a reactive current flows, which affects the output node control system. .
[0031]
  The present invention has been made in view of the above problems, and can quickly recover and stabilize the output voltage when an overshoot or undershoot occurs, and has a simple configuration and is less susceptible to process variations. The operation is stable, the delay time is short, the occupied area is small, and the steady reactive current is extremely small.ConstantVoltage generation circuit (claim)1~3) And semiconductor devices (claims)4).
[0038]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has the following features. That is, (1)Claim1The described invention is provided with a constant voltage circuit (20), an output node (Vout) of the constant voltage circuit (20), and a first power supply (Vdd), and the first electrode is connected to the first power supply (Vdd). Vdd), the second electrode is connected to the power supply wiring or the output node (Vout), and the control electrode is formed between the power supply wiring or the output node (Vout) and the first power supply (Vdd). The first transistor (Q2) connected to the output point of the first high-pass filter, and provided between the output node (Vout) of the constant voltage circuit (20) and the second power supply (Vss), The electrode is connected to the second power supply (Vss), the second electrode is connected to the power supply wiring or the output node (Vout), and the control electrode is connected to the power supply wiring or the output node (Vout) and the second power supply (Vss). Formed during) The second transistor (Q3) connected to the output point of the second high-pass filter is connected in series between the first power supply (Vdd) and the second power supply (Vss), and is saturated. The third transistor (Q1) and the constant current source (I1) or the fourth transistor (Q4) saturatedly connected to the resistor is included, and the first high-pass filter includes the third transistor (Q1) and the constant current source ( I2) or a connection point with a resistor, and the second high-pass filter is connected to a constant current source (I1) or a connection point between the resistor and the fourth transistor (Q4) (FIG. 2). ).
[0039]
(2Claim2The described invention is claimed.1The first and second high-pass filters are configured by series connection of resistors (R1, R2) and capacitors, respectively, and the output point of each high-pass filter is the connection point of the resistor and capacitor ( Figure 2).
[0040]
(3Claim3The described invention is claimed.2, Among the resistors and capacitors constituting each high-pass filter, the resistors (R1, R2) are connected between the first power supply (Vdd) or the second power supply (Vss) and the control electrodes of the transistors (Q2, Q3). The capacitor (C1, C2) is provided between the control electrode of each transistor (Q2, Q3) and the power supply wiring or the output node (Vout) (FIG. 2).
[0041]
(4Claim4The semiconductor device described is, ContractClaim1~In any one of 3A semiconductor device comprising the constant voltage generation circuit described above as a constituent element.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram for explaining an embodiment of a constant voltage generation circuit according to the present invention, and shows a voltage stabilization circuit 10, a constant voltage circuit 20, and a load circuit 30. The constant voltage circuit 20 includes an error amplifier A1, a P-type transistor Q5, and a resistor R3, and the load circuit 30 has a load and a capacitor C3.
[0043]
The voltage stabilization circuit 10 according to the present embodiment has a pair of stabilization circuit configurations. As shown in the figure, one stabilization circuit configuration is composed of a constant current source I1, P-type transistors Q1 and Q2, a capacitor C1, and a resistor R1, and the other stabilization circuit configuration is a constant current source I1. ', N-type transistors Q3 and Q4, a capacitor C2, and a resistor R2. Each of these pair of stabilization circuit configurations functions independently, and depending on the target output node, both charging and discharging are not necessarily required. A stabilizing circuit that functions during charging (for example, described later) 6 (a), FIG. 7 (a), FIG. 8 (a)) or a stabilization circuit that functions at the time of discharging (for example, FIG. 6 (b), FIG. 7 (b), FIG. ))).
[0044]
P-type transistor Q1, resistor R1, and capacitor C1 are connected between power supply Vdd and output node Vout, the source of P-type transistor Q1 is connected to power supply Vdd, and the gate and drain of P-type transistor Q1 are connected to resistor R1. The constant current source I1 is connected to the ground Vss, and the P-type transistor Q2 is arranged between the power supply Vdd and the output node. The source of the P-type transistor Q2 is connected to the power supply Vdd, the drain of the P-type transistor Q2 is connected to the output node, The gate of the type transistor Q2 is connected to the connection point between the capacitor C1 and the resistor R1.
[0045]
On the other hand, N-type transistor Q4, resistor R2, and capacitor C2 are connected between ground Vss and the output node. The source of the N-type transistor Q4 is connected to the ground Vss, the gate and drain of the N-type transistor Q4 are connected to the resistor R2 and to the power supply Vdd via the constant current source I1 ′, and the N-type transistor Q3 is connected to the ground Vss to output node. The source of the N-type transistor Q3 is connected to the ground Vss, the drain of the N-type transistor Q3 is connected to the output node, and the gate of the N-type transistor Q3 is connected to the connection point between the capacitor C2 and the resistor R2.
[0046]
In FIG. 1, a pair of stabilizing circuit configurations each having a constant current source are used in combination, but as shown in FIG. 2, the constant current source I1 and the constant current source I1 ′ of FIG. The constant current source I1 may be shared (shared) and connected in series between the P-type transistor Q1 and the N-type transistor Q4, and the constant current source I1 may be shared by a pair of stabilization circuit configurations. Further, a configuration in which a high resistance is simply provided instead of the constant current source I1 may be used.
[0047]
As described above, the output of the high-pass filter composed of the capacitor C1 and the resistor R1 or the capacitor C2 and the resistor R2 is applied to the gates of the P-type transistor Q2 and the N-type transistor Q3 connected between the power supplies, respectively. By adopting, the capacitors C1 and C2 are balanced and charged with a voltage smaller than the set voltage of the output node to the voltage between the power supplies by the threshold value of each transistor. At this time, both the P-type transistor Q2 and the N-type transistor Q3 are in the off state.
[0048]
Next, consider the case where the voltage at the output node changes transiently from the set voltage due to load fluctuation. In this case, the differential component of the fluctuation amount is transmitted to the gates of the P-type transistor Q2 and the N-type transistor Q3 via the capacitors to control these transistors. For example, when the output voltage Vout rises, the N-type transistor Q3 is immediately turned on to discharge the voltage. On the contrary, when the output voltage Vout falls, the P-type transistor Q2 is immediately turned on to charge the voltage, and then the voltage is fixed. Keep voltage.
[0049]
Note that the P-type transistor Q1 and the N-type transistor Q4 are transistors for canceling the influence of the threshold value Vth of the P-type transistor Q2 and the N-type transistor Q3. It does not depend on the current value of the constant current source I1 combined with the Q1 and the N-type transistor Q4.
[0050]
FIG. 3 is a characteristic diagram showing a temporal change in the load current flowing in the load circuit obtained using the circuit configuration shown in FIG. 1 and the output voltage at that time. In FIG. 3, the solid line in the output voltage indicates the change in the output voltage in the circuit configuration of the embodiment of the present invention shown in FIG. 2, and the broken line in the output voltage indicates the output voltage in the conventional general constant voltage circuit shown in FIG. (FIG. 4 and FIG. 5 are also the same).
[0051]
An example of a specific physical value of each element used in this example is as follows. The resistance value of the resistors R1 and R2 is 100 MΩ, the capacitance of the capacitors C1 and C2 is 10 pF, and the W / L size of the transistors Q2 and Q3 is 500 μ / The current value of 2 μ and constant current source I1 (constant current source I1 ′) is 1 nA, which is a sufficiently realistic value and can be easily realized.
[0052]
FIG. 4 is an enlarged view of the output voltage when the load current rises in FIG. As shown in the figure, the undershoot and overshoot of the output voltage at the rise of the load current are more in the case of the present circuit configuration (see FIG. 2) than in the case of the conventional general constant voltage circuit. It is decreasing and it turns out that it will be in a stable state more rapidly.
[0053]
FIG. 5 is an enlarged view of the output voltage when the load current falls in FIG. As shown in the figure, the output voltage at the fall of the load current remains elevated in the case of the conventional general constant voltage circuit (see the description of FIG. 9), but the circuit configuration of the present application (see FIG. 4). In the case of), it can be seen that immediately after rising, it decreases and stabilizes.
[0054]
In this way, by providing a high-pass filter composed of a resistor and a capacitor, a differential component is obtained at the time of transient fluctuation of the load current, and the transistor Q2 or Q3 is turned on by this differential component to quickly stabilize the output voltage. As a result, an effective voltage stabilization circuit can be realized.
[0055]
Further, as described above, it is not always necessary to provide both the stabilizing circuit configuration that functions during charging and the stabilizing circuit configuration that functions during discharging, and only one of them may be provided depending on the circuit to be applied. 6 to 8 are diagrams showing examples having only one stabilization circuit configuration. In each of these drawings, (a) is an example having only a stabilization circuit configuration that functions during charging, and (b) is a function during discharging. An example having only a stabilizing circuit configuration is shown.
[0056]
In FIG. 1, FIG. 2, FIG. 6 (a) or FIG. 6 (b), a transistor (P-type transistor Q2 or N-type transistor Q3) that charges or discharges between the high-pass filter and the power supply (Vdd or Vss). There are provided one-conductive saturated-connected transistors (P-type transistor Q1 and N-type transistor Q4) that generate a voltage equivalent to the threshold value Vth, but generate a voltage equivalent to the threshold value Vth. The configuration is not necessarily a transistor, and any voltage source that generates a voltage equivalent to the threshold value Vth may be used.
[0057]
FIG. 7A is a circuit diagram in which a voltage source that generates a voltage equivalent to the threshold value Vth of the transistor Q2 that performs charging is provided between the high-pass filter and the power source Vdd, and FIG. FIG. 6 is a circuit diagram in which a voltage source that generates a voltage equivalent to a threshold value Vth of a transistor Q3 that discharges between power sources Vss is provided. However, if the transistors (Q1, Q4) manufactured by the same process as the transistors (Q2, Q3) for charging and discharging are used as the voltage source as shown in FIGS. As a result, a stabilization circuit that performs stable operation can be obtained.
[0058]
As described above with reference to FIGS. 1, 2, 6, and 7, by canceling the influence of the threshold value Vth of the P-type transistor Q2 and the N-type transistor Q3 by using a transistor or a voltage source. Thus, a voltage stabilizing circuit with a short delay time, a small occupied area, and a very small steady reactive current can be realized. In particular, as shown in FIGS. 1, 2, and 6, if the influence of the threshold voltage Vth of a transistor to be charged / discharged is canceled using a transistor having a similar structure, the process can be performed with a simple configuration. Therefore, it is possible to realize a stable voltage stabilizing circuit that is less susceptible to variations due to.
[0059]
If it is not necessary to cancel the influence of the threshold value Vth of the P-type transistor Q2 and the N-type transistor Q3, a high-pass filter is simply applied to the gate of the charging transistor Q2 as shown in FIG. Alternatively, as shown in FIG. 8B, a high-pass filter may be provided at the gate of the discharging transistor Q3. According to this configuration, the system that controls the node voltage steadily with a very simple configuration has no effect, and when the output node voltage fluctuates transiently due to load fluctuation, In response to this, the output voltage can be stabilized quickly.
[0060]
As described above, the present invention has been described mainly with respect to the embodiment when applied to the voltage stabilization circuit, but the present invention is not limited to the voltage stabilization circuit and the voltage generation circuit described directly, and when voltage fluctuation occurs, The present invention can be applied to all circuits including circuits that need to be stabilized quickly, and a semiconductor device having the same effect can be obtained by incorporating such a voltage stabilizing circuit or voltage generating circuit.
[0064]
【The invention's effect】
  Claim1-3 and 4According to the described invention, when an overshoot or undershoot occurs, the output voltage can be quickly recovered and stabilized, and the configuration is simple, hardly affected by process variations, stable operation, and delay time. A constant voltage generation circuit and a semiconductor device that are short, occupy a small area, and have a very small steady reactive current can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an embodiment of a voltage stabilization circuit according to the present invention.
FIG. 2 is a diagram showing an example in which the constant current source is also used in the modification of FIG.
3 is a characteristic diagram showing a temporal change of a load current flowing in a load circuit obtained using the circuit configuration shown in FIG. 2 and an output voltage at that time. FIG.
4 is an enlarged view showing an output voltage when the load current rises in FIG. 3. FIG.
5 is an enlarged view showing an output voltage when the load current falls in FIG. 3;
FIG. 6 is a diagram showing an example having only one stabilization circuit configuration (part 1: example using a high-pass filter).
FIG. 7 is a diagram showing an example having only one stabilization circuit configuration (part 2: example using a voltage source).
FIG. 8 is a diagram showing an example having only one stabilizing circuit configuration (part 3: example using a transistor);
FIG. 9 is a diagram for explaining a configuration of a conventional general constant voltage circuit.
FIG. 10 is a diagram for explaining a circuit configuration example of an internal voltage down converter, a wiring equivalent circuit, and a load circuit disclosed in Japanese Patent No. 3085562;
FIG. 11 is a diagram for explaining a configuration of a semiconductor integrated circuit including a voltage auxiliary circuit disclosed in Japanese Patent Laid-Open No. 2000-47740.
FIG. 12 is a diagram for explaining an example of a reference voltage generation circuit according to the prior invention (Japanese Patent Application No. 2000-138489).
[Explanation of symbols]
10: Voltage stabilization circuit, 20: Constant voltage circuit, 30: Load circuit,
I1, I1 ′: constant current source, Q1 to Q5: transistors, C1 to C3: capacitors, R1 to R3: resistors, Vdd: power supply (first power supply), Vss: power supply (second power supply), Vout: output Node (or output voltage), Vth: threshold (or voltage source having threshold Vth), A1: error amplifier.

Claims (4)

A constant voltage circuit;
Provided between the output node of the constant voltage circuit and the first power supply, the first electrode is connected to the first power supply, the second electrode is connected to the power supply wiring or the output node, and control A first transistor having an electrode connected to an output point of a first high-pass filter formed between the power supply wiring or the output node and the first power supply;
Provided between the output node of the constant voltage circuit and a second power supply, the first electrode is connected to the second power supply, the second electrode is connected to the power supply wiring or the output node, and control A second transistor having an electrode connected to an output point of a second high-pass filter formed between the power supply wiring or the output node and the second power supply;
A third transistor connected in series between the first power supply and the second power supply, and a fourth transistor connected in saturation with a constant current source or a resistor;
The first high-pass filter is connected to a connection point between the third transistor and the constant current source or resistor;
A constant voltage generation circuit, wherein the second high-pass filter is connected to a connection point between the constant current source or resistor and the fourth transistor. The constant voltage generation circuit according to claim 1 ,
The first and second high-pass filters are each configured by a series connection of a resistor and a capacitor, and the output point of each high-pass filter is a connection point of a resistor and a capacitor. The constant voltage generation circuit according to claim 2 ,
Of resistance and capacitance constituting the respective high-pass filter, the resistor is provided in series between the control electrode of each transistor and the first or second power supply, the capacity and the control electrode of the respective transistors A constant voltage generating circuit, which is provided in series between the power supply wiring or the output node. The semiconductor device having a constant voltage generating circuit according to any one of claims 1 to 3.

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