JPS6070740A - Interelement isolation - Google Patents

Interelement isolation

Info

Publication number
JPS6070740A
JPS6070740A JP17964583A JP17964583A JPS6070740A JP S6070740 A JPS6070740 A JP S6070740A JP 17964583 A JP17964583 A JP 17964583A JP 17964583 A JP17964583 A JP 17964583A JP S6070740 A JPS6070740 A JP S6070740A
Authority
JP
Japan
Prior art keywords
insulating film
groove
film
amorphous silicon
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17964583A
Other languages
Japanese (ja)
Inventor
Shinichi Sato
真一 佐藤
Koji Eguchi
江口　剛治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17964583A priority Critical patent/JPS6070740A/en
Publication of JPS6070740A publication Critical patent/JPS6070740A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Abstract

PURPOSE:To obtain easily an interelement isolation region having a flat surface by a method wherein an amorphous silicon film having thickness of the degree of the half of a groove formed in the main surface part of a semiconductor substrate, and having a flat surface is formed in the groove thereof, and the amorphous silicon film thereof is oxidized or nitrified. CONSTITUTION:When light of mercury lamp, etc. is projected to the base of the groove 4 of a silicon substrate 1, the carriers of electrons and holes are generated. Then, when silane is supplied as reaction gas into a photo CVD device in the condition generated with the carriers at the part under the base of the groove 4 of the silicon substrate 1, SiH4 gas is resolved according to action of the carriers in the base of the groove 4 of the silicon substrate 1 to form an amorphous silicon film 6 as shown in the figure E. At this time, thickness of the amorphous silicon film 6 is made as to be the degree of the half of depth of the groove 4. When the amorphous silicon film 6 is oxidized in an oxygen gas atmosphere, the inside of the groove 4 is buried by volume expansion according to oxidation of the amorphous silicon film 6, and a silicon oxide film 7 to form an interelement isolation region having a flat surface can be obtained finally as shown in the figure F.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体集積回路装置などにおける素子間分離
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for isolating elements in a semiconductor integrated circuit device or the like.

〔従来技術〕[Prior art]

従来、Ｍ　Ｏ８半導体集積回路装置における素子間分離
方法としては、選択酸化分離（ＬＯＣＯ８）方法が用い
られている。ところが、近年、素子が微細化されるにつ
れて、素子間を分離する部分のパターン幅も数μｍ以下
の微細化が必要となってきた。Conventionally, a selective oxidation isolation (LOCO8) method has been used as a method for isolating elements in MO8 semiconductor integrated circuit devices. However, in recent years, as elements have been miniaturized, it has become necessary to miniaturize the pattern width of the portion separating the elements to several μm or less.

このために、ＬＯＣ！Ｏ８方法に替る新しい方法として
、各種の溝掘り素子間分離方法がさかんに提案されてい
る。For this reason, LOC! As a new method to replace the O8 method, various trenching methods for separating elements have been proposed.

第１図（Ａ）〜（Ｅ）は従来の溝堀り素子間分離方法の
一例の王幾段階の状態を示す断面図である。FIGS. 1(A) to 1(E) are cross-sectional views showing various stages of an example of a conventional groove-drilling method for separating elements.

まず、第１図（Ａ）に示すように、シリコン基板１＋）
の主面上に窒化シリコン膜などの第１の絶縁膜（２）を
形成し、この絶縁膜（２）の表面にフォトレジスト膜（
３）を形成する。次いで、フォトレジスト膜（３）のシ
リコン基板（１）の工面部の素子間分離領域を形成すべ
き部分上の部分に開口部（３ａ）を形成する。First, as shown in FIG. 1(A), a silicon substrate 1+)
A first insulating film (2) such as a silicon nitride film is formed on the main surface of the insulating film (2), and a photoresist film (2) is formed on the surface of this insulating film (2).
3) Form. Next, an opening (3a) is formed in a portion of the photoresist film (3) over a portion of the cut surface of the silicon substrate (1) where an element isolation region is to be formed.

次に、第１図ＣＤ）に示すように、開口部（３ａ）が形
成されたフォトレジスト膜（３）をマスクとして、絶縁
膜（２）にエツチングを施して開口部（２ａ）を形成す
る。次に、第１図（Ｃ）に示すように、開口部（２ａ）
が形成された絶縁膜（２）をマスクとした反応性イオニ
／エツチング（Ｒｅａｃｔｉｖｅ工ｏｎ　Ｅｔｃｈｉｎ
ｇ　：　Ｒ工Ｅ）法によって、シリコン基板＋１）の工
面部に０．５〜１．０μｍ程度の深さを有する溝（４）
を形成する。次に、面する部分上および絶縁膜（２）の
表面上Ｇこわたって０．５〜１．０μｍ程度の厚さを有
する酸化シリコン膜などの第２の絶縁膜（５）をＣＶＤ
法などを用いて形成する。最後に、第１図（Ｅ）に示す
ように、ＲＩＥ法を用いて、絶縁膜（２）の主面が露出
するように、絶縁膜（５）をエツチング除去して、溝（
４）内に素子間分離用の絶縁膜６１）を残すと、この従
来例の方法の作業が終了する。Next, as shown in FIG. 1CD), using the photoresist film (3) in which the opening (3a) is formed as a mask, the insulating film (2) is etched to form the opening (2a). . Next, as shown in FIG. 1(C), the opening (2a)
Reactive ionization/etching using the insulating film (2) on which is formed as a mask
g: A groove (4) having a depth of approximately 0.5 to 1.0 μm is formed in the machined surface of the silicon substrate +1) by the R engineering E) method.
form. Next, a second insulating film (5) such as a silicon oxide film having a thickness of about 0.5 to 1.0 μm is deposited on the facing portion and over the surface of the insulating film (2) by CVD.
Formed using methods such as methods. Finally, as shown in FIG. 1(E), the insulating film (5) is etched away using the RIE method so that the main surface of the insulating film (2) is exposed.
When the insulating film 61) for isolation between elements is left in 4), the work of this conventional method is completed.

ところで、この従来例の方法では、第１図ＣＤ）に示し
た絶縁膜（５）の形成段階において、絶縁膜（５）の厚
さと溝（４）の深さおよび幅との関係によっては、絶縁
膜（６）の表面部の溝（４）の中央部に対応する部分に
第１図（Ｄ）に符号イで例示するような凹部ができ、こ
の凹部（イ）を、第１図（Ｋ）に示した段階において、
全部除去することができす、凹部（イ）の一部が絶縁膜
いυの表面部に残り、絶縁膜Ｇ〃の表面部に凹凸ができ
る。従って、絶縁膜６】）の表面部に残った四部（イ）
の一部を埋めて絶縁膜−の表面を平坦にするためには、
更に工程を追加する必要があり、この従来例の方法の実
用化が容易ではないという欠点があった。By the way, in this conventional method, depending on the relationship between the thickness of the insulating film (5) and the depth and width of the groove (4), at the stage of forming the insulating film (5) shown in FIG. A recess as illustrated by reference numeral A in FIG. 1(D) is formed in a portion of the surface of the insulating film (6) corresponding to the central portion of the groove (4), and this recess (A) is designated by the symbol A in FIG. 1(D). At the stage shown in K),
However, part of the recess (a) remains on the surface of the insulating film υ, creating unevenness on the surface of the insulating film G. Therefore, the four parts (a) remaining on the surface of the insulating film 6])
In order to flatten the surface of the insulating film by filling a part of it,
Further, it is necessary to add a step, and this conventional method has the disadvantage that it is not easy to put it into practical use.

〔発明の概５−〕 この発明は、かかる欠点を除去する目的でなされたもの
で、半導体基板の主面部の素子間分離領域を形成すべき
部分Ｇこ形成された溝の底面上に溝の深さの半分程度の
厚さを有し平坦な表面のアモルファスシリコン膜を選択
的に形成し、このアモルファスシリコン膜を酸化または
象化することによって、溝内を埋め平坦な表面を有する
素子間分離領域を形成する酸化シリコン膜または窒化シ
リコン阪を得ることかできる素子間分離方法を提供する
ものである。[Summary of the Invention 5-] This invention has been made for the purpose of eliminating such drawbacks, and includes forming a groove on the bottom surface of the groove formed in the portion G on the main surface of the semiconductor substrate where the isolation region between elements is to be formed. By selectively forming an amorphous silicon film with a flat surface and a thickness of about half the depth, and oxidizing or oxidizing this amorphous silicon film, the inside of the trench is filled and element isolation with a flat surface is created. An object of the present invention is to provide a device isolation method that can obtain a silicon oxide film or a silicon nitride film forming a region.

〔発明の実施例〕[Embodiments of the invention]

第２図（Ａ）〜（Ｆｌ）はこの発明の一実施例の素子間
分前方法の王妥段階の状態を示す断面図である。FIGS. 2A to 2F are cross-sectional views showing the final stage of the inter-element dividing method according to an embodiment of the present invention.

図において、第１図に示した従来例と同一符号は同等部
分を示す。In the figure, the same reference numerals as in the conventional example shown in FIG. 1 indicate equivalent parts.

まず、第２図（Ａ）に示すように、第１図（０）に示し
た段階における状態と同様の状態にｌｂ成する。次に、
第２図（Ｂ）に示すように、この実施例での半導体基板
であるシリコン基板（１）の溝（４）に面する部分上お
よび第１の絶縁膜（２）の表面上にわたって酸化シリコ
ン膜などの比較的厚さの薄い第２の絶縁膜（５）をＣＶ
Ｄ法などを用いて形成する。次に、第２図（０）に示す
ように、絶縁膜（５）に図示矢印の方向から反応性ガス
のイオンを照射するＲＩＫ法によって、絶縁膜（５）の
溝（４）の底面上の部分および絶縁膜（２）の主面上の
部分を除去し、絶縁膜（６）の溝（４）の側壁面上の部
分を残して絶縁膜（５ａ）とする。次に、第２図（Ｄ）
に示すように、第２図（ｃ）に示した状態に形成された
シリコン基板＋１）を光ｃｖＤ装憤（図示せず）内に設
置し、シリコン基板＋１１の溝（４）の底面の部分に水
銀ランプなどの光発生管（図示せず）が発生ずる図示矢
印の光を照射する。水銀ランプの場合には、波長λが約
２５０ＯＡで、エネルギーｈνが約０．５　ｅＶでおる
。First, as shown in FIG. 2(A), lb is formed into a state similar to the state at the stage shown in FIG. 1(0). next,
As shown in FIG. 2(B), silicon oxide is applied over the portion facing the groove (4) of the silicon substrate (1), which is the semiconductor substrate in this example, and over the surface of the first insulating film (2). A relatively thin second insulating film (5) such as a film is
It is formed using the D method or the like. Next, as shown in FIG. 2(0), the bottom surface of the groove (4) of the insulating film (5) is exposed to the bottom surface of the groove (4) of the insulating film (5) using the RIK method in which the insulating film (5) is irradiated with reactive gas ions from the direction of the arrow shown in the figure. The portion and the portion on the main surface of the insulating film (2) are removed, leaving a portion of the insulating film (6) on the side wall surface of the groove (4) to serve as an insulating film (5a). Next, Figure 2 (D)
As shown in FIG. 2(c), the silicon substrate +1) formed in the state shown in FIG. A light generating tube (not shown) such as a mercury lamp emits light generated by the arrow shown in the figure. In the case of a mercury lamp, the wavelength λ is about 250 OA and the energy hν is about 0.5 eV.

このように、光が照射されたシリコン基板（１）の溝（
４）の底面下の部分には、照射光のエネルギ−１ｊｙｔ
手（ｒＡ承０） によって、正孔（図示■）や項畦眞河勾？ヤリャが発生
する。In this way, the grooves (
4) The energy of the irradiation light is -1jyt in the bottom part.
Depending on the hand (rA 0), the hole (diagram ■) or the direction of the river? Yarya occurs.

次に、第２図（Ｅ）に示すように、シリコン基板Ｈの溝
（４）の底面下の部分にキャリヤが発生した状態におい
て、光ＣＶＤ装置内に反応ガスとしてシラン（ＳｉＨ４
）を供給すると、Ｓ　ｉＨ４がシリコン基板＋ｌ）の溝
（４）の底面を形成する部分、絶縁膜（２）および絶縁
膜（５ａ）の表面上に付着するが、シリコン基板（１）
の溝（４）の底面下の部分に発生したキャリヤの作用に
よってこの部分に付着したＳｉＨ４の、アモルファスシ
リコンを反応生成物とする分解反応（ＥＩｉＨ４−８１
＋２Ｈ２）が促進されるので、このアモルファスシリコ
ンによってシリコン基板（１）の溝（４）の底面を形成
する部分上に選択的に平坦な表面を有するアモルファス
シリコン膜（６）が形成される。このとき、アモルファ
スシリコン膜（６）の厚さが溝（４）の深さの半分程度
になるようにする。Next, as shown in FIG. 2(E), in a state where carriers are generated under the bottom surface of the groove (4) of the silicon substrate H, silane (SiH4
), SiH4 adheres to the part forming the bottom of the groove (4) of the silicon substrate +l), and on the surfaces of the insulating film (2) and the insulating film (5a), but the silicon substrate (1)
The decomposition reaction (EIiH4-81
+2H2) is promoted, so that an amorphous silicon film (6) having a selectively flat surface is formed on the portion of the silicon substrate (1) forming the bottom surface of the trench (4). At this time, the thickness of the amorphous silicon film (6) is made to be approximately half the depth of the groove (4).

最後に、第２図（Ｆ）に示すように、アモルファスシリ
コン膜（６）を酸素ガスの雰囲気中で酸化させて酸化シ
リコン膜（７）にすると、この実施例の方法の作業が終
了する。Finally, as shown in FIG. 2(F), the amorphous silicon film (6) is oxidized in an oxygen gas atmosphere to form a silicon oxide film (7), thereby completing the process of this embodiment.

この実施例の方法では、溝（４）の深さの半分程度の厚
さを有し平坦な表面のアモルファスシリコン膜（６）を
酸化させるので、アモルファスシリコン膜（６）の酸化
による体積膨張によって溝（４）内を埋め平坦な表面を
有する素子間分離領域を形成する酸化シリコン膜（７）
を得ることができる。In the method of this embodiment, since the amorphous silicon film (6) having a flat surface and having a thickness of about half the depth of the groove (4) is oxidized, the volume expansion due to oxidation of the amorphous silicon film (6) causes A silicon oxide film (7) that fills the trench (4) and forms an interelement isolation region with a flat surface.
can be obtained.

この実施例では、シリコン基板（１）を用いたが、必ず
しもシリコン基板である必要がなく、その他の半導体基
板であってもよい。Although a silicon substrate (1) is used in this embodiment, it does not necessarily have to be a silicon substrate, and other semiconductor substrates may be used.

また、この実施例では、アモルファスシリコン膜（６）
を酸化して酸化シリコン膜（７）にしたが、必ずしもこ
れは酸化シリコン膜である必要がなく、窒化して窒化シ
リコン膜にしてもよい。In addition, in this example, the amorphous silicon film (6)
Although oxidized to form a silicon oxide film (7), this does not necessarily have to be a silicon oxide film, and may be nitrided to form a silicon nitride film.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように、この発明の素子間分離方法では
、半導体基板の主面部の素子間分離領域を形成すべき部
分に形成された溝の底面上に溝の深さの半分程度の厚さ
を有し平坦な表面のアモルファスシリコン膜を選択的に
形成し、このアモルファスシリコン膜を酸化または窒化
するので、酸化シリコン膜または窒化シリコン膜からな
り溝内を埋め平坦な表面を有する素子間分離領域を得る
ことができる。As described above, in the device isolation method of the present invention, a thickness of approximately half the depth of the trench is formed on the bottom surface of the trench formed in the portion of the main surface of the semiconductor substrate where the device isolation region is to be formed. By selectively forming an amorphous silicon film with a flat surface and oxidizing or nitriding this amorphous silicon film, an element isolation region made of a silicon oxide film or a silicon nitride film and filling the trench and having a flat surface is formed. can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の素子間分離方法の一例の主要段階の状態
を順次示す断面図、第２図はこの発明の一実施例の素子
間分離方法の主要段階の状態を順次示す断面図である。 図において、（１）はシリコン基板（半導体基板）、（
２）は第１の絶縁膜、（２ａ）は開口部、（４）は溝、
（５）は第２の絶縁膜、（５ａ）は溝（４）の側壁面上
に残された絶縁膜、（６）はアモルファスシリコン膜、
（７）は酸化シリコン膜である。 なお、図中同一符号はそれぞれ同一または相自部分を示
す。 代理人　大岩増雄 第１図 第１図 第２図 （ｅ） 手続補正書（自発） １．事件の表示　特願昭５８−１７９６４５号２・発明
の名称素子間分離方法 ３、補正をする者 事件との関係　特許畠願人 住　所　東京都千代田区丸の内二丁目２番３号名　称　
（６０１）三菱電機株式会社 代表者片山仁八部 ４、代理人 ５、補正の対象 明細書の特許請求の範囲の欄 ６、補正の内容 （１）明細書の特許請求の範囲を添付別紙のとお９に訂
正する。 ７、添付書類の目録 訂正後の特許請求の範囲を示す書面　１通以　上 特許請求の範囲 （１）　半導体基板の主面上に第１の絶縁膜を形成する
工程、この第１の絶縁膜の上記半導体基板の主面部の素
子間分離領域を形成すべき部分に開口部を形成する工程
、この開口部が形成された上記第１の絶縁膜をマスクと
した反応性イオンエツチング法によって上記半導体基板
の主面部に溝を形成する工程、上記半導体基板の上記溝
に面する部分上および上記第１の絶縁膜の表面上にわた
って第２の絶縁膜を形成する工程、この第２の絶縁膜に
反応性イオンエツチング法を施して上記第２の絶縁膜の
上記溝の底面上の部分および上記第ユの絶縁膜の主面上
の部分を除去し上記第２の絶縁膜の上記溝の側壁面上の
部分を残す工程、上記のように処理された上記半導体基
板を光ＯＶＤ装置内に設置し上記半導体基板の上記第２
の絶縁膜が除去された上記溝の底面下の部分に光を照射
してキャリヤを発生させる工程、上記光ＯＶＤ装置内に
シランを供給しアモルファスシリコンを反応生成物と作
用によって促進させ上記半導体基板の上記第２の絶縁膜
が除去された上記溝の底面を形成する部分上に選択的に
上記溝の深さの半分程度の厚さを有し平坦な表面のアモ
ルファスシリコン膜’ｃ形成する工程、並びにこのアモ
ルファスシリコン膜を酸化または窒化して酸化シリコン
膜または窒化シリコン膜からなる素子間分離領域を形成
する工程を備えた素子間分離方法。FIG. 1 is a cross-sectional view sequentially showing the main stages of an example of a conventional device isolation method, and FIG. 2 is a cross-sectional view sequentially showing the main steps of an example of the device isolation method of the present invention. . In the figure, (1) is a silicon substrate (semiconductor substrate), (
2) is the first insulating film, (2a) is the opening, (4) is the groove,
(5) is the second insulating film, (5a) is the insulating film left on the side wall surface of the groove (4), (6) is the amorphous silicon film,
(7) is a silicon oxide film. Note that the same reference numerals in the figures indicate the same or similar parts. Agent Masuo Oiwa Figure 1 Figure 1 Figure 2 (e) Procedural amendment (voluntary) 1. Display of the case Japanese Patent Application No. 58-179645 2. Name of the invention Inter-element separation method 3. Person making the amendment Relationship to the case Patent applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name Name
(601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 4, Agent 5, Claims column 6 of the specification to be amended, Contents of the amendment (1) Claims of the specification in the attached appendix. Corrected to 9. 7. Document showing the scope of claims after the list of attached documents has been corrected One or more copies Claims (1) Process of forming a first insulating film on the main surface of a semiconductor substrate, this first insulating film forming an opening in a portion of the main surface of the semiconductor substrate where an element isolation region is to be formed; etching the semiconductor by reactive ion etching using the first insulating film in which the opening is formed as a mask; forming a groove in the main surface of the substrate; forming a second insulating film over the portion of the semiconductor substrate facing the groove and over the surface of the first insulating film; A reactive ion etching method is applied to remove a portion of the second insulating film on the bottom surface of the groove and a portion on the main surface of the first insulating film to remove the sidewall surface of the groove of the second insulating film. A step of leaving the upper part of the semiconductor substrate, placing the semiconductor substrate processed as described above in an optical OVD apparatus, and leaving the upper part of the semiconductor substrate
A step of generating carriers by irradiating a portion under the bottom surface of the groove from which the insulating film has been removed, and supplying silane into the optical OVD apparatus to promote amorphous silicon by interaction with a reaction product of the semiconductor substrate. selectively forming an amorphous silicon film 'c having a thickness of about half the depth of the trench and having a flat surface on the portion forming the bottom surface of the trench from which the second insulating film has been removed; and a step of oxidizing or nitriding the amorphous silicon film to form an element isolation region made of a silicon oxide film or a silicon nitride film.

Claims (1)

【特許請求の範囲】[Claims] ＋１）　半導体基板の主面上に第１の絶縁膜を形成する
工程、この第１の絶縁膜の上記半導体基板の工面部の素
子間分離領域を形成すべき部分に開口部を形成する工程
、この開口部が形成された上記第１の絶縁膜をマスクど
した反応性イオンエツチング法によって上記半導体基板
の主面部に溝を形成する工程、上記半導体基板の上記溝
に面する部分上および上記第１の絶縁膜の表面上にわた
って第２の絶縁膜を形成する工程、この第２の絶縁膜に
反応性イオンエツチング法を施して上記第２の絶縁膜の
上記溝の底面上の部分および上記第１の絶縁膜の主面上
の部分を除去し上記第２の絶縁膜の上記溝の側壁面上の
部分を残す工程、上記のように処理された上記半導体基
板を光ＣＶＤ装餉内に設置し上記半導体基板の上記第２
の絶縁膜が除去された上記溝の底面下の部分に光を照射
してキャリヤを発生させる工程、上記光ＣＶＤ装置内に
シランを供給しアモルファスシリコンを反応生成物とす
るシランの分解反応の発生した上記キャリヤの作用によ
る促進によって上記半導体基板の上記第２の絶縁膜が除
去された上記溝の底面を形成する部分上に選択的に上記
溝の深さの半分程度の厚さを有し平坦な表面のアモルフ
ァスシリコン膜を形成する工程、並びにこのアモルファ
スシリコン膜を酸化または窒化して酸化シリコン膜また
は留化シリコン膜からなる素子間分離領域を形成する工
程を備えた素子間分離方法。+1) a step of forming a first insulating film on the main surface of the semiconductor substrate; a step of forming an opening in a portion of the first insulating film in a section of the semiconductor substrate where an element isolation region is to be formed; forming a groove on the main surface of the semiconductor substrate by a reactive ion etching method using the first insulating film in which the opening is formed as a mask; forming a second insulating film over the surface of the first insulating film; performing reactive ion etching on the second insulating film to remove the portions of the second insulating film on the bottom surface of the groove and the second insulating film; removing a portion of the first insulating film on the main surface and leaving a portion of the second insulating film on the side wall surface of the groove; placing the semiconductor substrate treated as described above in a photo-CVD equipment; and the second part of the semiconductor substrate.
A step of generating carriers by irradiating a portion under the bottom surface of the groove from which the insulating film has been removed, and a step of supplying silane into the photo-CVD apparatus and generating a decomposition reaction of silane with amorphous silicon as a reaction product. selectively form a flat surface having a thickness of about half the depth of the groove on a portion forming the bottom surface of the groove from which the second insulating film of the semiconductor substrate has been removed by the action of the carriers; A device isolation method comprising the steps of forming an amorphous silicon film with a surface having a uniform surface, and oxidizing or nitriding the amorphous silicon film to form a device isolation region made of a silicon oxide film or a silicon oxide film.
JP17964583A 1983-09-26 1983-09-26 Interelement isolation Pending JPS6070740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17964583A JPS6070740A (en) 1983-09-26 1983-09-26 Interelement isolation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17964583A JPS6070740A (en) 1983-09-26 1983-09-26 Interelement isolation

Publications (1)

Publication Number Publication Date
JPS6070740A true JPS6070740A (en) 1985-04-22

Family

ID=16069386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17964583A Pending JPS6070740A (en) 1983-09-26 1983-09-26 Interelement isolation

Country Status (1)

Country Link
JP (1) JPS6070740A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08139176A (en) * 1994-11-03 1996-05-31 Lg Semicon Co Ltd Manufacture of semiconductor device
JPH0964165A (en) * 1995-08-30 1997-03-07 Nec Corp Fabrication method of semiconductor device
US5872052A (en) * 1996-02-12 1999-02-16 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
JP2000340648A (en) * 1999-05-13 2000-12-08 Stmicroelectronics Inc Improved integrated circuit isolating structure and manufacture thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08139176A (en) * 1994-11-03 1996-05-31 Lg Semicon Co Ltd Manufacture of semiconductor device
JPH0964165A (en) * 1995-08-30 1997-03-07 Nec Corp Fabrication method of semiconductor device
US5872052A (en) * 1996-02-12 1999-02-16 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
US6194305B1 (en) 1996-02-12 2001-02-27 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
US6777346B2 (en) 1996-02-12 2004-08-17 Micron Technology, Inc. Planarization using plasma oxidized amorphous silicon
JP2000340648A (en) * 1999-05-13 2000-12-08 Stmicroelectronics Inc Improved integrated circuit isolating structure and manufacture thereof

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