JPS60253230A - Formation of fine pattern - Google Patents
Formation of fine patternInfo
- Publication number
- JPS60253230A JPS60253230A JP11175884A JP11175884A JPS60253230A JP S60253230 A JPS60253230 A JP S60253230A JP 11175884 A JP11175884 A JP 11175884A JP 11175884 A JP11175884 A JP 11175884A JP S60253230 A JPS60253230 A JP S60253230A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- gas
- etching
- fine pattern
- plasma reaction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000007795 chemical reaction product Substances 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 16
- 239000012495 reaction gas Substances 0.000 claims description 3
- 230000007261 regionalization Effects 0.000 claims 1
- 239000012212 insulator Substances 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052753 mercury Inorganic materials 0.000 abstract description 3
- 229910004014 SiF4 Inorganic materials 0.000 abstract description 2
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 abstract description 2
- ATVLVRVBCRICNU-UHFFFAOYSA-N trifluorosilicon Chemical compound F[Si](F)F ATVLVRVBCRICNU-UHFFFAOYSA-N 0.000 abstract 1
- 230000001678 irradiating effect Effects 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体基板中にプラズマ反応を利用して、
エツチングにより幅の狭い、深い溝からなる微細パター
ンを形成する方法に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention utilizes a plasma reaction in a semiconductor substrate to
This invention relates to a method of forming a fine pattern consisting of narrow and deep grooves by etching.
従来、ＳＳ 基板中に溝を形成する場合−ＣＦ４等のガ
スを用いてエツチングしていたが、幅が狭（て、深さの
ある溝を形成する際に反応が充分進まないために所望の
形状が得らｎない欠点がありに０
第１図（ａ）〜（ｃ）は従来の微細パターン形成方法の
概略を工程順に示す断面図である。Conventionally, when forming grooves in SS substrates, gas such as CF4 was used for etching, but the reaction did not proceed sufficiently when forming grooves with narrow width and depth. Figures 1(a) to 1(c) are cross-sectional views showing the outline of a conventional fine pattern forming method in the order of steps.
まず、第１図（ａ）に示すようＫＳｉ基板１上に所望の
形状の耐エツチング性マスク２ン形成し、このＳｋ基板
１をプラズマ反応室に入れる。次に、このプラズマ反応
室内に、ＣＦ４ 等のエツチングガスを導入して、反応
式（１）Ｋよって活性化されｋＣＦ４→ＣＦ３＋Ｆ＊
・・・・・・・・・・・・・・・・・・・・・（１）Ｓ
ｉ＋ＣＦ４→ＳｉＦ４↑十Ｃ・・・・・・・・・・・・
・・・（２）フッ素（Ｆ＊）Ｙ発生させ、Ｓｔ基板１と
反応させると、反応式（２）Ｋ示すように反応生成ガス
ＳｉＦ。First, as shown in FIG. 1(a), an etching-resistant mask 2 of a desired shape is formed on a KSi substrate 1, and this Sk substrate 1 is placed in a plasma reaction chamber. Next, an etching gas such as CF4 is introduced into the plasma reaction chamber, and the etching gas is activated according to the reaction formula (1) K.
・・・・・・・・・・・・・・・・・・・・・(1)S
i+CF4→SiF4↑10C・・・・・・・・・・・・
...(2) When fluorine (F*)Y is generated and reacted with the St substrate 1, the reaction product gas SiF as shown in reaction formula (2)K.
を発生しながら反応が進み、ＳＳ基板１がエツチングさ
れ、第１図（ｂ）に示すよう妊溝３が形成される。その
後、第１図（ｃ） ＶＣ示すように絶縁物４で溝３を埋
めて平坦化しに後、この絶縁物４の領域を電気的分離領
域とし、その他の活性領域にゲート電極５．ソース・ド
レイン拡散層６等からなるＭＯＳ）ランジスタ等を形成
し、半導体素子として使用する。The reaction progresses while generating etchants, and the SS substrate 1 is etched, forming a groove 3 as shown in FIG. 1(b). After that, as shown in FIG. 1(c) VC, the trench 3 is filled with an insulator 4 and planarized, and then the region of the insulator 4 is used as an electrical isolation region, and the other active regions are covered with gate electrodes 5. A MOS (MOS) transistor etc. consisting of source/drain diffusion layers 6 etc. is formed and used as a semiconductor element.
次に第１図の方法によって、幅の狭い形状の溝を形成す
る場合の問題点について第２図を用いて説明する。Next, problems when forming narrow grooves by the method shown in FIG. 1 will be explained with reference to FIG. 2.
第２図（ａ）は第１図（ａ）と同じ（８１基板１Ｖｃ幅
の狭いパターンを耐エツチング性マスク２ｙ１１′用い
て形成し、レラズマ反応室に入ｎる。このプラズマ反応
室において、ＣＦ４ ガスを導入し、Ｓｉ基板ＩＹエツ
チングする場合、溝３の深さがある程度以上になると、
ＣＦ４（ＣＦ、＋Ｆ”）が充分に供給されないＫめＫ、
第２図（ｂ）の破線で示したような所望の深さに到達す
る前にエツチングが停止し°（しまい、所望の深さの溝
３が得られない。その結果、第２図（ｅ）Ｋ示すようた
半導体素子を形成した場合、絶縁物４の領域が分離領域
として電気的に充分な機能を果に丁ことかできない欠点
を有している。FIG. 2(a) is the same as FIG. 1(a) (81 substrate 1Vc is formed with a narrow pattern using an etching-resistant mask 2y11' and entered into a plasma reaction chamber. In this plasma reaction chamber, CF4 When introducing gas to perform IY etching of the Si substrate, if the depth of the groove 3 exceeds a certain level,
KmeK where CF4 (CF, +F") is not sufficiently supplied,
The etching stops before reaching the desired depth as shown by the broken line in FIG. 2(b), and the groove 3 of the desired depth cannot be obtained. )K When a semiconductor element as shown in FIG.
この発明は、上記欠点ン除去するためになさｎｋもので
、プラズマ反応中に宛とえば水銀ランプ等から発てる短
波長の−ＸＶ照射することにより、プラズマ反応を促進
し、所望の形状のパターンを得ることができる微細パタ
ーン形成方法を提供するものである。以下第３図を用い
てこの発明の一実施例を説明する。This invention was made in order to eliminate the above-mentioned defects, and by irradiating -XV with a short wavelength emitted from a mercury lamp or the like during a plasma reaction, the plasma reaction is accelerated and a pattern of a desired shape is formed. The purpose of the present invention is to provide a method for forming a fine pattern that can obtain the following. An embodiment of the present invention will be described below with reference to FIG.
第３ 図（ａ）〜（ｃ）はこの発明の一実施例による微
細パターン形成方法を工程ＩＦ［示した断面図である。FIGS. 3(a) to 3(c) are cross-sectional views showing the process IF of a fine pattern forming method according to an embodiment of the present invention.
第３図（ａ）のように第１図（ａ）および第２図（ａ）
と同じく、Ｓｉ基板１上に耐エツチング性マスク２を形
成した後、第３図（ｂ） Ｋ示すように、プラズマ反応
室中で、ＣＦ４ガスを導入してＳｉ基板１ｔエツチング
する。この際、例えば水銀ランプ等から発生させたλ：
＝２５３７Ａ程度の波長の光ｈｖをこのＳｉ基板１の全
面から照射てると反応式（ａ）Ｋ示すようＫ、
Ｓｉ＋ＣＦ４→８ ｉ Ｆ、 ＋Ｆ＊十Ｃ・−・・・・
・・・（３）反応生成ガスであるＳｉＦ、が５ｉＦ１と
Ｆ ＶＣさらに分解される。ここで発生した新友な活性
ガスであるＦ＊が溝３の深い部分にも充分供給され、第
３図（ｂ）ＶＣ示すように所望の深さまでエツチングを
進行させることができる。その結果、第３図（ｃ）に示
すように所望の幅と深さｔ有する溝３が形成さｎ、この
溝３の部分を絶縁物４で充填し、所定の領域にゲート電
極５．ソース・ドレイン拡散層６を形成して半導体素子
を完成させることかできる。 。As shown in FIG. 3(a), FIG. 1(a) and FIG. 2(a)
Similarly, after forming the etching-resistant mask 2 on the Si substrate 1, as shown in FIG. 3(b) K, CF4 gas is introduced into the plasma reaction chamber and the Si substrate 1t is etched. At this time, for example, λ generated from a mercury lamp or the like:
When light hv with a wavelength of approximately 2537 A is irradiated from the entire surface of this Si substrate 1, the reaction formula (a) K is shown as K, Si + CF4 → 8 i F, +F * 10 C...
...(3) SiF, which is a reaction product gas, is further decomposed into 5iF1 and FVC. The new active gas F* generated here is sufficiently supplied to the deep part of the groove 3, and etching can proceed to a desired depth as shown by VC in FIG. 3(b). As a result, a groove 3 having a desired width and depth t is formed as shown in FIG. 3(c), a portion of this groove 3 is filled with an insulator 4, and a gate electrode 5 is formed in a predetermined area. The semiconductor device can be completed by forming the source/drain diffusion layer 6. .
なお、この発明ではＳｔ 基板中に溝を形成する場合に
ついて述べたが、プラズマ反応によって微細な形状の深
い溝あるいは穴を形成する場合において、反応生成ガス
が元によって分解し、新たな反応活性ガスを生成丁′る
方法に対しては、丁ぺて適用できることは勿論である。In this invention, the case of forming grooves in the St substrate has been described, but when forming deep grooves or holes with minute shapes by plasma reaction, the reaction generated gas decomposes depending on the source, and new reactive active gas is generated. Of course, it can be applied to any method for generating .
まＬ、半導体基板と叫てはＳｉ基板に限るものではない
。Well, the term "semiconductor substrate" is not limited to Si substrates.
以上詳細に説明したように、この発明は基板の一部を耐
エツチング性マスクで覆い、プラズマ反応によって一定
の深さの溝を有する微細パターンを形成する方法におい
て、プラズマ反応中に基板全面に元を照射して前記微細
パターン形成中の溝内の反応生成ガスを分解することに
より、新たな活性ガスを生成して所望の深さの溝の微細
パターンを形成する方法であるから１反応ガスが充分供
給されない幅の狭い、深い溝を形成する際に、溝中の反
応生成ガスを元か分解し、新たな反応ガスを生成し、溝
内に供給することができるので、微細パターンでも所望
の形状にエツチングすることができる利点がある。As explained in detail above, the present invention covers a part of a substrate with an etching-resistant mask and uses a plasma reaction to form a fine pattern having grooves of a certain depth. This is a method in which a new active gas is generated by irradiating the gas to decompose the reaction generated gas in the grooves during the formation of the fine pattern, thereby forming a fine pattern of grooves with a desired depth. When forming narrow and deep grooves that are not sufficiently supplied, it is possible to decompose the reaction gas in the grooves, generate new reaction gas, and supply it into the grooves, so even fine patterns can be formed. It has the advantage of being able to be etched into shapes.
第１図（ｈ）〜（ｃ）は従来の微細パターン形成方法の
概略を工程順に示す断面図、第２図（ａ）〜（ｃ）は第
１図の微細パターン形成方法の欠点を工程順ＶＣ説明す
るＫめの断面図、第３図（ａ）〜（ｃ）はこの発明の一
実施例の微細パターン形成方法な工程順に示す断面図で
ある。
図中、１はＳｉ基板、２は耐エツチング性マスク、３は
溝、４は絶縁物、５はゲート電極、６はソース・ドレイ
ン拡散層である。
なお、図中の同一符号は同一または相当部分を示す。
代理人 大岩増雄 （外２名）
第１図
（ａ）
（Ｃ）
第２図
（ａ）
第３図
（ａ）
（ｃ）
らFigures 1 (h) to (c) are cross-sectional views showing an outline of the conventional fine pattern forming method in the order of steps, and Figures 2 (a) to (c) show the shortcomings of the fine pattern forming method in Figure 1 in the order of the steps. 3(a) to 3(c) are cross-sectional views showing the steps of a fine pattern forming method according to an embodiment of the present invention. In the figure, 1 is a Si substrate, 2 is an etching-resistant mask, 3 is a groove, 4 is an insulator, 5 is a gate electrode, and 6 is a source/drain diffusion layer. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 (a) (C) Figure 2 (a) Figure 3 (a) (c) et al.
Claims (2)
ガスを用いプラズマ反応によって一定の深さの溝を有す
る微細パターンを形成する方法において、前記プラズマ
反応中に前記基板全面に元を照射して前記パターン形成
中の溝内の反応生成ガスを分解することにより、新たな
反応ガスを生成させて所望の深さの溝を有する微細パタ
ーンを形成することを特徴とする微細パターン形成方法
。(1) In a method in which a part of the substrate is covered with an etching-resistant mask and a fine pattern having grooves of a certain depth is formed by a plasma reaction using a reactive gas, the entire surface of the substrate is irradiated with a source during the plasma reaction. A method for forming a fine pattern, characterized in that a new reaction gas is generated by decomposing the reaction product gas in the grooves during pattern formation to form a fine pattern having grooves of a desired depth.
であることを特徴とする特許請求の範囲第（１１項記載
の微細パターン形成方法。(2) The substrate is a Si semiconductor, and the reactive gas is CF4
A fine pattern forming method according to claim 11, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11175884A JPS60253230A (en) | 1984-05-29 | 1984-05-29 | Formation of fine pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11175884A JPS60253230A (en) | 1984-05-29 | 1984-05-29 | Formation of fine pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60253230A true JPS60253230A (en) | 1985-12-13 |
Family
ID=14569440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11175884A Pending JPS60253230A (en) | 1984-05-29 | 1984-05-29 | Formation of fine pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60253230A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155144A (en) * | 2016-12-02 | 2018-06-12 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50130370A (en) * | 1974-04-01 | 1975-10-15 | ||
| JPS5789476A (en) * | 1980-11-21 | 1982-06-03 | Toshiba Corp | Dry etching method |
| JPS583233A (en) * | 1981-06-05 | 1983-01-10 | インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン | Etching method |
-
1984
- 1984-05-29 JP JP11175884A patent/JPS60253230A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50130370A (en) * | 1974-04-01 | 1975-10-15 | ||
| JPS5789476A (en) * | 1980-11-21 | 1982-06-03 | Toshiba Corp | Dry etching method |
| JPS583233A (en) * | 1981-06-05 | 1983-01-10 | インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン | Etching method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155144A (en) * | 2016-12-02 | 2018-06-12 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
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