JPH0644591B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0644591B2 JPH0644591B2 JP59113003A JP11300384A JPH0644591B2 JP H0644591 B2 JPH0644591 B2 JP H0644591B2 JP 59113003 A JP59113003 A JP 59113003A JP 11300384 A JP11300384 A JP 11300384A JP H0644591 B2 JPH0644591 B2 JP H0644591B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- sio
- film
- gas
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title description 17
- 239000004065 semiconductor Substances 0.000 title description 15
- 238000004519 manufacturing process Methods 0.000 title description 5
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 23
- 238000001020 plasma etching Methods 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000007789 gas Substances 0.000 description 22
- 238000005530 etching Methods 0.000 description 18
- 238000002955 isolation Methods 0.000 description 9
- 239000012495 reaction gas Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置に関し、特に溝を利用することによ
って高集積化を達成することのできる半導体装置の製造
方法に関するものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a semiconductor device which can achieve high integration by utilizing a groove.
ＬＳＩ，ＶＬＳＩ等の半導体装置の高集積化に伴って、
回路パターンも益々微細化が進められ、サブミクロン単
位での回路パターンが要求されてきている。With the high integration of semiconductor devices such as LSI and VLSI,
Circuit patterns are becoming finer and finer, and circuit patterns in submicron units are required.
半導体装置を形成する場合、半導体基板に溝（穴を含
む）を形成し、この溝内に絶縁材を充填して回路素子を
形成することが提案されている。例えば素子間分離用の
絶縁領域，キャパシタ等が挙げられている。When forming a semiconductor device, it has been proposed to form a groove (including a hole) in a semiconductor substrate and fill the groove with an insulating material to form a circuit element. For example, an insulating region for element isolation, a capacitor and the like are mentioned.
このため、この種の回路素子を形成する場合には溝を微
細に、つまり細幅に形成することが要求される。ところ
で、一方では素子分離効果を高め、或いは大容量のキャ
パシタを得るためには溝の深さを深くすることが要求さ
れることになる。結局、微細幅でかつできるだけ深い溝
が要求されることになる。Therefore, when forming this type of circuit element, it is required to form the groove finely, that is, to have a narrow width. On the other hand, in order to enhance the element isolation effect or obtain a large-capacity capacitor, it is necessary to increase the depth of the groove. After all, a groove with a fine width and as deep as possible is required.
従来、半導体基体に溝を形成するエッチング技術として
は反応性イオンエッチング（ＲＩＥ）法が、その異方性
が比較的に高いことから細溝幅の形成に利用されてい
る。具体的にはＣＦ4，Ｉ2ガスの混合ガス、又はこれら
弗化炭素ガスとＣＢｒＦ3ガスの混合ガスを反応ガスと
したドライエッチング法であり、シリコン半導体基板に
溝を形成する場合には基板表面にＳｉＯ2膜をパターニ
ングして形成し、これをマスクとして前述のエッチング
を行なっている。Conventionally, as an etching technique for forming a groove in a semiconductor substrate, a reactive ion etching (RIE) method has been used for forming a narrow groove width because its anisotropy is relatively high. Specifically, it is a dry etching method using a mixed gas of CF 4 and I 2 gas or a mixed gas of these fluorocarbon gas and CBrF 3 gas as a reaction gas. When a groove is formed in a silicon semiconductor substrate, the substrate is used. A SiO 2 film is formed on the surface by patterning, and the above etching is performed using this as a mask.
しかしながら、本発明者の検討によれば、前述した従来
方法はＳｉとＳｉＯ2とのエッチング選択比が小さいた
めに、微細幅でかつ深さの大きい溝、これを溝幅寸法と
溝深さ寸法との比で言えば、１：４程度以上の溝を形成
することは困難であり、前述のような高集積型の回路素
子の形成に適用することは実際上不可能であった。即
ち、ＳｉとＳｉＯ2の選択比が小さいと、深い溝を形成
するためには必然的にマスクとしてのＳｉＯ2膜を厚く
せざるを得ないが、ＳｉＯ2膜があつくなればそれだけ
ＳｉＯ2膜の微細パターニングが困難になり溝の細幅形
成ができなくなる。逆にＳｉＯ2膜を薄くすれば微細パ
ターニングは可能であるが、溝を深くエッチングする前
にＳｉＯ2膜がエッチングされてしまうことになり深溝
の形成ができなくなってしまう。However, according to the study by the present inventor, in the above-mentioned conventional method, since the etching selection ratio between Si and SiO 2 is small, a groove having a fine width and a large depth is obtained. In terms of the ratio, it is difficult to form a groove of about 1: 4 or more, and it is practically impossible to apply it to the formation of the highly integrated circuit element as described above. That, Si and the selection ratio of SiO 2 is small, thick forced to SiO 2 film as inevitably mask to form deep grooves, the more SiO 2 film if SiO 2 film is thick Therefore, it becomes difficult to perform fine patterning, and it becomes impossible to form a narrow groove. On the contrary, if the SiO 2 film is thinned, fine patterning is possible, but the SiO 2 film is etched before the groove is deeply etched, and the deep groove cannot be formed.
なお、シリコン半導体基板のエッチング技術に関して
は、たとえば特開昭５５−１３８８３４号公報、同５６
−１３４７３８号公報、同５６−１４４５４１号公報な
どに示されている。Regarding the etching technique of the silicon semiconductor substrate, for example, JP-A-55-138834 and JP-A-56-138834.
-134738 and 56-144541.
本発明の目的は、Ｓｉ基体をＳｉＯ2をマスクにして選
択的にエッチングし、そのＳｉ基体内に細幅でかつ十分
な深さの溝を形成し、集積度の高い半導体装置を製造す
る方法を提供することにある。An object of the present invention is to manufacture a highly integrated semiconductor device by selectively etching a Si substrate using SiO 2 as a mask to form a groove having a narrow width and a sufficient depth in the Si substrate. To provide.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面から明らかになるであろ
う。The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.
すなわち、本発明は、Ｏ2ガスを混入したＢｒ2ガスの雰
囲気中で、露出するＳｉ基体の一部を反応性イオンエッ
チングを行い、そのＳｉ基体に所定深さの溝を形成する
とともにその溝の周側表面ににＳｉＯ2膜を形成すると
いうものであり、これにより、溝幅と深さの比が１：４
以上の溝を極めて容易に形成でき、これにより高集積な
半導体装置の製造を可能とするものである。That is, according to the present invention, a part of the exposed Si substrate is subjected to reactive ion etching in an atmosphere of Br 2 gas mixed with O 2 gas to form a groove of a predetermined depth in the Si substrate and to form the groove. The SiO 2 film is formed on the surface of the peripheral side of the groove, so that the ratio of the groove width to the depth is 1: 4.
The above-mentioned groove can be formed extremely easily, which makes it possible to manufacture a highly integrated semiconductor device.
第１図は本発明の製造方法、即ちエッチング方法を実施
する装置の構成図である。内部を気密に保ち得るベルジ
ャ１内には上部電極２，下部電極３を対向配置し、エッ
チング処理されるシリコン（Ｓｉ）半導体基板（ウェー
ハ）Ｗは下部電極３上に載置している。そして、上部電
極２をグランド接地し、下部電極３に高周波電力源４を
接続している。また、下部電極３にはセルフバイアス用
の直流電圧５を加えている。また、サセプタ等のウェー
ハ加熱手段も付設している。前記ベルジャ１は上部に反
応ガス供給口６を開設し、かつ下部には排気ポンプ７に
連なる排気口８を開設し、これらの作用によってベルジ
ャ１内を所要の真空ガス圧に設定できる。FIG. 1 is a block diagram of an apparatus for carrying out the manufacturing method of the present invention, that is, an etching method. An upper electrode 2 and a lower electrode 3 are arranged to face each other in a bell jar 1 which can keep the inside airtight, and a silicon (Si) semiconductor substrate (wafer) W to be etched is placed on the lower electrode 3. The upper electrode 2 is grounded and the lower electrode 3 is connected to the high frequency power source 4. A DC voltage 5 for self-bias is applied to the lower electrode 3. A wafer heating means such as a susceptor is also attached. The bell jar 1 is provided with a reaction gas supply port 6 in the upper part and an exhaust port 8 connected to an exhaust pump 7 in the lower part, and by these actions, the inside of the bell jar 1 can be set to a required vacuum gas pressure.
この構成の装置によれば、シリコン（Ｓｉ）半導体基板
１０への溝のエッチング形成は次のように行なうことが
できる。第２図（Ａ）乃至第２図（Ｄ）はその原理図を
示す。例えば、第２図（Ａ）のように基板１０の表面に
ＣＶＤ法等により１．４μｍのＳｉＯ2膜１１を形成
し、更にその上にフォトレジスト膜１２を形成する。そ
して、常法のフォトリゾグラフィ技術により第２図
（Ｂ）のようにフォトレジスト膜１２に幅Ａが約１μｍ
の開口を形成した上で基板１０を前記下部電極３上に載
置する。そして、下部電極３に１３．５６ＭＨｚ，０．
１〜２Ｗ／cm3の高周波電力を印加し、かつ２００〜８
００Ｖの直流電圧を加えた上で、ガス供給口６からＣ2
Ｆ6等のガスをベルジャ内に供給し、かつ排気口８から
真空引きを行なって内部を５０ｍＴｏｒｒ程度のガス圧
にする。これにより、反応性イオンエッチング（ＲＩ
Ｅ）が行なわれ、第２図（Ｃ）のようにフォトレジスト
膜１２をマスクとしてＳｉＯ2膜１１は１μｍの幅にエ
ッチングされる。According to the apparatus having this configuration, the groove can be formed by etching in the silicon (Si) semiconductor substrate 10 as follows. 2 (A) to 2 (D) show the principle diagrams thereof. For example, as shown in FIG. 2A, a 1.4 μm SiO 2 film 11 is formed on the surface of the substrate 10 by a CVD method or the like, and a photoresist film 12 is further formed thereon. Then, as shown in FIG. 2 (B), the width A of the photoresist film 12 is about 1 μm by a conventional photolithography technique.
The substrate 10 is placed on the lower electrode 3 after forming the openings. Then, the lower electrode 3 has 13.56 MHz, 0.
High frequency power of 1-2 W / cm 3 is applied and 200-8
After applying a DC voltage of 00V, C 2 from the gas supply port 6
A gas such as F 6 is supplied into the bell jar, and the exhaust port 8 is evacuated to a gas pressure of about 50 mTorr. As a result, reactive ion etching (RI
As shown in FIG. 2C, the SiO 2 film 11 is etched to a width of 1 μm by using the photoresist film 12 as a mask as shown in FIG. 2C.
次いで、基板１０表面のフォトレジスト膜１２を除去し
た後（除去方法は公知の任意の方法でよい）、今度はガ
ス供給口６から臭素（Ｂｒ2）ガスを供給し、ベルジャ
１内を純粋のＢｒ2を反応ガスとしたＲＩＥにより、Ｓ
ｉＯ2膜１１をマスクにして基板１０のエッチングが開
始される。所定時間のエッチングを行なうことにより、
第２図（Ｄ）のエッチング溝１３が形成される。Then, after removing the photoresist film 12 on the surface of the substrate 10 (the removal method may be any known method), bromine (Br 2 ) gas is supplied from the gas supply port 6 to clean the inside of the bell jar 1. By RIE using Br 2 as a reaction gas, S
Etching of the substrate 10 is started using the iO 2 film 11 as a mask. By etching for a predetermined time,
The etching groove 13 of FIG. 2D is formed.
このようにして形成された溝１３は、溝幅が１μｍであ
るのに対しその深さＤは約８μｍであり、極めて細幅で
深さの大きい溝となる。そして、溝１３の底面は略平坦
であり、溝幅は上部の開口近傍において中間部の溝幅よ
り若干小さくなっている。このような狭い溝は、従来の
ガスを使用した方法では得ることができず、前述したＢ
ｒ2ガスを使用したエッチング法では異方性が極めて強
いことが明かとなった。また、マスクとしてのＳｉＯ2
膜１１の膜厚が０．４μｍ程度にしか低減されていない
ことからＳｉとＳｉＯ2との選択比も大きい。本発明者
の種々の実験によれば、１：１３〜１６の選択比が得ら
れた。これらのことから、このエッチング方法によれ
ば、ＳｉＯ2膜１１を薄く形成してそのマスクとしての
パターン形状をサブミクロンのレベルにまで微細化して
も、薄幅対溝深さの比が１：４以上の微細溝を形成する
ことは容易である。The groove 13 thus formed has a groove width of 1 μm and a depth D of about 8 μm, which is an extremely narrow groove with a large depth. The bottom surface of the groove 13 is substantially flat, and the groove width is slightly smaller than the groove width of the intermediate portion in the vicinity of the upper opening. Such a narrow groove cannot be obtained by a method using a conventional gas, and the above-mentioned B
It was revealed that the etching method using r 2 gas has extremely strong anisotropy. In addition, SiO 2 as a mask
Since the film thickness of the film 11 is reduced to only about 0.4 μm, the selection ratio between Si and SiO 2 is also large. According to various experiments conducted by the present inventor, a selectivity of 1:13 to 16 was obtained. From these facts, according to this etching method, even if the SiO 2 film 11 is formed thin and the pattern shape as the mask is miniaturized to the submicron level, the ratio of the thin width to the groove depth is 1 :. It is easy to form four or more fine grooves.
この時、本発明で特徴づけられた点は上記ガスにＯ2ガ
スを混入することである。すなわち、ベルジャ１内に若
干のＯ2ガスを混入しておけば、第３図のように、溝１
３Ｂ底部においてエッチングされたＳｉ成分は直ちに反
応してＳｉＯ2１９となり、溝１３Ｂの周側面上に徐々
に付着して溝１３Ｂ幅を低減するように作用する。これ
により、エッチングの進行と共に溝底面が狭められ、結
果的に底面が傾斜ないし曲面状に形成されることにな
る。At this time, the feature of the present invention is to mix O 2 gas with the above gas. That is, if a small amount of O 2 gas is mixed in the bell jar 1, as shown in FIG.
The Si component etched at the bottom of 3B immediately reacts to become SiO 2 19, which gradually adheres to the peripheral side surface of the groove 13B and acts to reduce the width of the groove 13B. As a result, the bottom surface of the groove is narrowed as the etching progresses, and as a result, the bottom surface is formed in an inclined or curved shape.
したがって、かかる本発明によれば、溝形成時にその溝
周側面が選択比の高いＳｉＯ2に変成されるため、溝幅
が拡がらず深くなおかつ細溝幅の溝形成ができるという
作用効果をもたらす。また、前述のように溝底面が傾斜
ないし曲面状に形成されることになるため、溝内への埋
込み材料の充填はされ易く、しかもその充填時間も短縮
できるという作用効果をもたらす。そしてさらに溝底部
でのＳｉＯ2は厚く形成され、例えばその溝内に埋込み
材料として下記の如くポリシリコンが充填されても、そ
のポリシリコンと基板との間の絶縁耐圧の低下を防止で
きるという効果をもたらす。Therefore, according to the present invention, since the peripheral side surface of the groove is transformed into SiO 2 having a high selection ratio at the time of forming the groove, the groove width does not spread and it is possible to form a deep groove with a narrow groove width. . Further, as described above, since the bottom surface of the groove is formed to have an inclination or a curved surface, the filling material can be easily filled into the groove, and the filling time can be shortened. Further, SiO 2 is formed thicker at the bottom of the groove, and even if the groove is filled with polysilicon as a filling material as described below, it is possible to prevent a decrease in dielectric strength between the polysilicon and the substrate. Bring
次に、以上のように形成される溝を回路素子として応用
した実施形態を説明する。Next, an embodiment in which the groove formed as described above is applied as a circuit element will be described.
第４図は、溝を素子間分離に適用した例である。即ち、
Ｐ型シリコン半導体基板２０に上述の如き方法で溝２１
を形成し、その上でＣＶＤＳｉＯ2またはノンドープポ
リシリコン等で溝内を充填している。そして、このよう
に構成されたそれぞれ素子分離域２３間にＰ型ウェル２
４，Ｎ型ウェル２５を形成し、Ｎ＋型半導体領域２７お
よびゲート電極２８を形成することにより夫々Ｎチャネ
ルMOSFETQNとＰチャネルMOSFETQPを構成でき、所謂ＣＭ
ＯＳが形成できる。FIG. 4 is an example in which a groove is applied to element isolation. That is,
The groove 21 is formed in the P-type silicon semiconductor substrate 20 by the method described above.
Is formed, and the groove is filled with CVD SiO 2 or non-doped polysilicon or the like. Then, the P-type well 2 is formed between the element isolation regions 23 thus configured.
4, by forming the N-type well 25 and forming the N + -type semiconductor region 27 and the gate electrode 28, the N-channel MOSFET QN and the P-channel MOSFET QP can be formed respectively.
OS can be formed.
このＣＭＯＳによれば、素子間分離域２３が十分深く形
成されているのでラッチアップの発生を防止して信頼性
を向上でき、しかも溝は狭幅に形成されるので、微細化
を達成でき高集積化に有効となる。According to this CMOS, since the element isolation region 23 is formed sufficiently deep, the occurrence of latch-up can be prevented and the reliability can be improved, and since the groove is formed with a narrow width, miniaturization can be achieved and high Effective for integration.
（１）反応ガスにＢｒ2ガスを使用してＲＩＥ法による
エッチングを行なうことにより、Ｓｉ／ＳｉＯ2の選択
比を１：１３〜１６にでき、これによりＳｉＯ2膜をエ
ッチングマスクに使用する際のマスクの薄膜化を図るこ
とができ、マスクパターンおよびエッチングパターンの
微細化および高集積化が達成できる。(1) By performing etching by the RIE method using Br 2 gas as a reaction gas, the selection ratio of Si / SiO 2 can be set to 1:13 to 16, which makes it possible to use the SiO 2 film as an etching mask. The thickness of the mask can be reduced, and the mask pattern and the etching pattern can be miniaturized and highly integrated.
（２）反応ガスにＢｒ2ガスを使用することにより異方
性を強めることができ、前記（１）の選択比の増大と共
に細幅かつ深い溝を容易に形成でき、特に、溝形成時に
その溝周側面が選択比の高いＳｉＯ2に変成されるた
め、溝幅が拡がらず深くなおかつ細溝幅の溝形成ができ
るので幅と深さの比が１：４以上の溝を簡単に形成でき
る。(2) By using Br 2 gas as the reaction gas, the anisotropy can be strengthened, and narrow and deep grooves can be easily formed with the increase of the selection ratio of (1) above. Since the side surface of the groove is transformed to SiO 2 with a high selection ratio, the groove width does not spread and it is possible to form a deep groove with a narrow groove width, so it is easy to form a groove with a width to depth ratio of 1: 4 or more. it can.
（３）溝底面が傾斜ないし曲面状に形成されることにな
るため、溝内への埋込み材料の充填はされ易く、しかも
その充填時間も短縮できる。(3) Since the bottom surface of the groove is formed to be inclined or curved, the filling material is easily filled in the groove, and the filling time can be shortened.
（４）溝底部でのＳｉＯ2は厚く形成され、絶縁耐圧の
低下を防止できる。(4) SiO 2 is formed thick at the bottom of the groove, so that the withstand voltage can be prevented from lowering.
（５）前記実施例の如き溝内に絶縁物を充填してＣＭＯ
Ｓ等の素子間分離用に利用ししているので、溝の十分な
深さにより素子分離効果を高めてＣＭＯＳにおけるラッ
チアップを防止する一方で高集積化が達成できる。(5) CMO by filling the groove with an insulator as in the above embodiment
Since it is used for element isolation such as S, the element isolation effect is enhanced by the sufficient depth of the groove to prevent latch-up in CMOS, while achieving high integration.
（６）反応ガスをＢｒ2そしてＯ2ガスを混入する以外は
従来と略同じＲＩＥ法でエッチングを行なっているの
で、装置は従前のものをそのまま使用でき、設備等の点
で有利である。(6) Since the etching is performed by the RIE method substantially the same as the conventional one except that the reaction gas is mixed with Br 2 and O 2 gas, the conventional apparatus can be used as it is, which is advantageous in terms of equipment and the like.
第１図は本発明方法を実施するエッチング装置の断面構
成図。 第２図（Ａ）乃至第２図（Ｄ）は溝の形成工程を示す原
理図。 第３図は本発明による溝形成状態を示す断面図。 第４図は本発明をＣＭＯＳの素子間分離に適用した例の
断面図。 １……ベルジャ、２……上部電極、３……下部電極、４
……高周波電力源、６……ガス供給口、８……排気口、
１０……Ｓｉ基板、１１，１１Ａ……ＳｉＯ2膜、１２
……フォトレジスト膜、１３……溝、１９……Ｓｉ
Ｏ2、２０……Ｓｉ基板、２１……溝、２２……Ｓｉ
Ｏ2、２３……素子間分離域、２４……Ｐ型ウェル、２
５……Ｎ型ウェル、２６，２７……拡散層、２８……ゲ
ート電極、Ｗ……ウェーハ。FIG. 1 is a sectional configuration diagram of an etching apparatus for carrying out the method of the present invention. 2 (A) to 2 (D) are principle diagrams showing a groove forming process. FIG. 3 is a sectional view showing a groove formation state according to the present invention. FIG. 4 is a sectional view of an example in which the present invention is applied to isolation between CMOS elements. 1 ... Belger, 2 ... Upper electrode, 3 ... Lower electrode, 4
…… High frequency power source, 6 …… Gas supply port, 8 …… Exhaust port,
10 ... Si substrate, 11, 11A ... SiO 2 film, 12
...... Photoresist film, 13 ...... Groove, 19 ...... Si
O 2 , 20 ... Si substrate, 21 ... groove, 22 ... Si
O 2 , 23 ... Element isolation region, 24 ... P-type well, 2
5 ... N-type well, 26, 27 ... Diffusion layer, 28 ... Gate electrode, W ... Wafer.
フロントページの続き (72)発明者 広部 嘉道 東京都小平市上水本町1450番地 株式会社 日立製作所武蔵工場内 (56)参考文献 特開 昭57−157540（ＪＰ，Ａ) 特開 昭59−13329（ＪＰ，Ａ) 特公 昭58−14507（ＪＰ，Ｂ２)Front Page Continuation (72) Inventor Yoshimichi Hirobe 1450, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (56) Reference JP-A-57-157540 (JP, A) JP-A-59- 13329 (JP, A) JP 58-14507 (JP, B2)
Claims (1)
工程と、そのＳｉＯ2膜を選択的に除去し、Ｓｉ基体の
一主面の一部を露出する工程と、Ｏ2ガスを混入したＢ
ｒ2ガスの雰囲気中で、残されたＳｉＯ2膜をマスクとし
て前記露出するＳｉ基体の一部を反応性イオンエッチン
グを行い、そのＳｉ基体に所定深さの溝を形成するとと
もにその溝の周側表面にＳｉＯ2膜を形成する工程と、
その側面にＳｉＯ2膜が形成された溝内に絶縁物を充填
する工程とから成ることを特徴とする半導体装置の製造
方法。1. A step of coating a main surface of a Si substrate with a SiO 2 film, a step of selectively removing the SiO 2 film to expose a part of the main surface of the Si substrate, and an O 2 gas. B mixed with
In the atmosphere of r 2 gas, the exposed SiO 2 film is used as a mask to carry out reactive ion etching on a part of the exposed Si substrate to form a groove of a predetermined depth in the Si substrate and to surround the groove. A step of forming a SiO 2 film on the side surface,
And a step of filling an insulating material in a groove having a SiO 2 film formed on its side surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59113003A JPH0644591B2 (en) | 1984-06-04 | 1984-06-04 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59113003A JPH0644591B2 (en) | 1984-06-04 | 1984-06-04 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60257539A JPS60257539A (en) | 1985-12-19 |
| JPH0644591B2 true JPH0644591B2 (en) | 1994-06-08 |
Family
ID=14601004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59113003A Expired - Lifetime JPH0644591B2 (en) | 1984-06-04 | 1984-06-04 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644591B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4702795A (en) * | 1985-05-03 | 1987-10-27 | Texas Instruments Incorporated | Trench etch process |
| JPS62250662A (en) * | 1986-04-24 | 1987-10-31 | Agency Of Ind Science & Technol | Complementary type semiconductor device |
| JP2619402B2 (en) * | 1987-08-17 | 1997-06-11 | 富士通株式会社 | Silicon trench etching method |
| DE68928977T2 (en) * | 1988-02-09 | 1999-08-19 | Fujitsu Ltd | Dry etching with hydrogen bromide or bromine |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57157540A (en) * | 1981-03-25 | 1982-09-29 | Hitachi Ltd | Semiconductor device |
-
1984
- 1984-06-04 JP JP59113003A patent/JPH0644591B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60257539A (en) | 1985-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4836885A (en) | Planarization process for wide trench isolation | |
| US7906407B2 (en) | Shallow trench isolation structures and a method for forming shallow trench isolation structures | |
| US7320927B2 (en) | In situ hardmask pullback using an in situ plasma resist trim process | |
| JP3248072B2 (en) | Oxide film etching method | |
| KR101292025B1 (en) | Robust shallow trench isolation structures and a method for forming shallow trench isolation structures | |
| US6214695B1 (en) | Method of manufacturing semiconductor device | |
| JPH0644591B2 (en) | Method for manufacturing semiconductor device | |
| US6667222B1 (en) | Method to combine zero-etch and STI-etch processes into one process | |
| JP2757838B2 (en) | Method for manufacturing semiconductor device | |
| US5851901A (en) | Method of manufacturing an isolation region of a semiconductor device with advanced planarization | |
| JP3097338B2 (en) | Method of forming contact hole | |
| US6309947B1 (en) | Method of manufacturing a semiconductor device with improved isolation region to active region topography | |
| JPH11330045A (en) | Method for etching laminated film of oxide film and silicon layer | |
| JP3053009B2 (en) | Method for manufacturing semiconductor device | |
| JP2817226B2 (en) | Method for manufacturing semiconductor device | |
| JPH09260485A (en) | Manufacture of semiconductor device | |
| KR20000061225A (en) | Method for fabricating trench of semiconductor device | |
| JP2000260871A (en) | Manufacture of semiconductor device | |
| JP2553539B2 (en) | Method for manufacturing semiconductor device | |
| JPH05235338A (en) | Semiconductor device and manufacture thereof | |
| KR980012266A (en) | Device isolation method of semiconductor device | |
| JPH06124944A (en) | Semiconductor device | |
| KR100575616B1 (en) | Method for forming borderless contact hole in a semiconductor device | |
| JPH02134818A (en) | Formation of wiring structure body | |
| KR100209279B1 (en) | Method for forming a contact of semiconductor device |