KR970008375A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR970008375A
KR970008375A KR1019960029111A KR19960029111A KR970008375A KR 970008375 A KR970008375 A KR 970008375A KR 1019960029111 A KR1019960029111 A KR 1019960029111A KR 19960029111 A KR19960029111 A KR 19960029111A KR 970008375 A KR970008375 A KR 970008375A
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KR
South Korea
Prior art keywords
semiconductor device
reaction chamber
gas
plasma
film
Prior art date
Application number
KR1019960029111A
Other languages
Korean (ko)
Other versions
KR100215601B1 (en
Inventor
마사토시 히구치
Original Assignee
니시무로 타이조
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 니시무로 타이조, 가부시키가이샤 도시바 filed Critical 니시무로 타이조
Publication of KR970008375A publication Critical patent/KR970008375A/en
Application granted granted Critical
Publication of KR100215601B1 publication Critical patent/KR100215601B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Abstract

본 발명은, 플라즈마를 이용한 드라이 에칭방법에 있어서, 종래로부터 개발이 진행되고 있는 탄화 플루오르가스와 C0의혼합가스를 이용한 경우와 같은 정도의 에칭특성을 갖고, 인화나 발화 등의 위험이 없으며, 안전성의 확보가 용이한 에칭방법을 실현한다.The present invention relates to a dry etching method using plasma, which has an etching characteristic to the same extent as that of the case of using a gas mixture of C0 and fluorine fluorocarbons, which has been developed conventionally, and has no risk of ignition or ignition, Can be easily obtained.

본 발명은, C0를 조성식에 포함하는 탄화 플루오르가스를 드라이 에칭에서의 에칭가스로서 이용하여, 예컨대 웨이퍼(21)상에 형성되고, 레지스트(23) 등의 마스크가 형성된 실리콘 산화막(22)에 소정 패턴의 개공(24)을 형성한다.The silicon oxide film 22 formed on the wafer 21 and having a mask such as the resist 23 is formed on the silicon oxide film 22 by using a fluorine gas containing C0 in the composition formula as the etching gas in the dry etching. Thereby forming openings 24 of the pattern.

Description

반도체장치의 제조방법Method for manufacturing semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 본 발명의 실시예에 이용하는 에칭장치의 일례를 나타낸 개략도.FIG. 1 is a schematic view showing an example of an etching apparatus used in an embodiment of the present invention. FIG.

Claims (5)

반응실(11)내의 전극(12)에 소정막이 형성된 반도체기판(13)을 재치하는 공정과, 상기 반응실(11)내에 C0를 조성식중에 포함하는 탄화 플루오르가스를 도입하는 공정 멎, 상기 전극(12)에 고주파전압을 인가하여 상기 반응실(11)내에 플라즈마를 생성하여 상기 소정막을 에칭처리하는 드라이 에칭공정을 갖춘 반도체장치의 제조방법.A step of placing a semiconductor substrate 13 on which a predetermined film is formed on the electrode 12 in the reaction chamber 11 and a step of introducing C0 into the reaction chamber 11 by introducing fluorocarbons 12. A method for manufacturing a semiconductor device, comprising the steps of: forming a plasma in a reaction chamber (11) by applying a high frequency voltage; 제1항에 있어서, 상기 반응가스가 CF3FCOCF2(hexaf1uoropropenoxide) 또는 CF3COCF3(hexafluoroacetone)인 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the reaction gas is CF 3 FCOCF 2 (hexafluoropropenoxide) or CF 3 COCF 3 (hexafluoroacetone). 제1항에 있어서, 상기 소정막이 실리콘 산화막 또는 실리콘 질화막 또는 실리콘막인 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the predetermined film is a silicon oxide film, a silicon nitride film, or a silicon film. 에칭마스크가 형성된 소정막을 반응실(11)내에 도입시킨 반응가스의 작용에 의해 에칭하는 드라이 에칭공정을 갖춘 반도체장치의 제조방법에 있어서, 상기 반응가스에 할로겐화물과 C와 CO가 화학 결합한 탄화 플루오르가스를 이용한 것을 특징으로 하는 반도체장치의 제조방법.A process for producing a semiconductor device having a dry etching process in which a predetermined film on which an etching mask is formed is etched by the action of a reaction gas introduced into a reaction chamber (11), characterized in that the reaction gas is a fluorine- Wherein a gas is used. 제4항에 있어서, 상기 소정막이 상기 반응실(11)내에 설치된 전극(12)상에 재치되고, 상기 전극(12)에 전압을 인가하는 것에 의해 상기 반응실(11)내에 플라즈마가 생성되며, 상기 플라즈마에 의해 상기 탄화 플루오르가스를 구성하는 C0가 상기 탄화 플루오르가스로부터 해리되는 것을 특징으로 하는 반도체장치의 제조방법.The plasma processing apparatus according to claim 4, wherein the predetermined film is placed on an electrode (12) provided in the reaction chamber (11), and plasma is generated in the reaction chamber (11) And the C0 constituting the fluorocarbon gas is dissociated from the fluorocarbon gas by the plasma. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960029111A 1995-07-20 1996-07-19 Manufacture of semiconductor device KR100215601B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7183652A JPH0936091A (en) 1995-07-20 1995-07-20 Manufacture of semiconductor device
JP95-183652 1995-07-20

Publications (2)

Publication Number Publication Date
KR970008375A true KR970008375A (en) 1997-02-24
KR100215601B1 KR100215601B1 (en) 1999-08-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960029111A KR100215601B1 (en) 1995-07-20 1996-07-19 Manufacture of semiconductor device

Country Status (3)

Country Link
JP (1) JPH0936091A (en)
KR (1) KR100215601B1 (en)
TW (1) TW302509B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1027781A (en) * 1996-07-10 1998-01-27 Daikin Ind Ltd Etching gas and cleaning gas
DE19706682C2 (en) * 1997-02-20 1999-01-14 Bosch Gmbh Robert Anisotropic fluorine-based plasma etching process for silicon
KR102303686B1 (en) * 2017-02-28 2021-09-17 샌트랄 글래스 컴퍼니 리미티드 Dry etching agent, dry etching method and semiconductor device manufacturing method

Also Published As

Publication number Publication date
KR100215601B1 (en) 1999-08-16
TW302509B (en) 1997-04-11
JPH0936091A (en) 1997-02-07

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