JPS6065348A - Diagnosis system for arithmetic unit - Google Patents

Abstract

PURPOSE:To perform the diagnosis of an arithmetic unit with high reliability with no deterioration of performance by starting a diagnosis program to an instruction fed from a central processing unit only in an idle period of the arithmetic unit. CONSTITUTION:A central processing unit CPU performs repetitively the reading and decoding of instructions, an operand calculation and the reading of data respectively. When it is decided that the instruction under decoding is equal to that to an arithmetic unit, this instruction is informed to the related arithmetic units. The arithmetic unit received an instruction sets the diagnosis flag of a diagnosis control register 5 at ''0'', and reads a program out of a control memory 3 with the start of the CPU to execute the instruction. When the decoded instruction is not equal to that related to the own arithmetic unit, the diagnosis flat of a diagnosis control register 6 is set at ''1''. Then the arithmetic unit sets the head address of the diagnosis program to a program counter 18 in response to a fact that the diagnosis flag is changed to 1 from 0 and then reads an idle time diagnosis program out of the memory 3 to start the execution of the program.

Description

[Detailed description of the invention]

(1) Technical Molecule of the Invention fff The present invention relates to an arithmetic device diagnostic system, and relates to an arithmetic device diagnostic method that can perform device diagnostics 1υ1 without affecting IM calculation speed and improve its reliability. (b) Background of the Technology A diagnostic analysis is performed to check whether 611 arithmetic operations are being performed normally for each arithmetic unit number of a central processing unit. There are various types of diagnosis depending on the need, but depending on the format, it is necessary to perform the diagnosis in a timely manner in relation to the data and program used for the diagnosis. There is still room for improvement, such as a decrease in performance, and this is becoming more noticeable as the number of computing devices increases. (c) Conventional technology and problems Conventional operation and equipment diagnosis...1 includes the initial diagnosis of a major power stage failure.
ji, diagnosis W1 during program loading (II) L)
, patrol examination Ij1, etc., and these examinations are mainly performed by checking data of calculation results. However, since Chenok data is always uniform data and the amount of data is small, it is difficult to analyze it when the basic program is running, and if you try to increase the number in pal-roll diagnosis, the system performance will be affected. There are disadvantages such as inviting low pitches. (d) Purpose of the Invention The present invention was devised in view of the drawbacks of the 15-diagnosis 1υ1 method as described above, and its purpose is to
It is an object of the present invention to provide a processing device diagnostic method capable of diagnosing a processing device during its idle time and improving its reliability without degrading its performance. (Po) Structure of the Invention In order to achieve this objective, the method of the present invention is controlled by a central processing unit, and each time the central processing unit issues an instruction to an arithmetic unit equipped with its own microprogram or control program, means for retaining whether the instruction is a first state in which the instruction is an instruction to be written on the arithmetic device, or a second state in which the instruction is an instruction for a device other than the arithmetic device; The diagnostic program of the arithmetic unit is started only when the state changes to

[Means for terminating the program; means for creating a plurality of data having a predetermined relationship from data preset in a predetermined register at the time of diagnosis Wi by different hexadecimal operations; means for setting an error flag when the specified relationship is not as expected, and responding to the error flag set when the arithmetic unit is started up; and means for issuing an interrupt to the central processing unit, thereby diagnosing one device at f4. (...) Embodiments of the Invention The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 shows a schematic configuration of an embodiment of the present invention, and FIG. 2 shows a first embodiment of the present invention.
FIG. 3 is a detailed diagram of the arithmetic device of the illustrated embodiment. In Figure 1,
1 indicates the central processing unit, and 2]. 22, . . . 21J are various arithmetic devices such as a floating point arithmetic device, a decimal arithmetic device, a function 4ii arithmetic device, etc. In FIG. 2, reference numerals 3, 4.5 are a control register IQ device, a control register, and a program counter that control the arithmetic unit, and their activation is performed by a program or a diagnostic IJ.
Controlled by Ji and controlled by Sisk 6. Register 6 is command information regarding free time diagnosis 1tli,
Stores status display and error information. The arithmetic section of the arithmetic device is composed of an arithmetic register 7, a multiplier 8, and an arithmetic unit 9. The input power of the arithmetic register 7 is connected via a multiplexer 10 to the arithmetic node 11 or the output of the arithmetic unit 9, which is connected to the °C central 6ii arithmetic unit 1 (see FIG. 1, 1jq). A parity check circuit 12 is connected to the calculation lotus 11 . 13.14 is an internal calculation lotus. 15 is a condition code generator connected to the arithmetic unit 9, and its output is sent to the control register 4.
h (CJ (hiso 1-) output is connected to the analog game 1-16.
Call flag in control register 6 (hit 2 in Figure 3)
and error? lI, 7%, (Hiso 13-7 in Figure 3
) is connected to the cent input. 17 is the output lotus, and 18 is a parity hit that adds a parity hit to the take of the output lotus 17. I9 is a calculation north on the central processing unit side. Next, the diagnostic state (daughter) of the arithmetic unit according to the present invention will be explained. As shown in FIG. 4, the operation in the central processing unit 1 is as shown in FIG.
(decode), operand calculation and data reading (1lead), and are repeated at h+15 of execution. During such an operation, if the central processing unit in Fig. 4 decodes the instruction 1, 1! reading, the instruction is written in the arithmetic unit. If the instruction is related to its own device, the arithmetic device issues a diagnosis tlJ at the timing shown in Figure 4 decode.
i il; 11fall The check 1 Jli fluff (hit 1) of the register 5 is set to "0", and the system waits for activation by the central processing unit. When the central processing unit starts up, the 64 arithmetic unit executes the specified arithmetic instruction (the program is the control memory
．． (read out from J device 3) is executed. At the timing of decode in FIG. 4, if an instruction related to the own arithmetic unit is lost, the diagnosis W1 flag (hit) of the diagnosis control register 6 is set to "I". In response to the arithmetic unit checking W1 flag changing from ``(') to ``'I'', the program counter 5 is checked to read the first address of the 1υ1 program from nano 1 to 1, and the iQ device 3 writes the control information as shown in FIG. Reads the empty interview W1 program and starts its execution. Prior to this execution, the initial value or the previous calculation result is stored in the calculation register (a), and the diagnosis is proceeded based on the contents. Calculation The calculation result of the unit 9 is checked using the c of the control register 4.
When khiso1- is ゛°1pa, it is determined whether the condition-r-l generated based on the calculation result matches the expected value, and if it is different from the expected value, the diagnostic program is sequentially executed. When the series of examinations W1 is completed, calculation register 1 is
Add 1 to the contents of (a) and repeat the same diagnosis as above. J'+ like this? Diagnosis 111i of + is shown in Figure 4 decod
If the instruction is related to the own iFi arithmetic device at timing e, the process ends when the diagnosis UIJi flag (hisoi-1 in FIG. 3) of the diagnosis 11i control register 6 changes from "1" to "0". If the condition code described above does not match the expected value, the error flag (bit 2 in Figure 3) and error number (bit 3 to 7 in Figure 3) of the diagnostic control register 6 are set. , h l', lJi instruction during instruction l:lJi −
J-ru. In accordance with the arithmetic unit −゛ in such a state, lJ! J g?
When the instruction is activated, the diagnostic control register 60)
Because the error flag is "1", that's it.
) Q instruction is not executed and is interrupted according to the central processing unit 1. The central processing unit 1 resolves the contents of the error, performs retry processing, and performs
Execution by 81F of the processing unit, etc. is performed. By the way, is the performance 3 of the above one? - The device may also include a processor in a channel device A connected to the central processing unit, not as exemplified above. (1) Results of the invention As stated above, the present invention has the following advantages: 1. ■ Perform diagnosis without reducing the calculation speed of the arithmetic unit.
In M, ■ the direction of the belief + + r - + of that arithmetic device '2! (2) It also prevents deterioration in the performance of the system.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, FIG. 2 is a detailed diagram of the arithmetic unit of the embodiment of FIG. 1, FIG. 3 is a diagram showing the contents sent to the diagnostic control B1 Lucister, and FIG. Processing of Central Processing Unit) II-Char 1-1 FIG. I-Chi+--1-. In the figure, 1 is a central processing unit, 21.22...21J are arithmetic units, 3 is a control record 4. a device, 4 is a control register,
5 is the program counter, 6 is the diagnosis 1jli control register, 7 is the calculation register, 8 is the fΔ counter, and 9 is the calculation dLIO.
is a multi-breaker, and 15 is a two-intion code generator. Figure 1 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] fil is controlled by the central processing unit and executes its own microprogram or control program fJif! Each time the central processing unit completes an instruction, the central processing unit maintains whether the instruction is in a first state in which the instruction is an instruction for the arithmetic unit or in a second state in which the instruction is an instruction to a unit other than the arithmetic unit. and means to start the diagnosis W1 program of the /iI calculation device when the retained content changes from the first state to the second state, and to start the diagnosis W1 program of the iI calculation device when the stored content changes from the first state to the first state. Means for terminating the Diagnosis 1vi program and Diagnosis 111i
means for creating a plurality of data having a predetermined relationship from data stored in a predetermined register in advance by different calculations; and when the microphone program or control program is turned on. Means for sending an error flag when the relationship between the plurality of data is not as expected, and activation of the /i'ii'd device 1I9
2) means for issuing an interrupt to the central processing unit in response to the error flag set in the above-mentioned error flag. (2) The arithmetic device diagnosis 101 method according to claim 1, wherein the arithmetic device is a multi-stage DJ, and each of the above means is provided for each arithmetic device.