JPS6063650A - バッファメモリ一致制御方式 - Google Patents

バッファメモリ一致制御方式

Info

Publication number
JPS6063650A
JPS6063650A JP58172410A JP17241083A JPS6063650A JP S6063650 A JPS6063650 A JP S6063650A JP 58172410 A JP58172410 A JP 58172410A JP 17241083 A JP17241083 A JP 17241083A JP S6063650 A JPS6063650 A JP S6063650A
Authority
JP
Japan
Prior art keywords
address
memory
tag
buffer memory
tag2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58172410A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6336536B2 (enExample
Inventor
Nobuhiko Kuribayashi
栗林　暢彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58172410A priority Critical patent/JPS6063650A/ja
Publication of JPS6063650A publication Critical patent/JPS6063650A/ja
Publication of JPS6336536B2 publication Critical patent/JPS6336536B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP58172410A 1983-09-19 1983-09-19 バッファメモリ一致制御方式 Granted JPS6063650A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58172410A JPS6063650A (ja) 1983-09-19 1983-09-19 バッファメモリ一致制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58172410A JPS6063650A (ja) 1983-09-19 1983-09-19 バッファメモリ一致制御方式

Publications (2)

Publication Number Publication Date
JPS6063650A true JPS6063650A (ja) 1985-04-12
JPS6336536B2 JPS6336536B2 (enExample) 1988-07-20

Family

ID=15941436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58172410A Granted JPS6063650A (ja) 1983-09-19 1983-09-19 バッファメモリ一致制御方式

Country Status (1)

Country Link
JP (1) JPS6063650A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177238A (ja) * 1986-10-17 1988-07-21 アムダール　コーポレーション データ処理装置
JPH01106154A (ja) * 1987-10-20 1989-04-24 Fujitsu Ltd 主記憶一致制御方式

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177238A (ja) * 1986-10-17 1988-07-21 アムダール　コーポレーション データ処理装置
JPH01106154A (ja) * 1987-10-20 1989-04-24 Fujitsu Ltd 主記憶一致制御方式

Also Published As

Publication number Publication date
JPS6336536B2 (enExample) 1988-07-20

Similar Documents

Publication Publication Date Title
US4747043A (en) Multiprocessor cache coherence system
US6023747A (en) Method and system for handling conflicts between cache operation requests in a data processing system
EP0062165A2 (en) Multiprocessors including private and shared caches
US8359443B2 (en) Secure memory access system and method
JPH09152988A (ja) 循環待ち行列作成者エンティティ
JPH04306748A (ja) 情報処理装置
JPH05210581A (ja) 書き戻しキャッシュを具えたコンピューターにおけるコンピューターメモリデータ統合方法
JPH07248967A (ja) メモリ制御方式
JP2005512192A (ja) キャッシュメモリをメインメモリに同期させる方法
JPS6063650A (ja) バッファメモリ一致制御方式
EP0153109A2 (en) Cache coherence system
US4737908A (en) Buffer memory control system
GB2037466A (en) Computer with cache memory
JPH0551933B2 (enExample)
US7181587B1 (en) Mapping an arbitrary number of contiguous memory pages at an arbitrary alignment
JPH05158793A (ja) 並列キャッシュメモリ
JPH05120133A (ja) キヤツシユ装置
JPS6036617B2 (ja) 情報処理システム
JPH1185613A (ja) キャッシュメモリ
JPS58214957A (ja) 計算機システム
JPH04340145A (ja) キャッシュメモリ装置
JPH0528038A (ja) キヤツシユメモリ制御方式
JPS6036618B2 (ja) 情報処理システム
JP2846789B2 (ja) 入出力プロセッサ間通信処理機能を有する情報処理システム
JPH077355B2 (ja) 情報処理装置