US20010001868A1 - Computer system including core logic unit with internal register for peripheral status - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
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- the present invention relates to peripheral devices in computer systems, and more particularly to a system with a centralized core logic register for maintaining status information for peripheral devices in a computer system.
- Computer systems typically include a central processing unit that is coupled to and communicates with a plurality of peripheral devices, typically through a computer system bus.
- peripheral devices can include: data storage devices, such as disk drives and tape drives; data input devices, such as a keyboard or a mouse; data output devices, such as a video display or an audio speaker; and communication devices, such as a network interface controller.
- a peripheral device frequently requires attention from the central processing unit in order to transfer data between the central processing unit and the peripheral device, or to otherwise command and manipulate the peripheral device. This attention is typically triggered by an interrupt, which the peripheral device sends to the central processing unit on order to “interrupt” normal processing by the central processing unit.
- the central processing unit temporarily suspends normal processing and executes a piece of code known as an “interrupt service routine” to perform the required service for the peripheral device. Once the interrupt service routine is complete, the central processing unit resumes normal processing.
- Peripheral devices can activate the same interrupt signal.
- One commonly-used shared interrupt architecture is a daisy-chained structure, in which peripheral devices are “chained” together through one or more interrupt lines. Any peripheral device in the chain can generate an interrupt signal, and this interrupt signal is passed through the chain until it ultimately reaches the central processing unit.
- peripheral devices share a common interrupt bus line; peripheral devices can signal an interrupt to the processor by asserting this interrupt bus line.
- a shared interrupt architecture has certain advantages. It is very simple; typically requiring only a small number of signal lines to carry interrupt signals. It is also expandable, typically allowing additional peripheral devices to be integrated into a computer system without requiring additional lines for interrupt signals.
- a shared interrupt architecture suffers from a major disadvantage. It requires the central processing unit to determine which peripheral device requires processing. This is because all of the peripheral devices generate the same interrupt signal, and the central processing unit cannot tell from the interrupt signal which peripheral devices require servicing. Hence, the central processing unit must typically “poll” the peripheral devices in order to determine which peripheral devices require servicing.
- This polling process can be quite time-consuming.
- the central processing unit may have to poll every peripheral device in the computer system, even though only one peripheral device typically requires servicing at any given time. Polling reduces CPU efficiency, because the CPU must perform multiple bus transactions to poll the peripheral devices, and each bus transaction can require a large number of CPU cycles in a high performance computing system. Polling also ties up the peripheral bus with a large number of polling accesses. Furthermore, polling increases the time required for servicing an interrupt. This may create problems for peripheral devices that require servicing in a timely manner. For example, a network interface controller may require immediate servicing to prevent a buffer of incoming data from overflowing. This immediate servicing may be delayed by polling.
- One embodiment of the present invention provides a computer system that maintains status information for several peripheral devices in a status register, which is located within a core logic unit in the computer system.
- a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing.
- the processor services the interrupt, the processor merely has to read the status register to determine which peripheral device requires processing. This is a very fast operation because the status register is internal to the core logic. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices.
- one embodiment of the present invention provides an apparatus within a core logic device that maintains status information for peripheral devices in a status register.
- This apparatus includes a peripheral communication channel coupled to a number of peripheral devices.
- An updating circuit is located within the core logic unit and is coupled between the peripheral communication channel and the status register. This updating circuit includes a mechanism to update the status register in response to signals containing status information received from the peripheral devices through the peripheral communication channel.
- the communication channel includes a CPU bus.
- the communication channel includes a processor-to-memory bus.
- the peripheral communication channel includes a PCI bus.
- the computer system includes a plurality of central processing units and a single status register coupled between the central processing units and the peripheral communication channel.
- the computer system includes a wire-ORed interrupt structure that couples the peripheral devices to the central processing unit through a core logic unit.
- Another embodiment of the present invention can be characterized as an apparatus within a core logic unit of a computer system for updating a status register to indicate changes in the status of peripheral devices in a computer system.
- This apparatus includes a plurality of address inputs coupled to address lines of a bus, wherein the bus is coupled to the peripheral devices.
- This apparatus also includes an address detecting circuit coupled to a set of higher order bits in the plurality of address inputs. This address detecting circuit is configured to detect an address in a reserved range of addresses specified by the set of higher order bits.
- the apparatus additionally includes a decoder circuit coupled to a set of lower order bits in the plurality of address inputs. This decoder circuit detects references to particular addresses in the reserved range of addresses.
- a status register is coupled to a set of outputs from the decoder circuit, so that a reference to a particular address in the reserved range of addresses by a peripheral device feeds through the decoder and updates status information for the peripheral device in the status register.
- the status register also includes outputs coupled to a central processing unit so that the status register can be read by the central processing unit.
- the address detecting circuit includes a decoder. In another variation on this embodiment, the address detecting circuit includes a comparator.
- the core logic unit resides inside of a single semiconductor chip. In a further variation on this embodiment, the core logic unit resides inside of a semiconductor chip set.
- FIG. 1 illustrates a prior art computer system, wherein a processor 100 reads status registers 112 , 122 and 132 located at respective peripheral devices 110 , 120 and 130 .
- FIG. 2 illustrates a computer system including a processor 100 with a core logic unit 103 with an internal status register 107 for storing the status of peripheral devices in accordance with an embodiment of the present invention.
- FIG. 3 illustrates a computer system including multiple processors with a single status register 107 within core logic unit 103 for storing the status of peripheral devices in accordance with an embodiment of the present invention.
- FIG. 4 illustrates the structure of a processing system in accordance with an embodiment of the present invention.
- FIG. 5 illustrates the structure of status register 107 in accordance with an embodiment of the present invention.
- FIG. 6 illustrates how status register updating is accomplished through memory mapping in accordance with an embodiment of the present invention.
- FIG. 7 illustrates some of the functional units within processor 100 in accordance with an embodiment of the present invention.
- FIG. 8 illustrates some of the internal structure of north bridge 408 in accordance with an embodiment of the present invention.
- FIG. 9 illustrates part of the internal structure of status register unit 712 in accordance with an embodiment of the present invention.
- FIG. 10 is a flow chart illustrating how a peripheral device updates status register 107 in accordance with an embodiment of the present invention.
- FIG. 11 is a flowchart illustrating how processor 100 uses information from status register 107 to trigger an appropriate interrupt service routine in accordance with an embodiment of the present invention.
- FIG. 1 illustrates a prior art computer system, wherein a processor 100 reads status registers 112 , 122 and 132 , located at respective peripheral devices 110 , 120 and 130 .
- Processor 100 is coupled to memory 101 and bus 105 through core logic unit 103 .
- Processor 100 can access peripheral devices 110 , 120 and 130 through bus 105 .
- processor 100 polls status registers 112 , 122 and 132 in order to determine which of peripheral devices 110 , 120 and 130 require processing. This polling requires multiple operations over bus 105 .
- FIG. 2 illustrates a computer system including a processor 100 with a core logic unit 103 with an internal status register 107 for storing the status of peripheral devices in accordance with an embodiment of the present invention.
- processor 100 is coupled to memory 101 and bus 105 through core logic unit 103 .
- Processor 100 can access peripheral devices 110 , 120 and 130 through bus 105 .
- processor 100 references status register 107 during interrupts to determine the status of peripheral devices 110 , 120 and 130 . This is a very fast operation because status register 107 is internal to core logic unit 103 . A reference to status register 107 by processor 100 requires no accesses across bus 105 to poll peripheral devices 110 , 120 and 130 .
- peripheral devices 110 , 120 and 130 are responsible for updating status information in status register 107 . This updating only needs to occur when the status of a peripheral device changes.
- a peripheral device such as peripheral device 110
- processor 100 references status register 107 located within core logic unit 103 . This is not as fast as referencing a status register within processor 100 , but it does not require any special modifications to processor 100 in order to implement it.
- processor 100 may be any type of computational engine for a computer system. This includes, but is not limited to, mainframe processors, microprocessors, and micro-controllers.
- Bus 105 may be any type of communication channel for coupling a processor to other devices in a computer system, including peripheral devices, memory devices and other processors. This includes, but is not limited to, buses such as the PCI bus, and buses that include signals to maintain coherency between multiple caches in a shared memory multiprocessor system.
- Peripheral devices 110 , 120 and 130 may be any type of peripheral devices that can coupled to a computer system. These include, but are not limited to: data storage devices, such as disk drives and tape drives; data input devices, such as a keyboard or a mouse; data output devices, such as a video display or an audio speaker; and communication devices, such as a network interface controller.
- FIG. 3 illustrates a computer system including multiple processors with a single status register 107 within core logic unit 103 for storing the status of peripheral devices in accordance with an embodiment of the present invention.
- processors 100 , 300 and 310 include caches 103 , 303 and 313 , respectively.
- Caches 103 , 303 and 313 store copies of code and data from memory 320 for use by processors 100 , 300 and 310 respectively.
- Processors 100 , 300 and 310 are coupled bus 320 , as is core logic unit 103 .
- Core logic unit 103 couples bus 320 to memory 101 and bus 105 .
- Peripheral devices 110 , 120 and 130 are coupled to bus 105 .
- bus 320 includes signals to maintain coherency between data stored memory 320 as well as copies of the data stored in caches 103 , 303 and 313 . Coherence is typically maintained by invalidating an entry in a cache if a copy of the data contained in the entry is modified in another cache or in memory 320 . Processors 100 , 300 and 310 use “snoop logic” to “snoop” or listen in to a set of signals on bus 320 to determine whether to invalidate an entry in a local processor cache.
- referencing status register 107 within core logic unit 103 is not as fast as referencing a status register located within processor 100 .
- status register 107 does not require any special modifications to a processor in order to implement it.
- FIG. 4 illustrates the structure of a processing system in accordance with an embodiment of the present invention.
- CPU 404 is coupled through north bridge 408 to memory 405 and to bus 430 .
- Memory 405 can be any type of semiconductor memory that can be used in a computer system.
- Bus 430 can by any type of computer system bus. In one embodiment, bus 430 includes a PCI bus.
- Bus 430 is coupled to graphics module 414 , which processes graphical images for output to display 416 .
- Bus 430 is additionally coupled to sound card 415 , which generates audio signals. Sound card 415 is coupled to speaker 417 , so that the audio signals generated by sound card 415 are outputted through speaker 417 .
- CPU 404 is additionally coupled with south bridge 410 through north bridge 408 .
- North bridge 408 and south bridge 410 form part of the “core logic” for the computer system. This core logic ties together and coordinates operations of components in the computer system.
- South bridge 410 is coupled with disk 406 , which may include any type of non-volatile storage device. This includes, but is not limited to, magnetic, optical, magneto-optical and flash memory storage devices.
- South bridge 410 is also coupled with bus 432 , which can be any type of computer system bus.
- bus 432 includes an ISA bus. Bus 432 allows CPU 404 to communicate with BIOS ROM 412 and modem 422 , which are coupled to bus 432 . Modem 422 may be any type of modem through which a computer system can communicate across a telephone line.
- status register 107 is located within north bridge 408 .
- status register 107 may include a stand-alone register in the computer system, not within north bridge 408 .
- FIG. 5 illustrates the structure of status register 107 in accordance with an embodiment of the present invention.
- status register 107 includes a plurality of bits containing status information for peripheral devices in the computer system. These bits include, status device 1 502 , status device 2 504 , status device 3 506 and status device N 508 . When a status bit is set, this indicates that the corresponding device requires servicing.
- status register 107 includes more than one bit of status information for each device. These bits contain additional status information for each device, beyond the mere fact that a particular device requires servicing. For example, the status information may specify the type of service the device requires.
- FIG. 6 illustrates how status register updating is accomplished through memory mapping in accordance with an embodiment of the present invention.
- address space 600 is an address space for address lines on a bus, such as bus 105 from FIG. 1.
- Address space 600 includes a BIOS image 610 at the lower end of address space 600 .
- BIOS image 610 contains code to implement lower-level operating system functions.
- Address space 600 additionally includes physical memory 630 at the upper end of address space 600 .
- Physical memory 630 contains code and data used by a processor to execute programs.
- a section of address space 600 between BIOS image 610 and physical memory 630 , is reserved for updating status register 107 . There is no actual memory in these address locations. However, accesses to these locations update the contents of status register 107 .
- an accesses to address 640 sets the status bit for device 1 502 to indicate that device 1 requires servicing, and an access to address 642 resets bit 502 to indicate that device 1 does not require servicing.
- accesses to addresses 644 , 648 and 652 set status bits 504 , 506 and 508 , respectively, and accesses to addresses 646 , 650 and 654 reset the same status bits.
- FIG. 7 illustrates some of the functional units within processor 100 in accordance with an embodiment of the present invention.
- processor 100 includes integer ALU (arithmetic logic unit) 702 and floating point unit 704 , which perform computational operations.
- Processor 100 also includes controller 706 , which can coordinate actions of functional units within processor 100 .
- a number of units within processor 100 are coupled to bus 105 .
- These include L 1 cache 708 , which stores instructions and data used by processor 100 during computational operations.
- L 1 cache 708 includes separate instruction and data caches.
- Snoop logic 710 is also coupled to bus 105 .
- Snoop logic 710 listens to signals on bus 105 that contain “snoop” information.
- Snoop logic 710 uses this snoop information to invalidate entries within L 1 cache 708 .
- Processor 105 additionally includes registers 712 , which temporarily store data values for computational operations within processor 105 .
- FIG. 8 illustrates some of the internal structure of north bridge 408 in accordance with an embodiment of the present invention.
- status register 107 resides within status register unit 712 within north bridge 408 .
- North bridge 408 additionally includes a switch 805 , which switches data between CPU 404 , memory 405 and bus 430 .
- status register unit 712 listens to accesses on bus 430 to detect accesses to the reserved range of addresses 620 .
- FIG. 9 illustrates part of the internal structure of status register unit 712 in accordance with one embodiment of the present invention.
- address lines from bus 105 are monitored by logic within status register unit 712 to detect references to reserved addresses 620 . More particularly, high order address bits from bus 105 feed into inputs of decoder 900 . If the high order address bits 902 specify an address in the reserved addresses 620 , decoder 900 generates a register hit signal 906 , which feeds into an enable input of decoder 910 . In another embodiment, high order address bits 902 feed into a comparator circuit that performs the same address detection function. In general, any commonly known address detection circuitry can be used to detect addresses in the reserved range 620 .
- Low order address bits 904 feed into inputs of decoder 910 . These low order address bits are used to select various outputs of decoder 910 . These outputs either set or reset bits in status register 107 .
- each bit of status register 107 is stored in a bistable circuit which includes two NAND gates connected circularly as shown in FIG. 9. Each NAND gate pair takes two inputs from decoder 910 . If the top input is asserted low, the bit is set, and if the bottom input is asserted low the bit is reset. For example, an access to address 640 causes the top output of decoder 910 to be asserted low, which causes to corresponding bit to be asserted to a one value.
- an access to address 642 causes the next lower output of decoder 910 to be asserted low, which resets the same bit.
- status read signal 912 is asserted, the attached drivers are activated to read the bits out from status register 107 .
- This embodiment illustrates one of many possible structures for status register 107 . In general, any other commonly known structure for a register may be used.
- FIG. 10 is a flow chart illustrating how a peripheral device updates status register 107 in accordance with an embodiment of the present invention.
- the peripheral device starts at state 1000 and proceeds to state 1002 .
- the peripheral device detects a change its status. This change in status may indicate that some servicing is required. For example, data may be ready to be transferred the to processor 100 .
- the peripheral device then proceeds to state 1004 .
- the peripheral device performs a bus master operation on bus 105 to update the status register 107 to indicate that the device requires servicing.
- the peripheral device then proceeds to state 1006 .
- the peripheral device generates an interrupt to indicate to processor 100 that a peripheral device requires servicing.
- the peripheral device then proceeds to state 1008 , which is an end state.
- FIG. 11 is a flowchart illustrating how processor 100 uses information from status register 107 to trigger an interrupt service routine in accordance with an embodiment of the present invention.
- Processor 100 starts in state 1100 and proceeds to state 1102 .
- state 1102 processor 100 receives an interrupt from one of the peripheral devices coupled to bus 105 .
- Processor 100 then proceeds to state 1104 , in which processor 100 saves state in order to process the interrupt.
- Processor 100 then proceeds to state 1106 .
- state 1106 processor 100 fetches interrupt instructions from the location pointed to by an interrupt vector.
- Processor 100 then proceeds to state 1108 .
- processor 100 copies status register 107 to a processor register in order to examine the contents of status register 107 .
- the system then proceeds to state 1110 .
- processor 100 branches based upon the contents of status register 107 to various interrupt service routines 1112 , 1114 and 1116 . This branching may actually require a number of instructions to test status register 107 and to perform appropriate conditional branching. If status register 107 indicates that device 1 requires processing, processor 100 branches to state 1112 , which is the start of an interrupt service routine to service device 1 . This interrupt service routine generally includes a large number of interrupt service instructions, which are not shown. After the interrupt service routine is complete processor 100 proceeds to state 1118 , which is an end state. If status register 107 indicates that device 2 requires processing, processor 100 branches to state 1114 , which is the start of an interrupt service routine to service device 2 .
- processor 100 proceeds to state 1118 , which is an end state. If status register 107 indicates that device N requires processing, processor 100 branches to state 1116 , which is the start of an interrupt service routine to service device N. After this interrupt service routine is complete processor 100 proceeds to state 1118 , which is an end state.
- the process of mapping peripheral devices to particular bits of status register 107 , and the process of assigning particular interrupt service routines to particular peripheral devices are performed as initialization routines during system initialization.
- the code to perform these functions resides in a read only memory, which is read during system boot up.
- Core logic circuitry within a computer system that interfaces a processor to a memory and a peripheral bus and performs other functions.
- Snoop bus a bus that carries signals to maintain consistency or coherency between multiple caches in a computer system including multiple processors.
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Abstract
Description
- The subject matter of this application is related to the subject matter in three co-pending non-provisional applications by the same inventor as the instant application and filed on the same day as the instant application, entitled: “Processor with Internal Register for Peripheral Status,” having serial number TO BE ASSIGNED, and filing date TO BE ASSIGNED (Attorney Docket No. MEI97-138400); “Method for Operating Processor with Internal Register for Peripheral Status,” having serial number TO BE ASSIGNED, and filing date TO BE ASSIGNED (Attorney Docket No. MEI97-138402); and “Method for Operating Core Logic Unit with Internal Register for Peripheral Status,” having serial number TO BE ASSIGNED, and filing date TO BE ASSIGNED (Attorney Docket No. MEI97-138403).
- 1. Field of the Invention
- The present invention relates to peripheral devices in computer systems, and more particularly to a system with a centralized core logic register for maintaining status information for peripheral devices in a computer system.
- 2. Related Art
- Computer systems typically include a central processing unit that is coupled to and communicates with a plurality of peripheral devices, typically through a computer system bus. These peripheral devices can include: data storage devices, such as disk drives and tape drives; data input devices, such as a keyboard or a mouse; data output devices, such as a video display or an audio speaker; and communication devices, such as a network interface controller. A peripheral device frequently requires attention from the central processing unit in order to transfer data between the central processing unit and the peripheral device, or to otherwise command and manipulate the peripheral device. This attention is typically triggered by an interrupt, which the peripheral device sends to the central processing unit on order to “interrupt” normal processing by the central processing unit. During an interrupt, the central processing unit temporarily suspends normal processing and executes a piece of code known as an “interrupt service routine” to perform the required service for the peripheral device. Once the interrupt service routine is complete, the central processing unit resumes normal processing.
- Many computer systems use a shared interrupt architecture, in which a plurality of peripheral devices can activate the same interrupt signal. One commonly-used shared interrupt architecture is a daisy-chained structure, in which peripheral devices are “chained” together through one or more interrupt lines. Any peripheral device in the chain can generate an interrupt signal, and this interrupt signal is passed through the chain until it ultimately reaches the central processing unit. In another commonly-used shared interrupt architecture, peripheral devices share a common interrupt bus line; peripheral devices can signal an interrupt to the processor by asserting this interrupt bus line.
- A shared interrupt architecture has certain advantages. It is very simple; typically requiring only a small number of signal lines to carry interrupt signals. It is also expandable, typically allowing additional peripheral devices to be integrated into a computer system without requiring additional lines for interrupt signals.
- However, a shared interrupt architecture suffers from a major disadvantage. It requires the central processing unit to determine which peripheral device requires processing. This is because all of the peripheral devices generate the same interrupt signal, and the central processing unit cannot tell from the interrupt signal which peripheral devices require servicing. Hence, the central processing unit must typically “poll” the peripheral devices in order to determine which peripheral devices require servicing.
- This polling process can be quite time-consuming. The central processing unit may have to poll every peripheral device in the computer system, even though only one peripheral device typically requires servicing at any given time. Polling reduces CPU efficiency, because the CPU must perform multiple bus transactions to poll the peripheral devices, and each bus transaction can require a large number of CPU cycles in a high performance computing system. Polling also ties up the peripheral bus with a large number of polling accesses. Furthermore, polling increases the time required for servicing an interrupt. This may create problems for peripheral devices that require servicing in a timely manner. For example, a network interface controller may require immediate servicing to prevent a buffer of incoming data from overflowing. This immediate servicing may be delayed by polling.
- What is needed is a system for retrieving status information from peripheral devices in a shared interrupt architecture that reduces the amount of time and bus activity required to determine the status of the peripheral devices.
- One embodiment of the present invention provides a computer system that maintains status information for several peripheral devices in a status register, which is located within a core logic unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor merely has to read the status register to determine which peripheral device requires processing. This is a very fast operation because the status register is internal to the core logic. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a core logic device that maintains status information for peripheral devices in a status register. This apparatus includes a peripheral communication channel coupled to a number of peripheral devices. An updating circuit is located within the core logic unit and is coupled between the peripheral communication channel and the status register. This updating circuit includes a mechanism to update the status register in response to signals containing status information received from the peripheral devices through the peripheral communication channel.
- In another embodiment of the present invention, the communication channel includes a CPU bus. (In a variation on this embodiment, the communication channel includes a processor-to-memory bus.) In another embodiment, the peripheral communication channel includes a PCI bus.
- In another embodiment of the present invention, the computer system includes a plurality of central processing units and a single status register coupled between the central processing units and the peripheral communication channel.
- In another embodiment of the present invention, the computer system includes a wire-ORed interrupt structure that couples the peripheral devices to the central processing unit through a core logic unit.
- Another embodiment of the present invention can be characterized as an apparatus within a core logic unit of a computer system for updating a status register to indicate changes in the status of peripheral devices in a computer system. This apparatus includes a plurality of address inputs coupled to address lines of a bus, wherein the bus is coupled to the peripheral devices. This apparatus also includes an address detecting circuit coupled to a set of higher order bits in the plurality of address inputs. This address detecting circuit is configured to detect an address in a reserved range of addresses specified by the set of higher order bits. The apparatus additionally includes a decoder circuit coupled to a set of lower order bits in the plurality of address inputs. This decoder circuit detects references to particular addresses in the reserved range of addresses. A status register is coupled to a set of outputs from the decoder circuit, so that a reference to a particular address in the reserved range of addresses by a peripheral device feeds through the decoder and updates status information for the peripheral device in the status register. The status register also includes outputs coupled to a central processing unit so that the status register can be read by the central processing unit.
- In a variation on this embodiment, the address detecting circuit includes a decoder. In another variation on this embodiment, the address detecting circuit includes a comparator.
- In a variation in this embodiment, the core logic unit resides inside of a single semiconductor chip. In a further variation on this embodiment, the core logic unit resides inside of a semiconductor chip set.
- FIG. 1 illustrates a prior art computer system, wherein a
processor 100 reads status registers 112, 122 and 132 located at respectiveperipheral devices - FIG. 2 illustrates a computer system including a
processor 100 with acore logic unit 103 with aninternal status register 107 for storing the status of peripheral devices in accordance with an embodiment of the present invention. - FIG. 3 illustrates a computer system including multiple processors with a
single status register 107 withincore logic unit 103 for storing the status of peripheral devices in accordance with an embodiment of the present invention. - FIG. 4 illustrates the structure of a processing system in accordance with an embodiment of the present invention.
- FIG. 5 illustrates the structure of
status register 107 in accordance with an embodiment of the present invention. - FIG. 6 illustrates how status register updating is accomplished through memory mapping in accordance with an embodiment of the present invention.
- FIG. 7 illustrates some of the functional units within
processor 100 in accordance with an embodiment of the present invention. - FIG. 8 illustrates some of the internal structure of
north bridge 408 in accordance with an embodiment of the present invention. - FIG. 9 illustrates part of the internal structure of
status register unit 712 in accordance with an embodiment of the present invention. - FIG. 10 is a flow chart illustrating how a peripheral device
updates status register 107 in accordance with an embodiment of the present invention. - FIG. 11 is a flowchart illustrating how
processor 100 uses information fromstatus register 107 to trigger an appropriate interrupt service routine in accordance with an embodiment of the present invention. - The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
- FIG. 1 illustrates a prior art computer system, wherein a
processor 100 reads status registers 112, 122 and 132, located at respectiveperipheral devices Processor 100 is coupled tomemory 101 andbus 105 throughcore logic unit 103.Processor 100 can accessperipheral devices bus 105. In response to an interrupt,processor 100 polls status registers 112, 122 and 132 in order to determine which ofperipheral devices bus 105. - FIG. 2 illustrates a computer system including a
processor 100 with acore logic unit 103 with aninternal status register 107 for storing the status of peripheral devices in accordance with an embodiment of the present invention. As in the system illustrated in FIG. 1,processor 100 is coupled tomemory 101 andbus 105 throughcore logic unit 103.Processor 100 can accessperipheral devices bus 105. - However, the embodiment illustrated in FIG. 2 differs in a number of respects from the system illustrated in FIG. 1. In FIG. 2,
processor 100references status register 107 during interrupts to determine the status ofperipheral devices status register 107 is internal tocore logic unit 103. A reference to status register 107 byprocessor 100 requires no accesses acrossbus 105 to pollperipheral devices - Instead,
peripheral devices status register 107. This updating only needs to occur when the status of a peripheral device changes. In order to update a status register, a peripheral device, such asperipheral device 110, writes to a reserved memory location in the address space ofbus 105. No memory actually resides in this reserved address space. Instead, logic attached to the status register intercepts references to these reserved locations, and uses these references to appropriately update status registers to reflect the indicated change in status of a peripheral device. - In an alternative embodiment,
processor 100references status register 107 located withincore logic unit 103. This is not as fast as referencing a status register withinprocessor 100, but it does not require any special modifications toprocessor 100 in order to implement it. - In
general processor 100 may be any type of computational engine for a computer system. This includes, but is not limited to, mainframe processors, microprocessors, and micro-controllers.Bus 105 may be any type of communication channel for coupling a processor to other devices in a computer system, including peripheral devices, memory devices and other processors. This includes, but is not limited to, buses such as the PCI bus, and buses that include signals to maintain coherency between multiple caches in a shared memory multiprocessor system.Peripheral devices - FIG. 3 illustrates a computer system including multiple processors with a
single status register 107 withincore logic unit 103 for storing the status of peripheral devices in accordance with an embodiment of the present invention. In this embodiment,processors caches Caches processors Processors core logic unit 103.Core logic unit 103 couples bus 320 tomemory 101 andbus 105.Peripheral devices bus 105. - In this embodiment, bus320 includes signals to maintain coherency between data stored memory 320 as well as copies of the data stored in
caches Processors - Note that referencing
status register 107 withincore logic unit 103 is not as fast as referencing a status register located withinprocessor 100. However,status register 107 does not require any special modifications to a processor in order to implement it. - FIG. 4 illustrates the structure of a processing system in accordance with an embodiment of the present invention. In the illustrated embodiment,
CPU 404 is coupled throughnorth bridge 408 tomemory 405 and to bus 430.Memory 405 can be any type of semiconductor memory that can be used in a computer system. Bus 430 can by any type of computer system bus. In one embodiment, bus 430 includes a PCI bus. Bus 430 is coupled tographics module 414, which processes graphical images for output to display 416. Bus 430 is additionally coupled tosound card 415, which generates audio signals.Sound card 415 is coupled tospeaker 417, so that the audio signals generated bysound card 415 are outputted throughspeaker 417. - In the illustrated embodiment,
CPU 404 is additionally coupled withsouth bridge 410 throughnorth bridge 408.North bridge 408 andsouth bridge 410 form part of the “core logic” for the computer system. This core logic ties together and coordinates operations of components in the computer system.South bridge 410 is coupled withdisk 406, which may include any type of non-volatile storage device. This includes, but is not limited to, magnetic, optical, magneto-optical and flash memory storage devices.South bridge 410 is also coupled with bus 432, which can be any type of computer system bus. In one embodiment, bus 432 includes an ISA bus. Bus 432 allowsCPU 404 to communicate withBIOS ROM 412 andmodem 422, which are coupled to bus 432.Modem 422 may be any type of modem through which a computer system can communicate across a telephone line. - In FIG. 4,
status register 107 is located withinnorth bridge 408. In another embodiment,status register 107 may include a stand-alone register in the computer system, not withinnorth bridge 408. - FIG. 5 illustrates the structure of
status register 107 in accordance with an embodiment of the present invention. In the illustrated embodiment,status register 107 includes a plurality of bits containing status information for peripheral devices in the computer system. These bits include,status device 1 502,status device 2 504, status device 3 506 and status device N 508. When a status bit is set, this indicates that the corresponding device requires servicing. In other embodiments of the present invention,status register 107 includes more than one bit of status information for each device. These bits contain additional status information for each device, beyond the mere fact that a particular device requires servicing. For example, the status information may specify the type of service the device requires. - FIG. 6 illustrates how status register updating is accomplished through memory mapping in accordance with an embodiment of the present invention. In this embodiment,
address space 600 is an address space for address lines on a bus, such asbus 105 from FIG. 1.Address space 600 includes aBIOS image 610 at the lower end ofaddress space 600.BIOS image 610 contains code to implement lower-level operating system functions.Address space 600 additionally includesphysical memory 630 at the upper end ofaddress space 600.Physical memory 630 contains code and data used by a processor to execute programs. A section ofaddress space 600, betweenBIOS image 610 andphysical memory 630, is reserved for updatingstatus register 107. There is no actual memory in these address locations. However, accesses to these locations update the contents ofstatus register 107. For example, an accesses to address 640 sets the status bit fordevice 1 502 to indicate thatdevice 1 requires servicing, and an access to address 642 resets bit 502 to indicate thatdevice 1 does not require servicing. Similarly, accesses toaddresses 644, 648 and 652 setstatus bits 504, 506 and 508, respectively, and accesses toaddresses 646, 650 and 654 reset the same status bits. - FIG. 7 illustrates some of the functional units within
processor 100 in accordance with an embodiment of the present invention. In the illustrated embodiment,processor 100 includes integer ALU (arithmetic logic unit) 702 and floatingpoint unit 704, which perform computational operations.Processor 100 also includescontroller 706, which can coordinate actions of functional units withinprocessor 100. A number of units withinprocessor 100 are coupled tobus 105. These includeL1 cache 708, which stores instructions and data used byprocessor 100 during computational operations. In some embodiments,L1 cache 708 includes separate instruction and data caches. Snooplogic 710 is also coupled tobus 105. Snooplogic 710 listens to signals onbus 105 that contain “snoop” information. Snooplogic 710 uses this snoop information to invalidate entries withinL1 cache 708.Processor 105 additionally includesregisters 712, which temporarily store data values for computational operations withinprocessor 105. - FIG. 8 illustrates some of the internal structure of
north bridge 408 in accordance with an embodiment of the present invention. In this embodiment,status register 107 resides withinstatus register unit 712 withinnorth bridge 408.North bridge 408 additionally includes aswitch 805, which switches data betweenCPU 404,memory 405 and bus 430. In this embodiment,status register unit 712 listens to accesses on bus 430 to detect accesses to the reserved range ofaddresses 620. - FIG. 9 illustrates part of the internal structure of
status register unit 712 in accordance with one embodiment of the present invention. In this embodiment, address lines frombus 105 are monitored by logic withinstatus register unit 712 to detect references to reserved addresses 620. More particularly, high order address bits frombus 105 feed into inputs ofdecoder 900. If the highorder address bits 902 specify an address in the reserved addresses 620,decoder 900 generates a register hitsignal 906, which feeds into an enable input ofdecoder 910. In another embodiment, highorder address bits 902 feed into a comparator circuit that performs the same address detection function. In general, any commonly known address detection circuitry can be used to detect addresses in thereserved range 620. Loworder address bits 904 feed into inputs ofdecoder 910. These low order address bits are used to select various outputs ofdecoder 910. These outputs either set or reset bits instatus register 107. In the illustrated embodiment, each bit ofstatus register 107 is stored in a bistable circuit which includes two NAND gates connected circularly as shown in FIG. 9. Each NAND gate pair takes two inputs fromdecoder 910. If the top input is asserted low, the bit is set, and if the bottom input is asserted low the bit is reset. For example, an access to address 640 causes the top output ofdecoder 910 to be asserted low, which causes to corresponding bit to be asserted to a one value. In contrast, an access to address 642 causes the next lower output ofdecoder 910 to be asserted low, which resets the same bit. Finally, when status read signal 912 is asserted, the attached drivers are activated to read the bits out fromstatus register 107. This embodiment illustrates one of many possible structures forstatus register 107. In general, any other commonly known structure for a register may be used. - FIG. 10 is a flow chart illustrating how a peripheral device
updates status register 107 in accordance with an embodiment of the present invention. In this embodiment, the peripheral device starts atstate 1000 and proceeds tostate 1002. Instate 1002, the peripheral device detects a change its status. This change in status may indicate that some servicing is required. For example, data may be ready to be transferred the toprocessor 100. The peripheral device then proceeds tostate 1004. Instate 1004, the peripheral device performs a bus master operation onbus 105 to update thestatus register 107 to indicate that the device requires servicing. The peripheral device then proceeds tostate 1006. Instate 1006, the peripheral device generates an interrupt to indicate toprocessor 100 that a peripheral device requires servicing. The peripheral device then proceeds tostate 1008, which is an end state. - FIG. 11 is a flowchart illustrating how
processor 100 uses information fromstatus register 107 to trigger an interrupt service routine in accordance with an embodiment of the present invention.Processor 100 starts instate 1100 and proceeds tostate 1102. Instate 1102,processor 100 receives an interrupt from one of the peripheral devices coupled tobus 105.Processor 100 then proceeds tostate 1104, in whichprocessor 100 saves state in order to process the interrupt.Processor 100 then proceeds tostate 1106. Instate 1106,processor 100 fetches interrupt instructions from the location pointed to by an interrupt vector.Processor 100 then proceeds tostate 1108. Instate 1108,processor 100copies status register 107 to a processor register in order to examine the contents ofstatus register 107. The system then proceeds tostate 1110. - In
state 1110,processor 100 branches based upon the contents ofstatus register 107 to various interruptservice routines status register 107 and to perform appropriate conditional branching. Ifstatus register 107 indicates thatdevice 1 requires processing,processor 100 branches tostate 1112, which is the start of an interrupt service routine toservice device 1. This interrupt service routine generally includes a large number of interrupt service instructions, which are not shown. After the interrupt service routine iscomplete processor 100 proceeds tostate 1118, which is an end state. Ifstatus register 107 indicates thatdevice 2 requires processing,processor 100 branches tostate 1114, which is the start of an interrupt service routine toservice device 2. After this interrupt service routine is complete,processor 100 proceeds tostate 1118, which is an end state. Ifstatus register 107 indicates that device N requires processing,processor 100 branches tostate 1116, which is the start of an interrupt service routine to service device N. After this interrupt service routine iscomplete processor 100 proceeds tostate 1118, which is an end state. - In one embodiment of the present invention, the process of mapping peripheral devices to particular bits of
status register 107, and the process of assigning particular interrupt service routines to particular peripheral devices are performed as initialization routines during system initialization. In one embodiment of the present invention, the code to perform these functions resides in a read only memory, which is read during system boot up. - Core logic—circuitry within a computer system that interfaces a processor to a memory and a peripheral bus and performs other functions.
- Snoop bus—a bus that carries signals to maintain consistency or coherency between multiple caches in a computer system including multiple processors.
- The foregoing descriptions of embodiments of the invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the invention to the forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in the art.
Claims (19)
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US09/764,631 US6393507B2 (en) | 1998-08-10 | 2001-01-17 | Computer system including core logic unit with internal register for peripheral status |
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US09/764,631 US6393507B2 (en) | 1998-08-10 | 2001-01-17 | Computer system including core logic unit with internal register for peripheral status |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6678838B1 (en) * | 1999-08-23 | 2004-01-13 | Advanced Micro Devices, Inc. | Method to track master contribution information in a write buffer |
US20070198757A1 (en) * | 2006-02-07 | 2007-08-23 | Samsung Electronics Co., Ltd. | Data processing system with hardware polling processor |
US20150109026A1 (en) * | 2013-10-22 | 2015-04-23 | Hon Hai Precision Industry Co., Ltd. | Electronic device assembly |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6219720B1 (en) * | 1998-08-10 | 2001-04-17 | Micron Technology, Inc. | Core logic unit with internal register for peripheral status |
US6738895B1 (en) * | 2000-08-31 | 2004-05-18 | Micron Technology, Inc. | Method and system for substantially registerless processing |
US6813730B2 (en) * | 2001-07-11 | 2004-11-02 | Dell Products L.P. | Method, computer program product, and system for detecting a peripheral device in a computer system |
US20040078708A1 (en) * | 2002-05-17 | 2004-04-22 | Chuang Li | Methods for facilitating the installation of computer devices |
US7565471B2 (en) * | 2005-09-16 | 2009-07-21 | Emulex Design & Manufacturing Corporation | Message signaled interrupt extended (MSI-X) auto clear and failsafe lock |
US20080209089A1 (en) * | 2007-02-27 | 2008-08-28 | Integrated Device Technology, Inc. | Packet-Based Parallel Interface Protocol For A Serial Buffer Having A Parallel Processor Port |
US8516163B2 (en) * | 2007-02-27 | 2013-08-20 | Integrated Device Technology, Inc. | Hardware-based concurrent direct memory access (DMA) engines on serial rapid input/output SRIO interface |
US7870313B2 (en) * | 2007-02-27 | 2011-01-11 | Integrated Device Technology, Inc. | Method and structure to support system resource access of a serial device implementating a lite-weight protocol |
US8094677B2 (en) | 2007-02-27 | 2012-01-10 | Integrated Device Technology, Inc. | Multi-bus structure for optimizing system performance of a serial buffer |
US7617346B2 (en) * | 2007-02-27 | 2009-11-10 | Integrated Device Technology, Inc. | Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latency |
US20100046516A1 (en) * | 2007-06-26 | 2010-02-25 | Media Patents, S.L. | Methods and Devices for Managing Multicast Traffic |
EP2078376B1 (en) * | 2007-06-26 | 2010-12-29 | Media Patents, S. L. | Router for managing multicast groups |
US8184630B2 (en) * | 2007-10-15 | 2012-05-22 | Media Patents, S.L. | Method for managing multicast traffic in a data network and network equipment using said method |
US8064449B2 (en) * | 2007-10-15 | 2011-11-22 | Media Patents, S.L. | Methods and apparatus for managing multicast traffic |
WO2009056175A1 (en) * | 2007-10-30 | 2009-05-07 | Soporte Multivendor S.L. | Method for managing multicast traffic between routers communicating by means of a protocol integrating the pim protocol; and router and switch involved in said method |
US9031068B2 (en) * | 2008-02-01 | 2015-05-12 | Media Patents, S.L. | Methods and apparatus for managing multicast traffic through a switch |
WO2009095041A1 (en) * | 2008-02-01 | 2009-08-06 | Soporte Multivendor S.L. | Method for managing multicast traffic through a switch operating in the layer 2 of the osi model, and router and switch involved in said method |
WO2009109684A1 (en) * | 2008-03-05 | 2009-09-11 | Media Patents, S. L. | Method for monitoring or managing devices connected to a data network |
US8189584B2 (en) * | 2009-07-27 | 2012-05-29 | Media Patents, S. L. | Multicast traffic management in a network interface |
US20110149960A1 (en) * | 2009-12-17 | 2011-06-23 | Media Patents, S.L. | Method and apparatus for filtering multicast packets |
US8495497B2 (en) * | 2010-01-28 | 2013-07-23 | International Business Machines Corporation | Graphical guides to aid user selection of groups of instruction packages |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3881174A (en) | 1974-01-18 | 1975-04-29 | Process Computer Systems Inc | Peripheral interrupt apparatus for digital computer system |
US3996561A (en) * | 1974-04-23 | 1976-12-07 | Honeywell Information Systems, Inc. | Priority determination apparatus for serially coupled peripheral interfaces in a data processing system |
US4024505A (en) | 1974-11-18 | 1977-05-17 | Compucorp | Interface system for coupling an indeterminate number of peripheral devices to a central processing unit |
US4090238A (en) | 1976-10-04 | 1978-05-16 | Rca Corporation | Priority vectored interrupt using direct memory access |
US4181941A (en) * | 1978-03-27 | 1980-01-01 | Godsey Ernest E | Interrupt system and method |
US4240140A (en) | 1978-12-26 | 1980-12-16 | Honeywell Information Systems Inc. | CRT display terminal priority interrupt apparatus for generating vectored addresses |
US4768149A (en) | 1985-08-29 | 1988-08-30 | International Business Machines Corporation | System for managing a plurality of shared interrupt handlers in a linked-list data structure |
JPH01162967A (en) * | 1987-12-18 | 1989-06-27 | Fujitsu Ltd | Method and device for interruption processing |
US5317707A (en) | 1989-10-20 | 1994-05-31 | Texas Instruments Incorporated | Expanded memory interface for supporting expanded, conventional or extended memory for communication between an application processor and an external processor |
JPH05509425A (en) | 1990-05-18 | 1993-12-22 | スター・セミコンダクター・コーポレーション | Programmable signal processor architecture |
US5678025A (en) | 1992-12-30 | 1997-10-14 | Intel Corporation | Cache coherency maintenance of non-cache supporting buses |
EP0640929A3 (en) | 1993-08-30 | 1995-11-29 | Advanced Micro Devices Inc | Inter-processor communication via post office RAM. |
US5462752A (en) | 1994-07-28 | 1995-10-31 | Prp, Inc. | Inhibition of platelet binding |
US5578953A (en) | 1995-09-22 | 1996-11-26 | Airnet Communications Corporation | Self-resetting status register |
US5848237A (en) | 1996-05-15 | 1998-12-08 | Intel Corporation | Programmable digital filter for stable interval detection |
US5754884A (en) | 1996-05-20 | 1998-05-19 | Advanced Micro Devices | Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA controller |
US5852743A (en) | 1996-07-12 | 1998-12-22 | Twinhead International Corp. | Method and apparatus for connecting a plug-and-play peripheral device to a computer |
US5797038A (en) | 1996-09-09 | 1998-08-18 | Ford Motor Company | Method and system for serially based host/peripheral communication |
US5905913A (en) | 1997-04-24 | 1999-05-18 | International Business Machines Corporation | System for collecting a specified number of peripheral interrupts and transferring the interrupts as a group to the processor |
US6189049B1 (en) * | 1998-08-10 | 2001-02-13 | Micron Technology | Method for operating processor with internal register for peripheral status |
US6219720B1 (en) * | 1998-08-10 | 2001-04-17 | Micron Technology, Inc. | Core logic unit with internal register for peripheral status |
-
1998
- 1998-08-10 US US09/131,447 patent/US6219720B1/en not_active Expired - Lifetime
-
2001
- 2001-01-17 US US09/764,631 patent/US6393507B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6678838B1 (en) * | 1999-08-23 | 2004-01-13 | Advanced Micro Devices, Inc. | Method to track master contribution information in a write buffer |
US20070198757A1 (en) * | 2006-02-07 | 2007-08-23 | Samsung Electronics Co., Ltd. | Data processing system with hardware polling processor |
US20150109026A1 (en) * | 2013-10-22 | 2015-04-23 | Hon Hai Precision Industry Co., Ltd. | Electronic device assembly |
US9667254B2 (en) * | 2013-10-22 | 2017-05-30 | Hon Hai Precision Industry Co., Ltd. | Electronic device assembly |
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US6393507B2 (en) | 2002-05-21 |
US6219720B1 (en) | 2001-04-17 |
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