JPS6062760A - Synchronizing device in start-stop system data transmission - Google Patents

Abstract

PURPOSE:To receive accurately a data even if noise exists or an error exists in transmission speed by measuring a phase difference between a sampling signal outputted from a constant period forming circuit and a synchronizing signal, and correcting the said circuit. CONSTITUTION:The synchronizing signal output circuit 4 outputs a synchronizing signal 5 in synchronizing with a clock from a transmission circuit 1 and a transmission data 3. A decision circuit 11 measures a phase difference between the said output and the sampling signal outputted from the constant period forming circuit 10. A correction control circuit 13 corrects the constant period forming circuit 10 based on the result of the decision circuit 11. Moreover, a sampling signal 7 from the forming circuit 10 is outputted to a sampling circuit 8, the transmission data 3 is sampled and a reception data 9 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization device for start-stop data transmission.

Generally, in start-stop data transmission, as shown in Figure 1 (a), the transmitting side adds a start pulse P1 to the beginning of the code current and sends it, and then sends data D1 to D8 using the code current. A stop pulse P2 is added at the end and sent.

In conventional start-stop data transmission, the receiving side receives data in synchronization with transmission, so it samples the received data at regular intervals, detects a start pulse when the receiving input level becomes low, and starts. If the time width of each bit of the pulse and data is, for example, 16 clock signals, the start pulse is counted from the time when 8 clock signals are counted from the time when the start pulse is detected, as shown in Figure 1 (b). As shown in the same figure (c), set the center point as the data sampling timing,
Below, sampling is performed at regular intervals. That is, conventionally, data is sampled at constant timing from the center point using only the start pulse transmitted prior to data transmission as a reference.

According to the above-mentioned conventional device, as shown in Fig. 2, when noise N is superimposed on the start pulse P1, the center point of the start pulse shifts, so the sampling also shifts, and the data is sampled at a portion containing distortion. Doing so may result in a situation where data cannot be received accurately.

In addition, in conventional devices, separate clocks are used on the transmitting side and the receiving side, but since there is some error in both clocks, when transmitting data consisting of many bits, the transmission speed Due to the accumulation of errors, the final side data may not be received accurately.

In view of the above points, the present invention provides a synchronization device that can accurately receive data without being affected by noise, and can also accurately receive data with a multi-bit configuration even if there is an error in the transmission speed. The purpose is to

Next, an embodiment of the present invention will be described based on the drawings from FIG. 3 onwards.

As shown in FIG. 3, a synchronization device that achieves the above object of the present invention generally includes an oscillation circuit 1 that generates a clock 2 that serves as a time reference for the operation of this device, and a transmission data 3.
゛When changing from OII to 11111 or from "1" to "0", a synchronization signal output circuit 4 outputs a synchronization signal 5 in synchronization with the clock, and the clock 2 constantly operates to create a fixed cycle. Then, using the periodic signal as a reference timing, it is determined whether the fixed period at the time of inputting the synchronization signal is advanced, delayed, or synchronized, and the fixed period is corrected or corrected based on the judgment result. a sampling signal output circuit 6 that outputs a sampling signal 7 for sampling the transmission data 3 without sampling the transmission data 3, and a sampling signal output circuit 6 that samples the transmission data 3 and outputs the reception data 9 each time the sampling signal is input It consists of a sampling circuit 8 for outputting.

The oscillation circuit 1 oscillates at a frequency that is an integral multiple of the transmission speed and outputs a clock 2. In the illustrated embodiment,
It oscillates at a frequency 16 times the transmission speed, and 16 clocks are output for one mark or space of the transmission data 3.

The synchronization signal output circuit 4 detects the change in the transmission data 3 when the clock 2 is input and outputs the synchronization signal 5. When the transmission data 3 changes from 0'' to 1'', the synchronization signal 5 is output. In order to output a When outputting the signal 5, as shown in FIG. 5a, two flips 70 are used.
Tsubu FF3. It can be constructed from FFa and an AND circuit AN D2. The operation of the synchronizing signal output circuit of FIGS. 4a and 5a is as shown in the time charts of FIGS. 4b and 5b.

The sampling signal output circuit 6, as shown in FIG.
Fixed cycle creation that inputs the clock 2 of the oscillation circuit 1, creates a predetermined cycle corresponding to the time width of one mark or space of the transmission data, and outputs a sampling signal at the midpoint of each cycle. having a circuit 10;
A determination circuit that determines, from the phase of the fixed cycle generation circuit 10 at the time when the synchronization signal 5 is inputted from the synchronization signal output circuit 4, whether the cycle generated by the circuit is in advance, behind, or in synchronization with respect to data transmission. 11 and synchronization signal 5
a correction value generation circuit 12 that measures the phase difference if there is a phase difference in the fixed period generation circuit at the time when the periodicity generation circuit is inputted, and generates a correction value of 1/N of the advance or delay; and a determination circuit. Immediately based on the output signal 11a when 11 is determined to be advanced, or output signal 11 when determined to be delayed.
The correction control circuit 13 presets the correction value of the correction value generation circuit in the fixed cycle generation circuit 10 between the end of a cycle and the start of the next cycle based on the correction value b.

FIG. 6 shows a specific example of circuits 10 to 13 having each function of the sampling signal output circuit 6, in which the time width of one mark of the transmission data is equal to the clock 1 of the oscillation circuit 1.
Considering that it corresponds to 6 bits, the fixed period generation circuit 10 is configured with a 4-bit hexadecimal counter 10Δ, and the output terminal QD of the most significant digit among the output terminals corresponding to the 4 bits of the counter 10Δ is taken as the sampling signal 7.

Further, by connecting the output terminal QD to the inhibit input terminal of the AND gate ΔND3 and applying the synchronization signal 5 to the drive input terminal of the AND gate,
is configured. As a result, while the count value is from "0" to "7" in decimal, the output of the output terminal QD is 0.
”, and it is judged as advance, so the AND gate AND
3 is opened and the synchronization signal 5 is passed. In addition, since the output of the output terminal QD is "1" when the count value is from "8" to "15", it is determined that there is a delay, and the AND gate A
ND3 is closed. Further, the correction value creation circuit 12 receives the output from each output terminal QA-QD corresponding to 4 bits of the counter, that is, the count value, every time the synchronization signal 5 is input, and converts it into a predetermined correction value. is configured. The output terminal of the encoder is connected to the input terminals (A to D) of the counter 10A.

In this embodiment, the counter content "0" is changed to "
15'', the encoder 12A converts them into predetermined correction values as follows and outputs them.

Count value Correction value O 1,21 3,42 5,63 7,84 9,103 11,122 13,141 150 Furthermore, the output of the AND gate A N D 3 forming a part of the judgment circuit and the Carry signal 14 from another output terminal OA of counter 9-10A
The correction control circuit 13 is constructed by using the inputs of the OR gate OR and applying the output of the OR gate to the preset input terminal of the counter 10A.

Among the above configurations, the operation of the correction control circuit 13 will be mainly explained. When the judgment circuit 11 outputs the advance judgment signal 11a, that is, when the output of the output terminal QD of the counter IOA is "0", , every time the synchronization signal 5 is input,
The synchronization signal passes through the AND gate A N D 3 and the OR gate OR of the correction control circuit and provides a preset input to the preset input terminal of the counter. The corrected value (0X deviation of 1 to 4 for the count value 1 to A) is immediately preset to the counter IOA.

On the other hand, when the judgment circuit 11 outputs the delay judgment signal 11b, that is, when the output of the output terminal QD of the counter 110-OA is 1'°, the AND gate AND3 of the judgment circuit closes and the synchronization signal 5 is not given to the modification control circuit 13. Therefore, the counter is not preset and continues to be incremented by clock 2. Then, when the count value becomes rOJ from "15", the carry signal 1
4 is given to the OR gate OR of the control circuit 13, and the preset input is applied from the control circuit to the counter.
A correction value corresponding to the count value at the time when the previous synchronization signal 5 was input is sent from the encoder 12A to the counter IOA.
is preset to .

Next, the operation of the apparatus having the above configuration will be explained based on time charts, in cases where there is no synchronization shift between the transmission data and the sampling signal 7 outputted from the sampling signal output circuit 6, and when there is a synchronization shift.

In addition, when operating this device, as an initial operation,
Prior to formal data transmission, dummy data transmission is performed several times at a predetermined period until there is no synchronization difference between the transmitted data and the sampling signal, and then formal data transmission is started in a normal state with no synchronization difference. It is something.

FIG. 7 shows a case where there is no synchronization shift between transmission data 3 and sampling @7. Transmission data is from O'' to 1
'', the synchronization signal 5 is output. In this embodiment, the synchronization signal 5 is generated when the count value of the counter 10A is "0", so there is no synchronization deviation and no synchronization correction is performed. .

FIG. 8 shows an example where the phase of the sampling signal 7 is advanced and the phase is to be corrected.

At the change point a of the transmission data, when the synchronization signal 5 is generated, the count value of the counter 1OA is "3", and it is determined that the process is progressing. The synchronizing signal 5 sets "2" in the encoder 12A. At this time, the synchronization signal 5 is passed through the AND gate AND3 and the OR gate OR to the counter 1.
To set the 0A preset input to L'', counter I
OA is preset to "2".

Therefore, the advance is corrected from "3 clocks" to "1 clock."

At the next change point of the transmitted data, the next synchronization signal 5
Since the count value of the counter 10A is "1" when this occurs, further correction is made. That is, "1" is set in the encoder 12A, and "1" is preset in the counter 10A. Therefore, the advance is corrected and a synchronized state is achieved.

FIG. 9 shows an example in which the phase of the sampling signal 7 is delayed and the delay is corrected.

At the change point a of the transmission data, when the synchronization signal 5 is generated, the count value of the counter IOA is "12", and it is determined that there is a delay. The synchronizing signal 5 sets "2" in the encoder 12A. However, the count value is "12"
Therefore, the AND gate AND3 is not opened, and no synchronization correction is performed at this point. When the count value reaches "15", the OA ratio output 13- of the counter IOA becomes "H", and the output of the counter IOA through the OR gate OR.
Set the preset input to LI+. The counter should normally be rOJ after "15", but at this point it is "2".
is preset.

Therefore, the delay is modified from "4 clocks" to "12 clocks."

At the next change point, when the next synchronizing signal 5 is generated, the count value of the counter 10A is "14", so further correction is made. That is, "1" is set in the encoder 12A, and "1" is preset in the counter 10A by the next OA ratio output IH11. Therefore, the delay is gradually corrected and a synchronized state is achieved.

As described above, according to the synchronization device of the present invention, 1) Even if the transmitted data becomes out of synchronization due to noise etc., it is gradually corrected, so no fatal synchronization will occur, and 2) "O" of the transmitted data ” to 1” or “1” to “0”
14- Accurate reception is possible even when transmitting long and large bit data because synchronization is maintained every time there is a change in ゛'. 3) There is some error in the transmission speed between sending and receiving. Also, since there is no accumulation of errors, high reliability can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a time chart illustrating the synchronization principle of the conventional device, and FIG. 2 is a time chart illustrating the drawbacks of the conventional device. FIG. 3 is a block diagram showing the basic configuration of the present invention, FIG. 4a is a block diagram showing an example of a synchronizing signal output circuit, FIG. 4b is a time chart of the circuit, and FIG. 5a is a diagram of the synchronizing signal output circuit. A block diagram showing another example, FIG. 5b, is a time chart of the same circuit. FIG. 6 is a block diagram showing an example of a sampling signal output circuit. Figure 7 and the following drawings are time charts that explain the time relationship between the transmission data and the fixed period and the operation of each circuit. The figure shows a case where the fixed cycle is ahead compared to the transmitted data and its correction, and FIG. 9 shows a case where the fixed cycle is delayed compared to the transmitted data and its correction. Patent applicant Nippon Signal Co., Ltd.

Claims (1)

[Claims] A synchronization signal circuit that outputs a synchronization signal every time data changes to 1'' or '0'', and samples data at regular intervals based on the generation timing of the synchronization signal. The system includes a sampling signal output circuit that outputs a signal for data processing, and a sampling circuit that samples the data using the sampling signal, extracts a synchronization point from the transmitted data, and samples and receives data using the synchronization point as a reference. In the synchronization device for start-stop data transmission, the sampling signal comparison circuit is configured to: (a) input a clock to create a predetermined period corresponding to the time width of one mark or space of the transmission data; (b) From the phase of the fixed period generating circuit at the time when the synchronization signal from the synchronization signal output circuit is input, the period created by the circuit is determined. (c) a determination circuit that determines whether the data transmission is in advance, delay, or synchronization; 1
/N; and (d) a correction value creation circuit that creates a correction value of the correction value creation circuit immediately or a delay of the judgment circuit based on an output signal indicating that the judgment circuit has determined that the correction value has progressed. a correction control circuit that presets the correction value of the correction value generation circuit in the fixed cycle generation circuit between the end point of a cycle of the fixed cycle generation circuit and the start point of the next cycle based on an output signal indicating that it has been determined that A synchronization device comprising: