JPS606227U - semiconductor integrated circuit element - Google Patents

semiconductor integrated circuit element

Info

Publication number
JPS606227U
JPS606227U JP9856383U JP9856383U JPS606227U JP S606227 U JPS606227 U JP S606227U JP 9856383 U JP9856383 U JP 9856383U JP 9856383 U JP9856383 U JP 9856383U JP S606227 U JPS606227 U JP S606227U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit element
semiconductor integrated
semiconductor wafer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9856383U
Other languages
Japanese (ja)
Inventor
金巻 政幸
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP9856383U priority Critical patent/JPS606227U/en
Publication of JPS606227U publication Critical patent/JPS606227U/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のIC素子を有する半導体ウェーハの平面
図、第2図は本考案によるIC素子の実施例を示す半導
体ウェーハの部分拡大図を含む平面図、第3図は第2図
のIC素子の部分概略断面図、第4図は第2図のIC素
子におけるトランジスタのhFEとピンチ抵抗のV−I
関係図である。 4・・・・・・半導体ウェーハ、5・・・・・・半導体
集積回路素子(IC素子)、6’、6’・・・・・・ピ
ンチ抵抗値測定用パッド、R・・・・・・ピンチ抵抗。
FIG. 1 is a plan view of a semiconductor wafer having a conventional IC device, FIG. 2 is a plan view including a partially enlarged view of the semiconductor wafer showing an embodiment of an IC device according to the present invention, and FIG. 3 is a plan view of a semiconductor wafer having a conventional IC device. A partial schematic sectional view of the device, FIG. 4 shows the hFE of the transistor and the V-I of the pinch resistance in the IC device of FIG.
It is a relationship diagram. 4... Semiconductor wafer, 5... Semiconductor integrated circuit element (IC element), 6', 6'... Pad for pinch resistance value measurement, R...・Pinch resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体ウェーハに複数個形成された半導体集積回路素子
であって、その表面に内部に形成したピンチ抵抗の抵抗
値を外部より測定できるパッドを形成したことを特徴と
する半導体集積回路素子。
1. A semiconductor integrated circuit element formed in plurality on a semiconductor wafer, characterized in that a pad is formed on the surface of the semiconductor integrated circuit element so that the resistance value of a pinch resistor formed inside can be measured from the outside.
JP9856383U 1983-06-24 1983-06-24 semiconductor integrated circuit element Pending JPS606227U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9856383U JPS606227U (en) 1983-06-24 1983-06-24 semiconductor integrated circuit element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9856383U JPS606227U (en) 1983-06-24 1983-06-24 semiconductor integrated circuit element

Publications (1)

Publication Number Publication Date
JPS606227U true JPS606227U (en) 1985-01-17

Family

ID=30233952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9856383U Pending JPS606227U (en) 1983-06-24 1983-06-24 semiconductor integrated circuit element

Country Status (1)

Country Link
JP (1) JPS606227U (en)

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