JPS5844852U - semiconductor wafer - Google Patents
semiconductor waferInfo
- Publication number
- JPS5844852U JPS5844852U JP13971081U JP13971081U JPS5844852U JP S5844852 U JPS5844852 U JP S5844852U JP 13971081 U JP13971081 U JP 13971081U JP 13971081 U JP13971081 U JP 13971081U JP S5844852 U JPS5844852 U JP S5844852U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- grooves
- chip
- view
- divided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図および第２図は従来の半導体ウェハの底面斜視図
およびその他の一部断面図、第３図はチップの接着態様
を示す斜視図、第４図は本考案Ｃ−実施例を示す半導体
ウェハの一部切欠底面斜祁図、第５図は第４図に示す半
導体ウェハを分割し： たときの１つのチップの底面
斜視図、第６図は従； 来のチップを接着したときの
態様を示す断面図、し 第７図は本考案にかかるチッ
プを接着したときの態様を示す断面図セある。
１０・・・・・・半導体ウェハの裏面、１１・・・・・
・格子状； のパターン溝、１１Ｘｉ、 １１Ｘ２
、 ”・、 １１）’ｔ。
・ １ｌｙ２．・・・・・・溝部、１２・・曲チップ
、１３・・開田〉 字状の溝部。1 and 2 are bottom perspective views and other partial sectional views of conventional semiconductor wafers, FIG. 3 is a perspective view showing how chips are bonded, and FIG. 4 is a semiconductor device showing an embodiment of the present invention C. FIG. 5 is a partially cutaway bottom perspective view of a wafer; FIG. 5 is a bottom perspective view of one chip when the semiconductor wafer shown in FIG. 4 is divided; FIG. 6 is a bottom perspective view of a conventional chip; FIG. 7 is a sectional view showing an embodiment of the present invention when the chip is bonded. 10... Back side of semiconductor wafer, 11...
・Lattice pattern; pattern groove, 11Xi, 11X2
, ``・, 11)'t. ・ 1ly2.・・・Groove, 12...Curved tip, 13...Kaida> letter-shaped groove.
Claims (1)
に分割される際に各々のチップに溝部カニ設けられるよ
うに所定パターンを有する溝を形成したことを特徴とす
る半導体ウェハ。1. A semiconductor wafer, characterized in that grooves having a predetermined pattern are formed on the back surface of the semiconductor wafer so that grooves are provided in each chip when the semiconductor wafer is divided into individual chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13971081U JPS5844852U (en) | 1981-09-19 | 1981-09-19 | semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13971081U JPS5844852U (en) | 1981-09-19 | 1981-09-19 | semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5844852U true JPS5844852U (en) | 1983-03-25 |
Family
ID=29932891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13971081U Pending JPS5844852U (en) | 1981-09-19 | 1981-09-19 | semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5844852U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5263674A (en) * | 1975-11-20 | 1977-05-26 | Matsushita Electronics Corp | Semiconductor device |
-
1981
- 1981-09-19 JP JP13971081U patent/JPS5844852U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5263674A (en) * | 1975-11-20 | 1977-05-26 | Matsushita Electronics Corp | Semiconductor device |
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