JPS6059798A - Ceramic circuit board - Google Patents

Ceramic circuit board

Info

Publication number
JPS6059798A
JPS6059798A JP16884783A JP16884783A JPS6059798A JP S6059798 A JPS6059798 A JP S6059798A JP 16884783 A JP16884783 A JP 16884783A JP 16884783 A JP16884783 A JP 16884783A JP S6059798 A JPS6059798 A JP S6059798A
Authority
JP
Japan
Prior art keywords
layer
hole
ceramic
circuit
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16884783A
Other languages
Japanese (ja)
Inventor
三森 誠司
堀部 芳幸
秀次 桑島
上山 守
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP16884783A priority Critical patent/JPS6059798A/en
Publication of JPS6059798A publication Critical patent/JPS6059798A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 不発明は電気、電子等の回路(以下回路という)を形成
するためのセラミック配線板の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in ceramic wiring boards for forming electrical, electronic, etc. circuits (hereinafter referred to as circuits).

促米5回路を形成するkめのセラミック基板としては、
軸度90%以上のりε結したA403左、奴VC与体配
腺層ン設け、そQ’z多層化し回路ン形成テゐ上2ミ配
線板勝板およびセラミックグリーンシート(以下グリー
ンシートどい′:))vc41本目に線′8!=施しそ
して絶縁j曽と晦1本rツ【′、j吻J曽と1父互に形
成した佐〜括焼結して回路ケ形成′1−ゐセラミック基
板かめる。
As the kth ceramic substrate that forms the 5th circuit,
On the left side of A403 with axiality of 90% or more, a VC donor wiring layer is provided, and a Q'z multi-layered circuit is formed. :)) VC41st line '8! = Apply and insulate the insulators and 1 piece together and sinter the circuit board.

A403基板は一般にd um I/、1A4(J+ 
VJ禾τヨニ成分とし、こ扛に焼結助MllとしてSi
Ox、CaO+lvigo等葡占己会し1こ組成物10
0里重hμに7寸し5〜20亘童都の1弓゛+χ乏9勿
(結814す、 口■当グをりζ’j’ ) ’a:除
カロ、混合したグリーンシート4人気中、1600℃付
近で焼結して製造さnる。そして回路は連体、絶縁、抵
抗、肪電体号の谷ペースI−τ焼結し’rc A110
3基似に、例えはスクリーン印刷し、つい″C′焼J収
すゐことによって形處鴎れな。
A403 board is generally d um I/, 1A4(J+
VJ is used as a component, and Si is added as a sintering aid.
Ox, CaO + lvigo, etc., composition 10
7 inches to 0 ri weight hμ and 5 to 20 doto's 1 bow ゛ + χ deficiency 9 course (result 814, mouth ■ hit guori ζ'j') 'a: Excluding Calo, mixed green sheet 4 popularity It is manufactured by sintering at around 1600°C. And the circuit is interconnected, insulated, resistive, fat electric body number trough pace I-τ sintered 'rc A110
For example, if you screen print the three pieces, and then print them on a C'print, you can create a shape.

さらに詳しく説明すると与体にはA u + P t+
 A g rPd等の賃金輌倣粉禾、杷嫌には9〜15
の比誘電率を持つカラス粉末、肪電坏vcta数10〜
数100の比誘電率を持つカラス紛Δ〈、」へJ九V(
はRu 2 Orカーボン寺の粉末τ使用し、そしてこ
扛らの粉末と凋−槻吻と盆混合して荀7こベーストを焼
結したAll、03基敬にスクリーン印刷Wで1回り1
=1」刷1ツバ例えば婢無配鹸鳩、絶縁層、抵抗体層尋
7形Jg丁ゐ旬に+000℃9、下り湿度で鵠、成τ竹
ない。それ會例えにカシス貿り結合片1」−C以yii
 L i この工程を畝回(−り返して回路が形j取込
fLゐ〇 一方一括b1L結法V(よゐセラミック自己!腺4メは
AjL03粉末ン90.mxlif都以上、S ioz
 、 CaO,MgO査τ70MLIii部以下そIl
、に虐h工の翁依9勿ン言むグリーンシートにW、Mo
、Mn青の冒1触点金城粉刀・ら成る晦捧ペーストケス
クリーン印刷等で4j、坏配想島ン設け、グリーンシー
ト又はグIJ −ンシートと同一組成の絶縁ペースト雀
得無配腺層と交互に形成することで尋捧配腺層を多層化
し、そn’z1.600°C付近で弱還元性雰囲気中で
一括胱軸して回路が形J戎ざ才tゐ。
To explain in more detail, the donor has A u + P t+
9 to 15 for wage imitation powder and loquats such as A g rPd.
Karasu powder with a dielectric constant of 10~
Karasu powder Δ〈, with a dielectric constant of several 100 to J9V (
I used Ru2Or carbon powder τ, and mixed these powders with Rin-Tsukichi and Bon and sintered the Xun7 base.
= 1'' printing 1 brim For example, a pigeon with no pigeons, an insulating layer, a resistor layer, a type 7 Jg, at +000 degrees Celsius 9, and humidity, there are no birds, and there are no mature bamboos. For example, a blackcurrant trade binding piece 1”-C yii
L i Repeat this process until the circuit is shaped like J Intake fL ゐ〇 Meanwhile, bulk b1L binding method V (Yo Ceramic Self! Gland 4 is AjL03 Powder N90.mxlife and above, Sioz
, CaO, MgO investigation τ70MLIii section below Il
, W, Mo on the green sheet where the old man of the brutality 9 says,
, Mn Blue's first contact point is Kinjo Powder Sword, which consists of a 4J, a 4J, a green sheet, and an insulating paste with the same composition as the green sheet or a green sheet. By forming these layers alternately, the glandular layers are multi-layered, and the circuit is formed into a shape of J in the shape of a circuit in a weakly reducing atmosphere at around 1.600°C.

しかしこnら従来、のセラミック自1′、腺板は一度最
外層表面の回路を設戻してしiうと後で回路の設計哀史
が生じるとそのセラミック配線数は使用不町寵となり1
窯回路別に叙位のセラミック自ES腺致を装作しなけ扛
はならないので量産性に欠け、コストアノグリ原因とな
っていたO不発明ぽムタタを層表面の回路の設馴吸史に
容易に対応でき、童派憔に複へ力・つ安1曲なセラミッ
ク区腺板盆提供丁ゐこと如目的とするものでりる0 不発明は1層又はそ扛以上の導体配線層忙内蔵し、この
内蔵した4無配腺層に〕<イアホール又σスルーホール
盆弁して配詠板の最外層表間の片面又は両凹のほぼ全面
に形成し1こ表聞尋捧層に接続してなるセラミック1腺
叡に関する。
However, in these conventional ceramics, once the circuit on the surface of the outermost layer is installed on the gland plate, the number of ceramic wiring becomes unusable when the circuit design is changed later.
Since it is necessary to equip ceramic self-sustaining glands for each kiln circuit, mass production is lacking, and the inventiveness that was the cause of cost anomalies can be easily dealt with by the construction history of the circuit on the surface of the layer. The purpose of this invention is to provide a ceramic plate tray with multi-layered power and stability. Built-in 4 non-gable layers] <Ear holes or σ through holes are formed on almost the entire surface of the outermost layer of the distribution plate on one or both sides of the surface, and one is connected to the surface layer. 1 Concerning glands.

不発明は上記のように最IA層次曲り片1川又に1両面
のほぼ全面に表佃専体層を形成するようにしてエソナン
グ等の手段により不安な挿分娑剛V取9回路r+f慧に
形JfAできるようにしたもの′Cある。
The invention is to form a surface exclusive layer on almost the entire surface of one side of the bent piece of the most IA layer as described above, and to create an unstable insertion layer with 9 circuits r+f by means such as etsonization. There is a 'C' that allows the form JfA.

なお本発明において与体蘭1、線層r形1&丁ゐのに用
い/)導体ペーストとしては、W、 No 、 Mn 
IAu、Ag、Pd、Cu青が用いら扛、こ扛らはその
焼結条件、製造プロセスIcよ+2用いるものとし。
In the present invention, the conductor paste used for the conductive layer 1 and the wire layer r-type 1 & 2) includes W, No, Mn.
IAu, Ag, Pd, and Cu blue are used, and the sintering conditions and manufacturing process Ic are +2.

その膜厚については特に制限にない。There is no particular restriction on the film thickness.

最夕を層表面V(形4■する表聞碍坏層の材料としてi
’JJ二♂己に示す21!71本ペーストτ塗イliL
、そ7シ2x焼@付りて形成してもよく、金鵬又は会金
娑真蹟蒸石して形成してもよく制限はない。
As the material of the layer surface V (form 4),
'JJ2♂ Show to yourself 21! 71 paste τ coating IliL
, 7 and 2 x fired, or may be formed by steaming metal or gold metal, and there is no restriction.

不発明においてバイアホール又はスルーホールの一部は
少な(とも2点以上基板表間に露出させゐことが好菫し
い。バイアポール又はスルーホールは一足ピノチ幅で刀
・つ1層俵するバイアホール叉はスルーホールとげ平行
、in:g+な位置に形成′Tることか好丘しい。こc
/)ように丁γしは取外ノ「・次曲の下部に位置1゛ゐ
バイアホール又はスルーホールの位If l)’ ll
l5 誌し易い。なおバイアホール又はスルホールの径
、形状および叡については11′:fに制限はない。も
し回wJ役割上不要でめ扛ば杷碌物で俵彼することによ
り容易に絶縁子ゐこと力ST@る。
In the invention, it is preferable that a part of the via hole or through hole is small (it is preferable to expose two or more points between the surfaces of the board). It is good that the through hole is formed parallel to the thorns, in:g+ position.
/) As shown in Figure 1, remove the cylindrical hole.
l5 Easy to read. Note that there is no limit to the diameter, shape, and thickness of the via hole or through hole (11':f). If it is unnecessary for the role of WJ, it is easy to insulate it by using a loquat with a loquat.

なお本発明になめセラミック門自塚板は必要に応じセラ
ミック度#椴の懺裏τ其通1−る部品穴笛形成してもよ
い。
In addition, the tanned ceramic gate plate of the present invention may be formed into a hole-shaped part with a ceramic degree # 椴の溺其 1- (1) as required.

以下不ヴ色明の実施例を図曲:ど引J1−j して祝明
する0 実施例1 第1図に本発明の一実施例になるセラミック配線数の製
作作菓状態を丁子一部しr凹ル[仇図である。1はグリ
ーンシートで1.1bJ−形状に切II7[したもの會
6枚葉備し、そ扛ぞnVcスルーホール2t−足ピンチ
嘱で形成し、そ(1)俊スルーホール2にW導体ペース
ト57光横する。そしてこのうちの2枚のグリーンシー
ト1の表面vc〃イ出しているスルーホール2を一つ匝
キに囲むように絶線部6r形j反しなからW寺犀ペース
トヶ印届1」シて導体自己最41曽6を形属し、次にこ
才を孕垂tUて前記スルーホール2と4無配勝ノ置6と
t父亙に接続−J−6ようにする。詳しくにグリl 7
.−ト1に形成した導体配勝層6がスルーホール2會介
してスルーホール2に発情したW導体ペースト5と接続
子ゐ部分と接続しない部分とが交互になるように3−6
0このようVCして2位のグリーンシート1tMLねた
恢その上部にW峠体ペス)5層7元填したのみのグリー
ンシート1ン厘ね79(玉石し、ついで弱還元性雰囲気
中で4600′CのM′1j及で跣I必し、その飲衣1
川の両uflのほぼ全[川にNi τ共空盛虐して六回
4q1本j曽4τ形成しこnと内戚した与体目C勝層6
とτj安角死し7てセラミ ) り llj己TI多製
11M ’、r: ’+委tイコ。
The following is an illustration of an embodiment of the present invention: Dobiki J1-j 0 Embodiment 1 Figure 1 shows the state of production of ceramic wiring according to an embodiment of the present invention. This is the opposite figure. 1 is a green sheet cut into a 1.1bJ-shape with 6 sheets of II7, then formed by pinching the nVc through hole 2t, and (1) W conductor paste in the through hole 2. 57 light horizontal. Then, on the surface of two of these green sheets 1, insert a conductor so as to surround one of the protruding through holes 2. Form the own maximum 41 so 6, and then connect this through hole 2 and 4 to the 6 and t father by placing the child's hand. Grill details 7
.. - The conductor distribution layer 6 formed on the plate 1 is inserted into the through hole 2 through the through hole 2 so that the W conductor paste 5 and the connecting portion and the unconnected portion are alternately 3-6.
0 After VC, the second place green sheet was 1tML, and on top of it was a W pass) 1 ton of green sheet with only 5 layers and 7 yuan filled. 'C's M'1j must be on the legs, and the drinking clothes 1
Almost all of the river's ufl [Ni τ together with the sky and attacked six times 4q 1 book j so 4τ formed n and the body order C victory layer 6
And τj Ankaku dead 7 and Cerami) ri llj self TI multi-made 11M', r: '+Committ Iko.

しり族1シリ2 第2図は不発明の他の一笑施しリになるセラミックr忙
腺狐の袈作作栗状悪τ示す一部〜「囲斜仇図でめゐ。こ
の砺谷に、母材となる焼結したA/ll、Os築載板7
上■に絶縁郡(図示せず)となぁ’8i(分で渋してA
g−Pd4体ペーストン印Aiすし、次にこn述空気中
″T:900℃の温度で尻)必して4す141じ触着8
に形成する。次にガラス粉床とビヒクルとて混合したも
の述−にピッチ幅で尋無配煉J曽8の上向に印刷法碇よ
りスルーホール2娑設けなから絶縁)會9を形ノ成子ゐ
0その後スルーホール2にAg−Pd尋与体−スト10
笛光項し、削記と同様空気中で900℃の温度で腕戟し
、その俊スルーホール2を設けた杷脈鳩9の上向の全面
に実施例1と同様にi4i’<真空蒸着して表囲縛1不
湘4t7彪我しこnと円J臥しR碍1小配線層8と弦接
続したセラミック配性・奴τ1・Jろ〇実施例6 第6図は不発明の1巳の一笑泥νりになめセラミック配
線板の破砕断面斜視図裟示し、実施例2と同様に母材と
なる焼結したA403端徹7の上面にAg−Pd纒体ペ
ースト〒印刷し−C尋坏配勝層11 、11”7設は空
気中1900°Cの?11ifkで焼成する。次にカラ
ス粉ンjことビヒクルとン混合したものt−尾ピンチ幅
で導体配線層11.44’の上面に印刷法によ!l12
列ずつスルーホール2盆設けると共に絶縁層9盆形戟丁
ゐ0なおスルーホール2は一候1−ゐスルーホール2と
は平イ1、直角な位置に形成する。そり阪やルーホール
2にAg−Pdn体ペースト10ン光項し、1lll記
と同様空気中で900℃の温度で焼成し、その俊得ら7
’Lるセラミック配線板の長妊万同の一方の端に位置す
るスルーホール2′の2点τ残し、以下実施例1とlo
1様[Ni ’;c真空蒸眉し、2点のスルーホールの
端面を表面VCC出出た六回尋俸層4忙形戟しこわと内
戚し7ζ尋坏自白Id層11と荀候わ′cしたセラミッ
ク配疵根12梵倚心。
Shirizoku 1 Series 2 Figure 2 shows a part of the ceramic r, which is a mockery of other uninvented works. Sintered A/ll, Os mounting plate 7 as base material
Insulation group (not shown) on the top
g-Pd 4 body paston mark Ai sushi, then the above mentioned air "T: bottom at a temperature of 900℃) must be 4th 141st touch 8
to form. Next, after mixing the glass powder bed and the vehicle, two through-holes were provided above the printing method anchor with a pitch width of 2 through holes (insulated) to form a plate 9. Ag-Pd donor-strike 10 in through hole 2
As in Example 1, i4i'< vacuum evaporation was performed on the entire surface of the locomotive pigeon 9 with the through-hole 2 in the upper direction. Ceramic arrangement with string connection with surface bound 1 Fu Xiang 4 t 7 Biwa Shiko n and circle J lying R 碍 1 Small wiring layer 8 and string connection τ 1 J Ro〇 Example 6 Figure 6 is the uninvented 1 A perspective view of a fractured cross section of a ceramic wiring board is shown in the same way as in Example 2, and Ag-Pd paste is printed on the top surface of the sintered A403 base material 7. The layer 11, 11''7 is fired in air at 1900°C at -11ifk.Next, the conductor wiring layer 11.44' is mixed with caras powder, also known as vehicle, and the width of the T-tail is 11.44'. By printing method on the top surface of!l12
Two trays of through-holes are provided in each row, and the insulating layer 9 is shaped like a tray.The through-holes 2 are formed at positions that are flat and perpendicular to the through-holes 2. The Ag-Pdn body paste was exposed to 10 nm of light on Sorisaka and Ruhole 2, and fired at a temperature of 900°C in air as described in Section 1.
Two points τ of the through hole 2' located at one end of the ceramic wiring board are left;
Mr. 1 [Ni';c vacuum vaporized, the end face of the two through-holes was exposed to the surface VCC, and the six-fold layer 4 had a rough shape and was internally connected to the 7ζ-layer confession Id layer 11 and the layer 11. Ceramic flaw root 12 Brahma heart.

失施vIJ4 第4凶は本発明の他の一夾/A!i例になるセラミック
配線板の破砕1Pir血斜祝凶匍示し、倚らγLるセラ
ミック配アΔ板の長さ方向の一方の端の内面に位1ピ丁
心スルーホール2′の4点(製表谷2点)髪表四に露出
した以外LrJ、笑流レリ1しioJじ工程匍肚て表1
nJ々メ体層と内戚した47休配勝層5と匍」掟枕しR
セラミック配勝似12髪1びる○不発明のセラミック配
線板に1層又にそ6以上の導体配線層【内蔵し、この内
戚した導体配線J曽荀バイアホール又はスルーホール葡
弁して基板の取外層表面の片面又は両凹のほぼ全面に形
成した衣iII]4体層に接続するようにしたので、最
外層表Ua+に形成する回路はエツチング等の手段によ
!ll製1′[できるので回路の設計変更が生じても回
路π容易に形成することかでさ、し刀島も最外励衣面に
形成するIg路別に献独のセラミック自己腺叡忙製1乍
しな(てもよいので蓋肢性に優れ、安f[iI]にでき
め。
Loss of practice vIJ4 The fourth evil is another example of the present invention/A! For example, if a ceramic wiring board is broken, there are four points (1 pin and 1 center through hole 2') on the inner surface of one end of the ceramic wiring board in the length direction. 2 points) LrJ, Shoryu Leri 1 and ioJ process, except for the exposed hair 4) Table 1
The 47-year-old payout layer 5 and the 47-year-old who are intimately related to the nJ Me body layer.
Ceramic distribution similar to 12 hairs 1 biru○ An uninvented ceramic wiring board with one layer or six or more conductor wiring layers [built-in, and this internal conductor wiring J Zengsun via hole or through hole valve to the substrate. The circuit formed on one or both sides of the surface of the removable layer is connected to the four body layers, so the circuit formed on the outermost layer surface Ua+ can be formed by means such as etching! Since it is possible to easily form the circuit π even if the circuit design is changed, Tojima is also made of a ceramic self-contained ceramic plate dedicated to Germany for the Ig path formed on the outermost surface. It has excellent operculum properties and can be made into a safe f[iI].

1だバイアホール又はスルーホールは一足ピッチ幅でか
つIJ 接−3−るバイアホール又はスルーホールとは
平行、直角な位置に形成1−nは次間導体層の下面に位
置″fゐバイアホール又はスルーホールの位置欠容易に
脱みとることがC′さめ。
1. The via holes or through holes are one foot pitch wide and are parallel to and perpendicular to the IJ contacting via holes or through holes. Or, the position of the through hole is missing and it can be easily removed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一笑1M例になるセラミック配線板の
製作作菜状態匍示す一郡11.lr凹刷祝凶、第2図は
不発明の他の一実施例Vcなめセラミンク配)層板の製
作作業状態欠示す一部断1m斜視図、第6図および第4
図は本発明の他の一実施例になるセラミック配線板の破
砕断面斜視図である。 符号の説明 1、グリーンシート 212′ スルーホール6、導体
配線層 43表表面体層 5、W導体ペースト 6.絶 祿 都 7、 焼結したA40:+基板 8. 導体配線層9・
 絶 鎌 層 10・ Ag−Pd尋俸ペースト11.
11コ 導体配線層゛12 セラミック配緘低第 1 
図 舅 2 (2) 茅3 図 ム 第4図 、手続補正書(自発) 昭和 581− ρ月26日 1事件の表示 2、発明の名称 セラミック配線板 3、補正をする者 事f1との関係 特許出願人 名 称 (445)日立化成工業株式会社4、代 理 
人 5、補正の対象 明細書の発明の詳細な説明の欄 6、補正の内容
Figure 1 shows the state of production of a ceramic wiring board as an example of the present invention. lr Congratulations on intaglio printing, Fig. 2 is another embodiment of the invention (Vc smooth ceramic layer), a partially cutaway 1m perspective view showing the working state of the laminated plate, Figs. 6 and 4
The figure is a perspective view of a fragmented cross section of a ceramic wiring board according to another embodiment of the present invention. Explanation of symbols 1, green sheet 212' through hole 6, conductor wiring layer 43 surface body layer 5, W conductor paste 6. Absolutely 7, Sintered A40: + Substrate 8. Conductor wiring layer 9・
Zetsukama layer 10・Ag-Pd thick paste 11.
11 Conductor wiring layer 12 Ceramic wiring layer 1
Figure 2 (2) Figure 3 Figure 4, Procedural amendment (spontaneous) Showa 581- ρ Month 26 1 case indication 2, name of the invention Ceramic wiring board 3, relationship with the person making the amendment f1 Patent applicant name (445) Hitachi Chemical Co., Ltd. 4, Agent
Person 5, Detailed explanation of the invention in the specification subject to amendment 6, Contents of amendment

Claims (1)

【特許請求の範囲】[Claims] 1.1層又にそn以上の縛体部腺層を内成し、この円厭
した導体配曽層笛バイアホール又はスルーホールンブt
して配線板の最外層表面の□ 片曲又に両…Jのほぼ全
曲に形1戎しlζ表■専坏層に接続してなるセラミック
配線7叡。 2、バイアホール又はスルーホールの端間を少なくとも
2点以上表(rHvc露出した特許請求の範囲第1項記
載のセラミック配線機。
1. A via hole or through hole having one or more layers of binding body layers, and having this rounded conductor distribution layer.
The outermost layer surface of the wiring board □ One side or both sides... Ceramic wiring 7 发 is formed by cutting out almost all of J and connecting it to the special layer. 2. The ceramic wiring machine according to claim 1, in which at least two or more points (rHvc) are exposed between the ends of the via hole or through hole.
JP16884783A 1983-09-13 1983-09-13 Ceramic circuit board Pending JPS6059798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16884783A JPS6059798A (en) 1983-09-13 1983-09-13 Ceramic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16884783A JPS6059798A (en) 1983-09-13 1983-09-13 Ceramic circuit board

Publications (1)

Publication Number Publication Date
JPS6059798A true JPS6059798A (en) 1985-04-06

Family

ID=15875637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16884783A Pending JPS6059798A (en) 1983-09-13 1983-09-13 Ceramic circuit board

Country Status (1)

Country Link
JP (1) JPS6059798A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130888A (en) * 1983-12-19 1985-07-12 日本特殊陶業株式会社 Method of producing multilayer laminated board
JPS62103279U (en) * 1985-12-19 1987-07-01

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100495A (en) * 1980-01-16 1981-08-12 Fujitsu Ltd Method of manufacturing ceramic multilayer printed circuit board
JPS58138095A (en) * 1982-02-10 1983-08-16 日本特殊陶業株式会社 Method of producing ceramic multialyer circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100495A (en) * 1980-01-16 1981-08-12 Fujitsu Ltd Method of manufacturing ceramic multilayer printed circuit board
JPS58138095A (en) * 1982-02-10 1983-08-16 日本特殊陶業株式会社 Method of producing ceramic multialyer circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130888A (en) * 1983-12-19 1985-07-12 日本特殊陶業株式会社 Method of producing multilayer laminated board
JPH0241917B2 (en) * 1983-12-19 1990-09-19
JPS62103279U (en) * 1985-12-19 1987-07-01

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