JPH0410670Y2 - - Google Patents
Info
- Publication number
- JPH0410670Y2 JPH0410670Y2 JP9874688U JP9874688U JPH0410670Y2 JP H0410670 Y2 JPH0410670 Y2 JP H0410670Y2 JP 9874688 U JP9874688 U JP 9874688U JP 9874688 U JP9874688 U JP 9874688U JP H0410670 Y2 JPH0410670 Y2 JP H0410670Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electrode layer
- glass frit
- solderability
- weight percent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011521 glass Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000006116 polymerization reaction Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 29
- 239000003985 ceramic capacitor Substances 0.000 description 12
- 238000005476 soldering Methods 0.000 description 11
- 239000003973 paint Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011230 binding agent Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000007606 doctor blade method Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000004898 kneading Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- -1 etc. Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
Description
産業上の利用分野
本考案はチツプ型電子部品に関し、特にチツプ
型積層セラミツクコンデンサにおける端子電極の
構造に関するものである。
従来の技術
第２図に示すような、一般的な構造をしたチツ
プ型積層セラミツクコンデンサは、次のようにし
て作製される。まず、微細化したセラミツク粉末
と有機バインダを混練した後、ドクターブレード
法によつて、生シートを作製する。次に、このシ
ートを所望の面積に切断し、その表面の片面に、
スクリーン印刷により内部電極を被着・乾燥した
生シートを用意する。次に、内部電極を印刷した
生シートを、電極を印刷しない生シートからなる
保護層で、上下からはさむようにして所望の枚数
を積み重ね、積層体を形成し、熱圧着した後、個
片状態に切断して、生チツプ個片を形成する。こ
の生チツプ個片を焼成して、焼成チツプ１を作製
する。そして、その両端に、銀を主成分として少
量のガラスフリツトを含む導電塗料（導電部材）
を塗布して、端子電極２，２を形成する。最後に
それを焼き付けて、チツプ型積層セラミツクコン
デンサ３を作製する。
考案が解決しようとする課題
ところで、端子電極２の半田付け性と、半田耐
熱性との関係は、第１表の試験結果に示すよう
に、上記導電塗料の種類（ガラスフリツトの含有
量）に依存するところが大である。
そして、上述した従来のチルプ型積層セラミツ
クコンデンサ３は、端子電極２が、１層構造であ
る為、例えば、表中Ａ，Ｂの場合のように、ガラ
スフリツト量を減じて、端子電極２の表面の半田
付け性を向上させると、端子電極２の半田中への
溶解性が増大すると共に、半田耐熱性が低下し、
下地のセラミツク素子が露出してくる。
一方、表中Ｃ，Ｄの場合のように、ガラスフリ
ツト量を増して、半田耐熱性を向上させると、端
子電極２の表面の、半田との接合性が低下し、半
田付け性が悪化する。
このようにして、回路基板への実装時、半田付
け性と、半田耐熱性の両方を、同時に満足させる
ことは、非常に困難であつた。
INDUSTRIAL APPLICATION FIELD The present invention relates to chip-type electronic components, and in particular to the structure of terminal electrodes in chip-type multilayer ceramic capacitors. Prior Art A chip-type multilayer ceramic capacitor having a general structure as shown in FIG. 2 is manufactured as follows. First, after kneading fine ceramic powder and an organic binder, a green sheet is produced by a doctor blade method. Next, cut this sheet into the desired area, and on one side of the sheet,
Prepare a raw sheet with internal electrodes coated and dried by screen printing. Next, the desired number of green sheets with internal electrodes printed on them are stacked by sandwiching them from above and below between protective layers made of raw sheets without electrodes printed on them to form a laminate, which is heat-pressed and then cut into individual pieces. Cut to form raw chips. The raw chip pieces are fired to produce fired chips 1. At both ends, conductive paint (conductive member) containing silver as the main component and a small amount of glass frit.
is applied to form the terminal electrodes 2, 2. Finally, it is baked to produce a chip-type multilayer ceramic capacitor 3. Problems to be solved by the invention By the way, the relationship between the solderability of the terminal electrode 2 and the soldering heat resistance depends on the type of conductive paint (glass frit content), as shown in the test results in Table 1. It is important to do so. In the conventional tilted multilayer ceramic capacitor 3 described above, since the terminal electrode 2 has a one-layer structure, the surface of the terminal electrode 2 is When the solderability of the terminal electrode 2 is improved, the solubility of the terminal electrode 2 in the solder increases, and the soldering heat resistance decreases.
The underlying ceramic element is exposed. On the other hand, as in cases C and D in the table, when the amount of glass frit is increased to improve the solder heat resistance, the bondability of the surface of the terminal electrode 2 with the solder decreases, and the solderability deteriorates. In this way, it is extremely difficult to simultaneously satisfy both solderability and soldering heat resistance when mounting on a circuit board.
【表】
本考案の目的は、半田付け性と、半田耐熱性
を、同時に良好とするような、チツプ型積層セラ
ミツクコンデンサ等のチツプ型電子部品を提供す
ることにある。
課題を解決するための手段
本考案のチツプ型電子部品は、端子電極を２層
構造とし、焼成チツプ上に形成される第１の電極
層と、その上に重合して形成される第２の電極層
に区分し、第１の電極層は、90〜99重量パーセン
トの金属と、１〜10重量パーセントのガラスフリ
ツトとを含む導電部材にて、第２の電極層は、95
〜100重量パーセント金属と、５重量パーセント
以下のガラスフリツトとを含む導電部材にて形成
することにより構成される。
作 用
本考案によれば、チツプ型電子部品の端子電極
において、第１の電極層は、半田耐熱性の向上
を、また、第２の電極層は、半田付け性の向上を
担い、半田耐熱性と半田付け性を、同時に良好と
することができる。また、第１の電極層は、半田
と直接接触せず、半田付け性の性能にかかわらな
いため、導電部材中のガラスフリツト成分を多く
することが可能となり、焼成チツプと端子電極間
の接着強度も向上する。
実施例
次に、本考案に係るチツプ型積層セラミツクコ
ンデンサの一実施例について、第１図ａ，ｂを参
照して説明する。ここで、ａは斜視図、ｂは側断
面図である。
本考案によるチツプ型積層セラミツクコンデン
サは、次のようにして作製される。まず、微細化
したセラミツク粉末と有機バインダを混練した
後、ドクターブレード法によつて、生シートを作
製する。次に、このシートを、所望の面積に切断
し、その表面の片面に、スクリーン印刷により、
内部電極４を被着・乾燥した生シートを用意す
る。次に、内部電極４を印刷した生シートを、電
極を印刷しない生シートからなる保護層で、上下
から挟むようにして所望の枚数を積み重ね、積層
体を形成し、熱圧着した後、個片状態に切断し
て、生チツプ個片を形成する。この生チツプ個片
を、800〜1000℃で焼成し、焼成チツプ５を得る。
次に、この焼成チツプ５の両端に、銀を主成分と
し、１〜10重量パーセントのガラスフリツトを含
む第１層用導電塗料を、浸漬法などにより塗布し
た後乾燥し、600〜850℃で焼成して第１の電極層
６を形成する。次いで、同様に、５重量パーセン
ト以下のガラスフリツトを含有した、銀を主成分
とする第２層用導電塗料を塗布・乾燥した後、
600〜850℃で焼成して、第２の電極層７を形成す
ることにより、２層構造の端子電極８を形成し
て、チツプ型積層セラミツクコンデンサ９を作製
する。
次に、ガラスフリツト含有量を変えた第１、第
２層用導電塗料を用い、本実施例により作製した
チツプ型積層セラミツクコンデンサ９について、
半田付け性試験と、半田耐熱性試験を実施した具
体例について、その結果を第２表に示す。表中Ｅ
〜Ｈ仕様の試験結果より、本実施例による積層セ
ラミツクコンデンサ９は、半田付け性試験におけ
る半田被覆率が、85パーセント以上、半田耐熱性
試験における素地セラミツクの露出率が、10パー
セント以下であり、両性能とも、同時に良好な値
が得られた。ここで、第１表と第２表とを比較し
て、分かるように、２層構造の端子電極としたこ
とで、各層のガラスフリツト含有量が１層構造の
ものと同量であつても、半田付け性及び半田耐熱
性共に、原因は明らかでないが、若干良い結果が
得られた。
また、前記半田被覆率85パーセント以上、素地
セラミツク被覆率10パーセント以下という値は、
通常の半田付けで行われる半田槽温度約250℃、
10秒浸漬の条件下で半田付け不良を起こさない充
分な値である。[Table] An object of the present invention is to provide a chip-type electronic component such as a chip-type multilayer ceramic capacitor that has good solderability and soldering heat resistance at the same time. Means for Solving the Problems The chip-type electronic component of the present invention has a terminal electrode having a two-layer structure, with a first electrode layer formed on a fired chip and a second electrode layer formed by polymerization thereon. The first electrode layer is a conductive material containing 90 to 99 weight percent of metal and 1 to 10 weight percent of glass frit, and the second electrode layer is a conductive material containing 95 to 99 weight percent of metal and 1 to 10 weight percent of glass frit.
It is constructed by forming a conductive member containing ~100% by weight metal and 5% by weight or less glass frit. Effect According to the present invention, in the terminal electrode of a chip-type electronic component, the first electrode layer is responsible for improving solder heat resistance, and the second electrode layer is responsible for improving solderability. It is possible to improve both solderability and solderability at the same time. In addition, since the first electrode layer does not come into direct contact with the solder and has no effect on solderability, it is possible to increase the glass frit component in the conductive member, and the adhesive strength between the fired chip and the terminal electrode can be increased. improves. Embodiment Next, an embodiment of the chip-type multilayer ceramic capacitor according to the present invention will be described with reference to FIGS. 1a and 1b. Here, a is a perspective view and b is a side sectional view. The chip-type multilayer ceramic capacitor according to the present invention is manufactured as follows. First, after kneading fine ceramic powder and an organic binder, a green sheet is produced by a doctor blade method. Next, cut this sheet into a desired area, and screen print on one side of the sheet.
A green sheet on which internal electrodes 4 are adhered and dried is prepared. Next, a desired number of raw sheets with internal electrodes 4 printed on them are sandwiched from above and below between protective layers made of raw sheets with no electrodes printed on them, and a desired number of sheets are stacked to form a laminate. After thermo-compression bonding, it is cut into pieces. Cut to form raw chips. The individual raw chips are baked at 800 to 1000°C to obtain baked chips 5.
Next, a first layer conductive paint containing silver as a main component and 1 to 10 weight percent of glass frit is applied to both ends of the fired chip 5 by dipping, dried, and fired at 600 to 850°C. Then, the first electrode layer 6 is formed. Next, in the same manner, after applying and drying a second layer conductive paint containing 5% by weight or less of glass frit and containing silver as a main component,
By firing at 600 to 850° C. to form a second electrode layer 7, a terminal electrode 8 having a two-layer structure is formed, and a chip-type multilayer ceramic capacitor 9 is manufactured. Next, regarding the chip-type multilayer ceramic capacitor 9 manufactured according to this example using conductive paints for the first and second layers with different glass frit contents,
Table 2 shows the results of specific examples of solderability tests and soldering heat resistance tests. E in the table
~ From the test results of specifications H, the multilayer ceramic capacitor 9 according to this example has a solder coverage rate of 85% or more in the solderability test, and an exposure rate of the base ceramic in the solder heat resistance test of 10% or less, Good values were obtained for both performances at the same time. Here, by comparing Tables 1 and 2, it can be seen that by using a terminal electrode with a two-layer structure, even if the glass frit content in each layer is the same as that of a single-layer structure, Slightly better results were obtained for both solderability and soldering heat resistance, although the cause is not clear. In addition, the values of solder coverage of 85% or more and base ceramic coverage of 10% or less are as follows:
The temperature of the soldering bath during normal soldering is approximately 250°C.
This value is sufficient to prevent soldering defects under 10-second immersion conditions.
【表】
なお、第１層用の導電塗料中のガラスフリツト
量を、１重量パーセント未満とした場合は、焼成
チツプと端子電極の固着強度を低下させ、10重量
パーセントを越える場合は、ガラスフリツトが、
焼成時に、第２の電極層に拡散し、第２の電極層
の半田付け性を低下させるという問題があり、ま
た、第２層用の導電塗料中のガラスフリツト量
が、５重量パーセントを越える場合は、半田付け
性を極端に低下させるという問題がある。
尚、上記実施例では、導電部材（導電塗料）の
主成分である金属が銀の場合について示したが、
本考案では、銀以外の金属材料、例えば銅や錫等
や、あるいは銀をも含めそれらの合金であつても
よく、適宜選定すればよい。
更に、本考案は、チツプ抵抗、フエライトチツ
プ部品、コンデンサー抵抗ネツトワークなど、端
子電極を持つチツプ型電子部品全てに適用できる
ことはもちろんのことである。
考案の効果
以上のように、本考案によれば、端子電極が、
第１の電極層と第２の電極層とに区分され、第１
の電極層は、１〜10重量パーセントのガラスフリ
ツトを含む導電部材により、また、第２の電極層
は、５重量パーセント以下のガラスフリツトを含
む導電部材により形成されているので、回路基板
への実装時、半田付け性と半田耐熱性の両方を、
同時に満足させることができる。また、第１の電
極層は、半田付けに関与しないため、ガラスフリ
ツト量をかなり増加できるので、焼成チツプと端
子電極の固着力も向上させることができるという
効果もある。[Table] If the amount of glass frit in the conductive paint for the first layer is less than 1% by weight, the adhesion strength between the fired chip and the terminal electrode will be reduced, and if it exceeds 10% by weight, the glass frit will
There is a problem that glass frit diffuses into the second electrode layer during firing and reduces the solderability of the second electrode layer, and if the amount of glass frit in the conductive paint for the second layer exceeds 5% by weight. However, there is a problem in that the solderability is extremely reduced. In addition, in the above example, the case where the metal that is the main component of the conductive member (conductive paint) is silver,
In the present invention, metal materials other than silver, such as copper, tin, etc., or alloys thereof including silver may be used, and may be selected as appropriate. Furthermore, it goes without saying that the present invention can be applied to all chip-type electronic components having terminal electrodes, such as chip resistors, ferrite chip components, and capacitor resistance networks. Effects of the invention As described above, according to the invention, the terminal electrode is
The first electrode layer is divided into a first electrode layer and a second electrode layer.
The second electrode layer is formed of a conductive material containing 1 to 10 weight percent glass frit, and the second electrode layer is formed of a conductive material containing 5 weight percent or less of glass frit, so that when mounted on a circuit board, , both solderability and soldering heat resistance,
can be satisfied at the same time. In addition, since the first electrode layer does not participate in soldering, the amount of glass frit can be increased considerably, which also has the effect of improving the adhesion between the fired chip and the terminal electrode.
第１図は、本考案に係るチツプ型積層セラミツ
クコンデンサの実施例を示す図であり、第１図ａ
は、斜視図、同図ｂは、同図ａのＡ−A'線に沿
う断面図、第２図は、従来のチツプ型積層セラミ
ツクコンデンサの側断面図である。
５……焼成チツプ、６……第１の電極層、７…
…第２の電極層、８……端子電極、９……チツプ
型積層セラミツクコンデンサ。
FIG. 1 is a diagram showing an embodiment of a chip-type multilayer ceramic capacitor according to the present invention, and FIG.
1 is a perspective view, FIG. 2B is a sectional view taken along the line AA' in FIG. 5... Baked chip, 6... First electrode layer, 7...
. . . second electrode layer, 8 . . . terminal electrode, 9 . . . chip type multilayer ceramic capacitor.
Claims (1)
焼成チツプ上に形成される第１の電極層と、その
上に重合して形成される第２の電極層に区分し、 第１の電極層は、90〜99重量パーセントの金属
と、１〜10重量パーセントのガラスフリツトとを
含む導電部材にて、 第２の電極層は、95〜100重量パーセントの金
属と、５重量パーセント以下のガラスフリツトと
を含む導電部材にて形成したことを特徴とするチ
ツプ型電子部品。[Scope of claim for utility model registration] The terminal electrode of a chip-type electronic component has a two-layer structure,
It is divided into a first electrode layer formed on the fired chip and a second electrode layer formed thereon by polymerization, and the first electrode layer contains 90 to 99 weight percent metal and 1 to The chip is characterized in that the second electrode layer is formed of a conductive member containing 95 to 100 weight percent of metal and 5 weight percent or less of glass frit. type electronic components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9874688U JPH0410670Y2 (en) | 1988-07-26 | 1988-07-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9874688U JPH0410670Y2 (en) | 1988-07-26 | 1988-07-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0220319U JPH0220319U (en) | 1990-02-09 |
| JPH0410670Y2 true JPH0410670Y2 (en) | 1992-03-17 |
Family
ID=31325280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9874688U Expired JPH0410670Y2 (en) | 1988-07-26 | 1988-07-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0410670Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346322A (en) * | 2018-10-17 | 2019-02-15 | 成都宏明电子科大新材料有限公司 | A kind of pulse power ceramic capacitor, termination electrode and preparation method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3760770B2 (en) * | 2001-01-05 | 2006-03-29 | 株式会社村田製作所 | Multilayer ceramic electronic component and manufacturing method thereof |
-
1988
- 1988-07-26 JP JP9874688U patent/JPH0410670Y2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346322A (en) * | 2018-10-17 | 2019-02-15 | 成都宏明电子科大新材料有限公司 | A kind of pulse power ceramic capacitor, termination electrode and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0220319U (en) | 1990-02-09 |
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