JPH0510382Y2 - - Google Patents

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Publication number
JPH0510382Y2
JPH0510382Y2 JP3182587U JP3182587U JPH0510382Y2 JP H0510382 Y2 JPH0510382 Y2 JP H0510382Y2 JP 3182587 U JP3182587 U JP 3182587U JP 3182587 U JP3182587 U JP 3182587U JP H0510382 Y2 JPH0510382 Y2 JP H0510382Y2
Authority
JP
Japan
Prior art keywords
thick
lead frame
film printed
hybrid
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3182587U
Other languages
Japanese (ja)
Other versions
JPS63140675U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3182587U priority Critical patent/JPH0510382Y2/ja
Publication of JPS63140675U publication Critical patent/JPS63140675U/ja
Application granted granted Critical
Publication of JPH0510382Y2 publication Critical patent/JPH0510382Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は信頼性を損うことなく実装密度を高め
ることができるハイブリツドICの構造の改良に
関するものである。
[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to an improvement in the structure of a hybrid IC that can increase packaging density without impairing reliability.

〔考案の概要〕[Summary of the idea]

2枚の厚膜回路基板を重ね合せて両端をF字型
のリードフレームで固定するタイプのハイブリツ
ドICは、特に重ね合せた基板の内面に導体がク
ロス配線している場合、その厚さのために回路基
板端部に段差を生じ、それをリードフレームで固
定すると応力によりクラツクが生じるなどの不具
合があつた。本考案はこの不具合を除去するた
め、複数の厚膜回路基板のリードフレームをかん
合させる端子部にスペーサを挾み、これらを重ね
合せてより高密度実装を実現できるようにしたも
のである。
Hybrid ICs, which consist of two thick-film circuit boards stacked one on top of the other and fixed at both ends with F-shaped lead frames, are prone to problems due to their thickness, especially if conductors are cross-wired on the inner surface of the stacked boards. However, there were problems such as a level difference at the edge of the circuit board, and when it was fixed with a lead frame, stress caused cracks. In the present invention, in order to eliminate this problem, a spacer is inserted between the terminal portions of the lead frames of multiple thick film circuit boards, and these are overlapped to realize higher-density mounting.

〔従来の技術〕[Conventional technology]

現在実用化されている多層階構造のハイブリツ
ドICの断面図を第3図に示す。1A,1Bは厚
膜印刷基板、3はリードフレーム、4はリードフ
レーム3のクリツプ部、5は厚膜印刷基板1Bに
形成されている多層上部導体、6は絶縁ガラス、
7はスルーホール、8は表面導体、9は裏面導
体、10は抵抗である。この従来例では通常の厚
膜印刷技術から推定すると、絶縁ガラス6の膜厚
は40μm、多層上部導体5の膜厚が10μmほどあ
り、厚膜印刷基板1Aと1Bには約50μmの間隙
が生じることになる。ハイブリツドICの組立は
この状態で厚膜印刷基板の両端部をF字型のリー
ドフレーム3で挾み込み、クリツプ部4をデツプ
はんだ付けした後ハイブリツドIC全体をモール
ド材でコーテイングする。コーテイングは一例と
してモールド材を塗布したあと120℃1時間程加
熱処理を行うが、その際内部応力のためにスルー
ホール7を起点として厚膜回路基板にクラツクが
生じるという不具合があつた。その原因はリード
フレームで2枚の厚膜印刷基板を押さえ込み力
と、加熱処理地の熱膨張による重ね合わせ面の内
側から外側の向かう力とが互いに逆向きに働ら
き、また多層上部導体5と絶縁ガラス6の高さが
あるため、これが支点となつて、てこの作用によ
りスルーホール部に応力が集中してクラツクを生
じると考えられている。さらに厚膜印刷基板(通
称白基板)の状態ではすでに50μm程度のそりが
あるため、これらの基板を重ね合せると前述の応
力はより助長されることになる。
Figure 3 shows a cross-sectional view of a hybrid IC with a multilayer structure that is currently in practical use. 1A and 1B are thick film printed boards, 3 is a lead frame, 4 is a clip portion of the lead frame 3, 5 is a multilayer upper conductor formed on the thick film printed board 1B, 6 is an insulating glass,
7 is a through hole, 8 is a front conductor, 9 is a back conductor, and 10 is a resistor. In this conventional example, the film thickness of the insulating glass 6 is about 40 μm, the film thickness of the multilayer upper conductor 5 is about 10 μm, and there is a gap of about 50 μm between the thick film printed circuit boards 1A and 1B, as estimated from normal thick film printing technology. It turns out. To assemble the hybrid IC, in this state, both ends of the thick film printed circuit board are sandwiched between the F-shaped lead frames 3, the clip portions 4 are deep soldered, and then the entire hybrid IC is coated with a molding material. For coating, for example, a molding material is applied and then heat treatment is performed at 120°C for about one hour, but there was a problem in that internal stress caused cracks in the thick film circuit board starting from the through holes 7. The reason for this is that the force holding down the two thick-film printed circuit boards with the lead frame and the force directed from the inside to the outside of the overlapping surfaces due to thermal expansion of the heat-treated material act in opposite directions, and the multilayer upper conductor 5 It is believed that the height of the insulating glass 6 acts as a fulcrum and causes stress to concentrate on the through-hole portion due to a lever action, causing a crack. Furthermore, thick-film printed substrates (commonly known as white substrates) already have a warpage of about 50 μm, so if these substrates are stacked on top of each other, the stress described above will be further exacerbated.

以上の不具合を回避するためには厚膜回路基板
A,Bの間隙にバツフア材を充填するか、厚膜回
路基板の端部にスペーサとしてダミーの絶縁ガラ
ス、導体等を印刷することが考えられる。
In order to avoid the above problems, it is possible to fill the gap between thick film circuit boards A and B with buffer material, or print dummy insulating glass, conductor, etc. as a spacer on the edge of the thick film circuit board. .

しかしこの手法ではバツフア材の充填量のばら
つき、スペーサの膜厚のばらつきなど微妙なパラ
メータが干渉して、信頼性及び安定性に欠けるも
のであつた。また、各パラメータを長時間かけて
シビアに条件出しをしてハイブリツドICの設計、
組立て作業を安定化させても、この方法では厚膜
印刷基板毎にクロス配線、スルーホールの位置が
変れば全くのカツトアンドトライ的手法になり、
生産設計上は効率の悪いものであつた。
However, this method lacks reliability and stability due to the interference of delicate parameters such as variations in the filling amount of the buffer material and variations in the film thickness of the spacer. In addition, we design hybrid ICs by carefully setting each parameter over a long period of time.
Even if the assembly work is stabilized, this method becomes a completely cut-and-try method if the positions of cross wiring and through holes change for each thick film printed circuit board.
The production design was inefficient.

〔考案が解決しようとする問題点〕[Problem that the invention attempts to solve]

本考案は以上の不具合に鑑みてなされたもの
で、複数の厚膜回路基板を重ね合わせて各部の応
力を逃がす構造にしたことでありその目的は信頼
性を低下させることなく従来の技術の延長線上で
の制作にて、より集積したハイブリツドICを提
供することにある。
This invention was devised in view of the above-mentioned problems, and consists of stacking multiple thick-film circuit boards to create a structure that relieves stress from each part.The purpose is to extend the conventional technology without reducing reliability. Our goal is to provide more integrated hybrid ICs through on-line production.

〔問題点を解決するための手段〕[Means for solving problems]

本考案は上記目的を達成するため、従来の厚膜
印刷基板のリードフレームのクリツプとかん合す
る部分にスルーホールをあけてリードフレームの
ピンを挿入し、言うなれば、ピンで厚膜印刷基板
を串ざし状にして多層階構造にしたものである。
In order to achieve the above object, the present invention creates a through hole in the part of the conventional thick film printed circuit board that engages with the clip of the lead frame and inserts the pin of the lead frame. It is a skewer-shaped building with a multi-story structure.

〔実施例〕〔Example〕

以下本考案の一実施例を第1図及び第2図に示
す。第1図は第3図と同じタイプの厚膜印刷基板
のクリツプとかん合させる部分にスルーホールを
設け、そこへリードフレームのピンを挿入して多
層階構造とし、かつ基板相互間へスペーサを入れ
て基板間に若干の間隙を設けることで前述の内部
応力のストレスを逃がす構造にしている。ここで
3〜10は第3図と同一部分であり、1Aは1階
層厚膜印刷基板、1B,1Cは同様に3階層、2
階層を示している。4Aはリードフレーム3に一
体化形成されたピンの折り曲げ部であり、まつす
ぐなピンを基板を重ね合わした後適宜な方法で折
り曲げている。ここでは折り曲げを一例として示
したが、はんだ付時までに厚膜印刷配線板が動な
ければ、ピンをつぶすか、ねじる等の適宜な手段
でもよい。第2図はスペーサ11を拡大した斜視
図である。ここで111はスペーサコア部で材質
な熱膨張が小さく、リードフレームのはんだ付に
耐えられるものであればどんなものでも良い。1
12はリードフレーム3のピンを挿入するための
穴であり、ピンとのクリアランスは十分にとつて
いる。また113は板状のプリフオームはんだで
111と同一部に穴をあけてある。さらに114
はプリフオームはんだ113に形成した切り欠き
部でリードフレーム3をはんだ付した際、各々の
穴に良好にはんだが供給されるようにしたもので
ある。尚、コア111とプリフオームはんだ11
3は単に重ね合せた状態を想定して示してあるが
一体化形成しても良い。
An embodiment of the present invention is shown in FIGS. 1 and 2 below. Figure 1 shows the same type of thick-film printed circuit board as in Figure 3, with through-holes formed in the parts to be mated with the clips, and pins of the lead frame inserted into the holes to create a multi-layered structure, and spacers installed between the boards. The structure is such that the above-mentioned internal stress is released by providing a slight gap between the substrates. Here, 3 to 10 are the same parts as in FIG.
Shows hierarchy. 4A is a bent portion of a pin formed integrally with the lead frame 3, and a straight pin is bent by an appropriate method after overlapping the substrates. Although bending is shown here as an example, if the thick film printed wiring board does not move by the time of soldering, appropriate means such as crushing or twisting the pins may be used. FIG. 2 is an enlarged perspective view of the spacer 11. Here, reference numeral 111 denotes the spacer core, and any material may be used as long as it has a small thermal expansion and can withstand soldering of the lead frame. 1
Reference numeral 12 denotes a hole for inserting a pin of the lead frame 3, and there is sufficient clearance between the hole and the pin. Further, 113 is a plate-shaped preform solder, and a hole is made in the same part as 111. 114 more
When the lead frame 3 is soldered to the notch portion formed in the preform solder 113, the solder is properly supplied to each hole. In addition, the core 111 and the preform solder 11
3 is shown assuming a state in which they are simply overlapped, but they may be formed integrally.

第1図で分るようにスペーサ11の厚さは、厚
膜印刷基板1Bと1C、又は1Cと1Aの間に形
成された導体及び絶縁体層の厚さより若干厚くし
てあるので、それらが互いにぶつかり合うことに
よる応力は発生しない。また、仮に1A〜1Cの
厚膜印刷基板に当初からそりが生じていても、ス
ペーサ11の厚さにその値を見込んでおけばさら
に良好な結果が得られる。以上のように各厚膜印
刷基板をスペーサを介して重ね合せ、その状態で
リードフレームのピン4Aを折り曲げれば構造的
にストレスフリーの状態とすることができる。
As can be seen in FIG. 1, the thickness of the spacer 11 is slightly thicker than the thickness of the conductor and insulator layers formed between the thick film printed circuit boards 1B and 1C or between 1C and 1A, so that they No stress is generated by hitting each other. Further, even if the thick-film printed substrates 1A to 1C have warpage from the beginning, even better results can be obtained if the thickness of the spacer 11 is taken into account. As described above, by stacking the thick film printed circuit boards with spacers in between and bending the pins 4A of the lead frame in this state, a stress-free state can be achieved structurally.

ここで第2図からも分るように、本実施例では
リードフレームのピンを挿入する穴を一例に配置
してあるが、ピツチの関係で白基板の加工が難し
ければ千鳥配列にする等の工夫をしても良い。一
方、リードフレーム3と各厚膜印刷基板の端子部
のはんだ付は、基板の重ね枚数が2枚のときは従
来のデイプ法で支障ないが、3枚以上になると第
1図の例では基板1Cのはんだ供給に不安が残
る。そこでその解決法の一例として第2図に示す
ように、コア111の上に板状のプリフオームは
んだを重ね合わせてデイプはんだ付けすれば、そ
れが厚膜印刷基板1Cのスルーホールへ供給され
厚膜印刷基板のスルーホールとピンを接続するこ
とができる。また図面には明記していないが厚膜
印刷基板1Cを重ね合せた時点で、デイスペンサ
を用いて各スルーホールへクリームはんだを供給
する等の方策を講じてもよい。尚、以上の内容で
は厚膜印刷基板1A〜1Cの材質はアルミナ等の
セラミツクスを前提にしているが、一般の樹脂基
板でも良く、また、厚膜印刷基板の重ね枚数を制
限するものでもない。
As can be seen from Fig. 2, in this example, the holes for inserting the pins of the lead frame are arranged as an example, but if it is difficult to process the white board due to the pitch, it may be arranged in a staggered arrangement, etc. You can try your best. On the other hand, when soldering the terminals of the lead frame 3 and each thick film printed circuit board, the conventional dipping method has no problem when the number of stacked boards is two, but when the number of stacked boards is three or more, Concerns remain regarding the supply of 1C solder. As an example of a solution to this problem, as shown in FIG. 2, if a plate-shaped preform solder is superimposed on the core 111 and deep soldered, the preform solder is supplied to the through hole of the thick film printed circuit board 1C, and the thick film You can connect pins to through holes on printed circuit boards. Although not clearly shown in the drawings, it is also possible to take measures such as supplying cream solder to each through hole using a dispenser when the thick film printed circuit boards 1C are stacked on top of each other. In the above description, it is assumed that the material of the thick-film printed substrates 1A to 1C is ceramic such as alumina, but a general resin substrate may be used, and there is no restriction on the number of stacked thick-film printed substrates.

〔考案の効果〕[Effect of idea]

以上、本考案によれば、現状のハイブリツド
IC製造技術の延長線上で、一般的に困難とされ
ている厚膜印刷基板の多層階構造のハイブリツド
ICを実現することができる。また、技術的には
基板の重ね枚数を制限することがないことから
も、実装密度的には従来の湿式ビルトアツプ法に
迫るものであり、コスト面ではスペーサ代を差し
引いても、湿式法に必要である金型費と比べれば
大幅なコストダウンが可能である。
As described above, according to the present invention, the current hybrid
As an extension of IC manufacturing technology, we are developing a hybrid multilayer structure for thick-film printed circuit boards, which is generally considered difficult.
IC can be realized. In addition, since there is no technical limit to the number of stacked boards, the packaging density approaches that of the conventional wet build-up method, and in terms of cost, even after subtracting the spacer cost, the mounting density is close to that of the conventional wet build-up method. Compared to the mold cost, significant cost reductions are possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す断面図、第2図
は第1図に示したスペーサの拡大斜視図、第3図
は従来例を示す断面図である。 1A〜1C……厚膜印刷基板、3……リードフ
レーム、4,4A……リードフレームのクリツプ
部、5……多層上部導体、6……絶縁ガラス、7
……スルーホール、8……表面導体、9……裏面
導体、10……抵抗、11……スペーサ。
FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is an enlarged perspective view of the spacer shown in FIG. 1, and FIG. 3 is a sectional view showing a conventional example. 1A to 1C...Thick film printed circuit board, 3...Lead frame, 4, 4A...Clip portion of lead frame, 5...Multilayer upper conductor, 6...Insulating glass, 7
... Through hole, 8 ... Surface conductor, 9 ... Back conductor, 10 ... Resistor, 11 ... Spacer.

Claims (1)

【実用新案登録請求の範囲】 1 デユアルインライン型のハイブリツドICを
形成するための厚膜印刷基板において、リード
フレームをかん合させる端子部にスルーホール
を設け、そこへリードフレームと一体若しくは
単独に形成したピンを挿入し、さらにスペーサ
と厚膜印刷基板を交互又は順不動に重ね合わせ
てピンで串ざし状にした状態で、各厚膜印刷基
板の端子部とリードフレーム及びそのピンをは
んだ付して形成したことを特徴とするハイブリ
ツドIC。 2 各厚膜印刷基板間に挾んだ前記スペーサは、
はんだ付等の手法によつてリードフレームのピ
ンと固定されるようにしたことを特徴とする実
用新案登録請求の範囲第1項記載のハイブリツ
ドIC。 3 前記厚膜印刷基板はセラミツクスの代わりに
ガラス布エポキシ等の樹脂基板を用いたことを
特徴とする実用新案登録請求の範囲第1項又は
第2項記載のハイブリツドIC。
[Claims for Utility Model Registration] 1. In a thick-film printed circuit board for forming a dual-in-line hybrid IC, a through hole is provided in the terminal portion to which the lead frame is to be mated, and the through hole is formed integrally with the lead frame or independently. Then, while the spacers and thick-film printed circuit boards are stacked alternately or in a fixed order, and the pins are skewered, solder the terminals of each thick-film printed circuit board, the lead frame, and the pins. A hybrid IC characterized by being formed using 2 The spacer sandwiched between each thick film printed board is
2. The hybrid IC according to claim 1, wherein the hybrid IC is fixed to a pin of a lead frame by a method such as soldering. 3. The hybrid IC according to claim 1 or 2, wherein the thick film printed substrate uses a resin substrate such as glass cloth epoxy instead of ceramics.
JP3182587U 1987-03-06 1987-03-06 Expired - Lifetime JPH0510382Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3182587U JPH0510382Y2 (en) 1987-03-06 1987-03-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3182587U JPH0510382Y2 (en) 1987-03-06 1987-03-06

Publications (2)

Publication Number Publication Date
JPS63140675U JPS63140675U (en) 1988-09-16
JPH0510382Y2 true JPH0510382Y2 (en) 1993-03-15

Family

ID=30837917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3182587U Expired - Lifetime JPH0510382Y2 (en) 1987-03-06 1987-03-06

Country Status (1)

Country Link
JP (1) JPH0510382Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241454A (en) * 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package

Also Published As

Publication number Publication date
JPS63140675U (en) 1988-09-16

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