JPS58138095A - Method of producing ceramic multialyer circuit board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the manufacture of Ceracic multilayer wiring boards, and more specifically to the drilling of conductive holes in the gold layers to be laminated and the filling of conductive paste into the holes. Embroidery of the gold layer is performed simultaneously on the same gold layer, using only the conductive paths necessary for connecting the upper and lower layers, and closing the unnecessary four paths by laminating the layers. Replacement of cost and gold layer II & Setstsutsu multi-layer circuit board O to reduce cost and opening time and create drama at low cost
It concerns the construction method.

The conventional CERASEC multilayer wiring board OIl manufacturing method is as follows.

Cut the green sheet to the number of sheets to be laminated.

A conductive hole is formed at a prescribed position in each layer using a punched gold layer for each layer, and Wt9 is excited or Wt is inserted into the conductive hole.
+ Mo O metal powder was prepared by mixing a binder and a scattering agent, and the leading conductive paste was packed into holes for each layer, and then the 011111 distribution was printed for each layer,
This is stacked and bonded, heated and resin is removed, and then sintered to produce a 10"e6x9. According to this manufacturing method, each layer to be laminated has 0.
4) Conductive holes must be punched at specified positions using the punched gold layer for each layer, and IK filling the holes with conductive paste must be performed separately for each layer. Therefore, it was necessary to make separate K11 punching metal bolts and a gold layer for filling the holes at different hole positions for the 709th through holes. In addition, the gold layer cost was a bonus, and it took a lot of time to set up the replacement of the rounded gold layer during drilling, so the sII construction was extremely difficult. In addition to that, recently O high book hawk ^ integrated OI
The number of laminated layers increased to 100% due to demand, and the number of conductive holes provided in each layer increased as well.

This increases production time and production costs.

Motoya solves the above problems and at the same time improves the efficiency of the shaving process 1 without degrading the quality of the finished product. It is also O according to the content of the summary aS claims.
Conductive holes for forming conductive paths in the gold layers to be laminated are simultaneously drilled in all six layers of green sheets in the same manner, and all conductive holes are made conductive at the same time. Fill the holes with paste at the same time to create a conductive path and connect it to the upper and lower layers! A manufacturing method is adopted in which wiring circuits are printed on the top surface of each layer using only conductive paths, and unnecessary conductive paths are closed by laminating and bonding. Regardless of the number of laminated layers of the rounded multilayer wiring board, the conductive hole O hole
Minimum number of 1ltIP' and hole filling machine parts -'t"a
We will use a procurement method that is highly efficient in manufacturing multilayer wiring boards with a large number of laminated boards, using products that can be manufactured by GUSM.

By adopting the manufacturing method of the present invention), the cost of making gold layer, the period of making gold layer, and the time for changing meals can be reduced or shortened to less than the conventional method. <Useful circle. '*9 The completed product of the multilayer wiring board was superior to the conventional product in terms of quality and quality.

Hereinafter, IF details will be explained using examples, but this will not be determined within the scope of the gist of the present invention.

Example Mu 110s Powder Octopus Weight - Added sintering agent to CaO5Mg
0, 810s O gold amount 1% by weight tlsjt gold total 10
0m, peptizer ajms butyral resin-1@.

DIP (dibutyl phthalate) Jilt ethanol J
oOII *) Add Luen Joy* and in the scolding room/
j Time turns into a whirlpool and turns into mud. A green plate of thickness o, j is formed using a known doctor blade fiber on a plastic film made of IOx/DO.
Prepare one sheet by cutting it to the dimensions of -.

Below, I will explain from the first JIK, which is the original @Ohiraga. Figure B is the intermediate layer. Figure C' is a plan view of the lower layer. As with the case of the green sheet, all of the rounded conductive holes for forming conductive paths necessary for connecting the upper and lower layers of this one layer are drilled between the J layers using holes 11aJwK. One particle size I ~ jp @ in the conduction hole
Add ethyl cell resin and butylcarpitol acetate (OIII) agent to Q Tandasten powder wheel, make it into a wave shape, and inject it between the J) J layers using the press-in method to form a conductive path/Jt.
ii Required wiring printing on the top surface of each 1st layer to be formed/J@
, /1b, and /Ja are formed using the above-mentioned tungsten liquid material. At this time, the 0th order KJ layer is stacked on top of each other so that the wiring is printed in the same position as the wiring, and the 0th order KJ layer is formed at a distance of 9 J6 that does not intersect with any unnecessary conductive paths. With the conduit passage closed, laminated and bonded under pressure at a temperature of 111!76cm11, a resin shield at a temperature of JOOC#PK, and a hook at a temperature of tzzocyc in a mixed atmosphere of hydrogen and nitrogen, were integrated. A multilayered base I[O decorated bell body was obtained.

Then, the silicon chip is mounted in the specified position and used for installation in the device. At this time, there were no problems with the insulating neutrality of the board, and it was used successfully.

Comparative example Figure 1 is a 1000-page drawing of the conventional method, and the
This will be explained from IIJIIK, which is a cross-sectional view of O laminated adhesive. s
The M diagram in Figure 1 is laminated and bonded and is located in the upper layer, Bll is the middle layer, and Figure 0 is the lower layer.
+ ' b + 76 is the same green sheet as 9 molded in the above embodiment, and a conductive path 1a+J between the upper and lower layers
The forming method b*Jo uses each individual punching metal part to punch through holes. Rounding 1 which in this case is 3 layers
Use the metal part of the stand. One layer of the same tungsten paste as in the above embodiment was separately injected into the conductive holes by the injection method to form conductive paths J&*Jb*JO.

Next, print wiring on the top surface of each layer J&+J b * J c
Form it with the above tungsten paste.Next, stack one layer and bond by applying pressure while heating.
Firing was performed under the same conditions as in the example, and a sintered body of nine multilayer wiring boards was obtained. The sintered body is subjected to surface treatment with KNi plating and MuU plating, and a silicon chip is mounted at a specified position for use.

The above examples and comparative examples are based on the drawings regarding the O manufacturing method.
I explained using the simplest three-layer wiring board as an example, but
Usually, one or more sheets are common. In Mochichi, the production of ~10 laminated wiring boards is increasing due to the demand for higher density integration.The manufacturing method of the present invention reduces production costs, production time, and stages of production. It is an artist who can greatly reduce or shorten replacement time, greatly reduce manufacturing costs, and ensure quality assurance, making it an artist who can contribute to industry.

[Brief explanation of drawings]

Figure 1 is a circular view of the product formed using the conventional manufacturing method.
Figure 0 shows the bottom layer of a 6D, mK-p resolute stack of IIJ
IK is a plan view of each layer formed by the manufacturing method of the present invention. '& a / b m / @ e /'a+//b
+/10 ”” Green sheet, Co1. Kob, Koc
, /J... Conduction path to upper and lower layers, J & * J b
a.

Claims (1)

[Claims] V) Conductive circuit O wiring printed on the upper surface of each layer to be laminated, and a conductive path connecting the O wiring of each layer above and below the layer.Ceraic multilayer wiring created by stacking and bonding green sheets and firing. In the method for manufacturing a substrate, the above 1. At the time of lamination, conductive paste is generally applied to all the conductive holes of the gold layers to be laminated. Fill the holes in all layers at the same time to create a conductive path, print a hoisting circuit on the top of each layer using only the conductive paths necessary for connection with the upper and lower layers, and glue them together to eliminate unnecessary conductors. A method for producing a one-rank multilayer wiring board according to 411Ik, in which the passages are closed and the resin is removed by heating, followed by sintering in a non-oxidizing atmosphere at l≠10-/400C. -) Patent-Kyo no Han-Laminated gold layer O11 described in s1
(3) Scope of claims m*iil [IF! Posted by 金layer-co. A method for manufacturing a ceramic ivy multilayer wiring board, in which filling the through holes with conductive paste and filling the holes at the same time in the same gold layer is a 41I feature.