JPS6059504A - Muting circuit of tape recorder - Google Patents

Abstract

PURPOSE:To suppress noise generated at the ON/OFF of a power source with a simple circuit by using a muting circuit suppressing noise generated at the switching of sound recording and reproducing. CONSTITUTION:An inversion circuit 12 is inverted every switching of a sound recording/reproducing alteration switch 9 and outputs a control signal for a prescribed period. A muting transistor (TR) 29 is kept at connected state during its collector/emitter line is connected between a signal transmission line and the earch and a control signal from the circuit 12 is impressed to its base. When a detecting circuit 17 detects the output voltage of a rectifier/smoothing circuit 3 and reduces its level, a trigger circuit inverts the circuit 12 at the ON of the power source and a capacitor 5 is always charged at the time of power supply. Power supply to the circuits 12, 17 is executed through the circuit 3 at the ON of the power source and by the discharged charge of the capacitor 5 at the OFF of the power source.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a tape recorder, and particularly to a miniting circuit that suppresses noise generated when power is turned on and off.

(b) Prior Art A high-grade tape recorder called a tape deck is used by being connected to an amplifier with a high output, so the noise generated by the tape recorder is amplified by the amplifier and then emitted at a high level from the speaker. This will cause discomfort to the user. Some of the noise generated by tape recorders occurs when switching operations, but the level of noise generated when the power is turned on and off is particularly large, and a circuit to suppress such noise is called muting. Various circuits have been developed. Conventional muting circuits are often configured separately for noise prevention when the power is turned on, noise prevention when the power is turned off, and noise prevention during normal operation, resulting in a complicated circuit configuration. was there.

(C) Purpose of the Invention The present invention seeks to provide a circuit that can suppress the noise generated when the power is turned on and turned off by using a meeting circuit that suppresses the noise generated when switching between recording and playback. be.

B) Structure of the Invention The present invention provides a recording and playback switch that switches a tape recorder between a recording state and a playback state, an inversion circuit that inverts each time the recording and playback switch is switched and outputs a control signal for a predetermined period of time, and a signal A muting transistor whose collector-emitter path is connected between the transmission path and the ground and which becomes conductive while the control signal from the inverting circuit is applied to the pace, and detects the output voltage of the rectifier and smoothing circuit. and a detection circuit that causes the inverting circuit to perform an inverting operation when the output voltage decreases, a trigger circuit that causes the inverting circuit to perform an inverting operation when the power is turned on, and a capacitor that is constantly charged when the power is supplied, Power is supplied to the inverting circuit and the detection circuit by the rectifying and smoothing circuit when the power is turned on, and by the discharged charge of the capacitor when the power is turned off.

(E) Embodiment The illustrated circuit is an embodiment of the miniting circuit of the present invention. In the figure, (1) is a power supply terminal connected to the commercial power supply, (2) is a power switch that is closed when power is supplied, and (3) is a power supply terminal that is equipped with a power transformer and is connected to the power supply through the power switch (2). (4) is a constant voltage circuit that converts the DC signal obtained from the rectifier and smoothing circuit (3) to a predetermined voltage; It has the function of supplying DC power. (5) is supplied with direct current from the rectifier and smoothing circuit (3) through the diode (6) and Zener diode (7) when the power is turned on, and is charged, and when in a steady state, from the constant voltage circuit (4). A direct current is supplied through the diode (8) to the capacitor which is charged. That is, in such a circuit, the diode (8)
The voltage applied to the capacitor (5) through the diode (6) and the Zener diode (power) is set to be higher than the voltage applied through the diode (6) and the Zener diode. The output voltage of (3) is configured to rise faster than the output voltage of the constant voltage circuit (4) and fall earlier when the power is cut off.(9) is switched by the recording/playback switching operation of the tape recorder. It is a recording/playback selector switch, and has a common terminal (C), a playback side terminal ω), and a recording side terminal (2), and during switching operation, the playback side terminal (P) and the recording side terminal (switching switch (S)) The common terminal (C) of the recording/playback selector switch (9) is composed of a so-called non-switching type switch that will not be short-circuited.
is connected to the output terminal of the constant voltage circuit (4), and the playback side terminal (P) and the recording side terminal (2) are commonly connected and grounded via resistors Cl0) and 01). . It is an inverting circuit that enters an inverting operation state for a predetermined period of time when triggered, and one input terminal is connected to the resistor 01 and αl.
) @INAND circuit O connected to voltage dividing point (4)
A second NAND circuit that inverts the output of the first NAND circuit a.
It consists of an AND circuit (+4), a capacitor 05 for determining the inversion operation time, and a resistor ae. The side is a detection circuit that detects the output voltage of the rectifier and smoothing circuit (3), and includes a Zener diode and a resistor connected in series between the output terminal of the rectifier and smoothing circuit (3) and the ground.
The voltage dividing point between the Zener diode 08 and the resistor Ql [F])
A third NAND circuit Qυ is connected to the input terminal thereof, and a fourth NAND circuit Qυ is applied with an output signal of the third NAND circuit and inverts the level thereof. The output terminal of the fourth NAND circuit CD is connected to the input terminal of the first NAND circuit H constituting the inverting circuit (2) through a diode (2).
is the recording/playback selector switch (9) when the power is turned on, and the resistance QOI
This is a capacitor that is charged by the current from the constant voltage circuit (4) through a diode and a diode, and has the function of inverting the inverting circuit 0 when the power is turned on. 0 is a diode that discharges the electric charge stored in the capacitor (J3) when the power is cut off. (2e
is an input terminal to which a playback signal is applied during playback operation and a recording signal is applied during recording operation, (C) is a recording/playback amplifier circuit that amplifies the signal applied to the input terminal a6), and ⑼ is the input terminal for the recording operation. This is an output terminal to which a signal amplified by the reproducing/amplifying circuit (5) is applied. The wire is the signal transmission line f':! of the recording/playback amplifier circuit 07). The collector is connected to A and the emitter is grounded.
The base of the muting transistor is connected to the output terminal of the first NAND circuit OS constituting the inverting circuit U via a resistor 01) and a Zener diode 02. In such a circuit, the inverting circuit (the first NAND circuit a3 constituting the first NAND circuit) and the second
NAN 'I') circuit (14), and a third NANT) circuit (201 and fourth NAND) constituting the detection circuit 0
The power supply terminal of the circuit (21) is connected to the capacitor (5).
connected to the power supply terminal.

The muting circuit of the present invention is constructed as described above, and the operation of this circuit will now be described. The illustrated state is a non-power supply state, and when the power switch (2) is closed in such a state, an AC signal is applied from the commercial power source to the rectifying and smoothing circuit (3), and the rectifying and smoothing circuit (3)
A DC signal that has been rectified and smoothed is output. Further, the DC signal output from the rectifying and smoothing circuit (3) is applied to a constant voltage circuit (4), and the voltage is made constant and output.

When a DC signal is output from the rectifying and smoothing circuit (3), a charging current is applied to the capacitor (5) through the diode (6) and the Zener diode (7), and the capacitor (5) is quickly charged. Therefore, the power switch (2
) is closed and power is supplied, the capacitor (5) is immediately charged, 1st NAND circuit 0■, 2nd NAND circuit
circuit 04), the third NAND circuit (2(1) and the fourth NAND circuit (21), since the KIt source is supplied, each N
The AND circuit becomes operational. Furthermore, when the DC voltage is output from the constant voltage circuit (4), a charging current is passed through the recording/playback switch (9), the resistor GO) and the diode Ca4) to the capacitor 0 for a predetermined period of time, during which time an inverting circuit is formed. One input terminal of the first NAND circuit α is held at the T (low) level. As a result, the inverting circuit U is triggered to perform an inverting operation, and the first
An H (high) level signal is output to the output terminal of the NAND circuit 03). The H level signal output to the output terminal of the first NAND circuit 03) is connected to the Zener diode C.
321 and resistor 01) are made conductive and applied to the pace of the meeting transistor wire, thereby making the muting transistor wire conductive for a predetermined period of time. Therefore, the signal transmission path (to) is grounded by the muting transistor 〇'l, and signals such as noise are not output to the output terminal (28). Then, after a predetermined period of time has elapsed, the inverting circuit returns to its original state and the first
Since the output of the NAND circuit (+31) becomes L level, the muting transistor wire is inverted to a non-conducting state. When the power switch (2) is closed, the above-mentioned operation is performed and each circuit is in a steady state, but In such a steady state, the charging potential of the capacitor (5) is set by the voltage applied from the constant voltage circuit (4) through the diode (8). 4th NA forming detection circuit 0
An H level signal is output to the output terminal of the ND circuit 0υ. If a reproduction operation is performed in such a state, the tape recorder enters a reproduction operation state, and the reproduction signal reproduced by the magnetic head is applied to the input terminal (26). The playback signal applied to the input terminal (c) is input to the recording/playback amplifier circuit Qη, amplified, and then output to the output terminal (mark 2).The playback signal output to the output terminal (c) is amplified by an amplifier with high output, and then applied to a speaker to emit sound.

As described above, the muting operation and the tape recorder playback operation are performed when the power is turned on.Next, the operation when the recording operation is performed will be explained. When the user performs a recording operation, the switch (S) of the recording/playback switch (9)
Q is switched from the playback terminal to the recording terminal, but in the middle of the switching, the common terminal (Q is the playback terminal) and the recording terminal is disconnected from the recording terminal.As a result, the inversion circuit One input terminal of the first NAND circuit (13) constituting the NAND circuit becomes L level, and the inverting circuit 0 is triggered and becomes active.When the inverting circuit becomes active, the muting transistor r29 is activated as described above.
) is in a conductive state for a predetermined period of time to perform a muting operation, so that the noise generated at the time of switching is not applied to the magnetic head and is not recorded on the magnetic tape. When a recording operation is performed, the recording operation is started after the above-described muting operation has been completed for a predetermined period of time. If you perform an operation such as stopping while the tape recorder is in the recording mode, the switch (81) of the recording/playback switch (9) will be switched from the recording side terminal (R) to the playback side terminal. When this is done, the inverting circuit is triggered and enters the operating state in the same manner as the switching to the recording state described above. Since the muting operation is performed by the muting transistor wire while the inverting circuit side is inverted to the operating state, noise caused by the cancellation of the recording operation is not outputted to the output terminal C barrel.

As described above, the muting operation is performed by switching the recording/playback selector switch (9), but then the power switch (2) is switched.
) is opened and the power is cut off. When the power switch (2) is opened, the rectifier and smoothing circuit (3)
The output voltage of the constant voltage circuit (4) drops quickly, but the output voltage of the constant voltage circuit (4) drops with a delay.

In addition, the electric charge that had been charged in the capacitor (5) during the operating state is prevented from being discharged to the power supply circuit by the diodes (6) and (8), and the discharged electric charge is transferred to the first NAND circuit that constitutes the inverting circuit side. α□□□, 2nd NAN
3rd NAND that constitutes D circuit (+4) and detection circuit 0
It is supplied as an operating power source for the circuit board and the fourth NAND circuit (21). When the output voltage of the rectifying and smoothing circuit (3) quickly drops as the power switch (2) is opened, the input terminal of the third NAND circuit (20) forming the detection circuit I becomes L level and its output becomes H level. As a result, that H
The output of the fourth NAND circuit CD to which the level signal is input becomes L level. When the output of the fourth NAND circuit (21) becomes L level, the first NAND circuit configured as an inverting circuit
One input terminal of the circuit 03) becomes L level, and the inverting circuit 0 is triggered and becomes operational. When the inverting circuit side becomes operational, the miniaturing transistor wire becomes conductive for a predetermined period of time and performs a muting operation, as described above, and as a result, noise due to power cut-off is output to the output terminal (c). There isn't.

In this embodiment, the operation was explained in which the power was cut off and supplied by the opening/closing operation of the power switch (2), but the power was controlled by a timer device while the power switch (2) remained closed. A similar operation can also be performed in this case. There is also a recording/playback selector switch (9
) has been described with reference to the muting operation when power is supplied when the recorder is at the playback position, but a similar muting operation can also be performed when power is supplied when the recorder is at the recording position.

(f) Effects of the Invention The miniting circuit of the present invention performs a switching operation in a steady state and uses a muting circuit that suppresses the noise generated with the recording/playback switching operation, and only when the power is turned on. Since the noise generated when the power is cut off is suppressed, the circuit configuration is simplified, and the present invention is most suitable as a muting circuit for a tape recorder connected to an amplifier having a large output.

[Brief explanation of the drawing]

The illustrated circuit is one embodiment of the meeting circuit of the present invention. Explanation of main drawing numbers (2)...power switch, (3)...rectifier smoothing circuit, (4)...constant voltage circuit, (9)...recording/playback selector switch, O2... Inversion circuit, country 0...first NAND circuit, (I4)...second NAND circuit,
Re: Detection circuit, (Second cap: Third NAND circuit,
(2υ...4th NAND circuit, (A)...input terminal, (Foundation)...recording/playback amplifier circuit, wire...
・Output terminal, wire...miniuting transistor, (to)...signal transmission path.

Claims (1)

[Claims] (]) A tape recorder equipped with a rectifying and smoothing circuit that rectifies and smoothes an alternating current signal obtained from a commercial power source into a direct current signal, and a constant voltage circuit that adjusts the direct current signal obtained from the rectifying and smoothing circuit to a predetermined voltage. a recording/playback changeover switch that switches between the recording and playback states, an inversion circuit that inverts each time the recording/playback changeover switch is switched and outputs a control signal for a predetermined time, and a collector-emitter path connected between the signal transmission path and ground. a muting transistor that is conductive while a control signal from the inverting circuit is applied to the pace; and a muting transistor that detects the output voltage of the rectifying and smoothing circuit and activates the inverting circuit when the output voltage decreases. It consists of a detection circuit that causes the inversion circuit to perform an inversion operation, a trigger circuit that causes the inversion circuit to perform an inversion operation when the power is turned on, and a capacitor that is constantly charged when power is supplied. A muting circuit for a tape recorder, characterized in that when the power is turned on, the muting is performed by the rectifying and smoothing circuit, and when the power is turned off, the muting is performed by the discharged charge of the capacitor.