JPS6051923A - Synchronizing system - Google Patents

Abstract

PURPOSE:To take easily timing by constituting a titled system so that a CPU stops its processing until a prescribed timing signal comes, and executes immediately the next operation when the timing signal is received. CONSTITUTION:A titled system is provided with a register 10 for setting an MEM address to a main storage device MEM by a program, and an MEM address coincidence controlling circuit 15 for monitoring the MEM address when transferring data and sending out an MEM address coincidence signal when said address coincides with the contents of the register 10. A CPU is provided with an MEM address coincidence signal holding register 20 for holding the MEM address coincidence signal, and an instruction processing circuit 21 for processing an instruction. The circuit 21 refers to the register 20, and timing is taken so that unless the MEM address coincidence signal is reported, processing of a synchronizing instruction is stopped until said signal is reported, and when the coincidence signal is reported, the next operation is executed immediately after resetting its signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization method, and more particularly, to a synchronization method that facilitates testing of delicate timing between multiple devices in a test function of a data processing device. In the test, for example, as an input/output operation test between the device and the central processing unit (hereinafter referred to as OPU),
OJ during input/output operation of the device? When starting an input/output command from U and expecting some kind of result, a method for determining the timing to start the input/output command is to set the timing after a time calculated based on the performance of the input/output device. was taken. However, there is a drawback that it is difficult to start an input/output command at the expected timing when the device performance changes or due to variations in performance.

Furthermore, the a channel command word specifies the generation of a program control interrupt that generates an interrupt when the channel command word, which is one of the seven functions of the channel command word that controls data transfer between the device and the main memory, is activated. The channel command word is activated by an input/output instruction with the main memory data transfer start address in the memory corresponding to the timing, and the time when a program control interrupt occurs is considered as the timing to activate the input/output instruction. Although there is a method to do this, it is necessary to reset the interrupt when an interrupt occurs and cover various states by a program, which has the drawback that the timing of starting the input/output command is delayed.

The present invention has been made in view of the above-mentioned conventional circumstances.
Therefore, an object of the present invention is to stop the OPU at the point when it wants to exchange timing with the device, report the predetermined timing while the device is operating to the OPU, and have the OPU immediately perform the next operation in response. It is an object of the present invention to solve the above-mentioned drawbacks and to provide a new means for activating input/output commands from the CPU at expected timings during operation of the device.

In order to achieve the above object, the synchronization method according to the present invention includes a timing setting circuit that can be set externally or by a program,
The timing generating circuit includes a timing generating circuit that generates timing under conditions set in the timing setting circuit, a receiving circuit that is attached to a central processing unit and receives the output of the timing generating circuit, and a synchronization command processing circuit, The synchronous command processing circuit is characterized in that it stops processing the synchronous command until the receiving circuit receives the output of the timing generation circuit.

Next, a preferred embodiment of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. 3 in FIG. 1, one embodiment of the synchronization method according to the present invention is programmed to address the main memory (hereinafter referred to as MEM).
MFiM 'f address setting register lO and MKM address at the time of data transfer are MF
A main memory device MEM having an MEM address matching control circuit /3 that monitors whether the iM address setting register matches the contents of /θ and sends out an MFiM address matching signal when they match, and MF! M that holds the M address match signal
It is composed of a central processing unit (2) having an EM address match signal holding register J and an instruction processing circuit 2/(including a synchronous instruction processing circuit) for processing instructions. Note that the instruction processing circuit refers to the lower address match signal holding register, and if the MEM address match signal is reported, the instruction execution ends after resetting the signal, and if the signal is not reported, the instruction execution ends. Processes synchronization commands for functions that remain in a stopped state until

(3) Figure 1 shows the test flow of the device JO. The program is
Data transfer is executed between the device 30 and the main memory MIIIM, and at 9 o'clock, the M address corresponding to the timing to start the next input/output instruction to be started is set in the MEM address setting register IO ( 10θ and 101).

After activating the input/output command 1 (10 commands), the program 2 executes the following synchronous command (toy). Data transfer is performed between the device 30 and the main storage device 111IiM according to the input/output command l, and the main storage device Ml! ! When the access address of M is updated, the updated address matches the contents of the address setting register 10, so that j5. Ml! ! The M address match control circuit 15 reports the MFiM address match signal to the M11iM address match signal holding register. The synchronous instruction that was stopped waiting for the address match signal will not immediately finish executing, and the following input/output instruction will be started (
toy). That is, the synchronization command immediately preceding the input/output command absorbs the time required to reach the address, and when the timing is detected, the execution is completed in a very short time, so that the expected timing can be obtained.

(g) Although the present invention has been described in detail with respect to one preferred embodiment thereof, this is merely an example, and the present invention is not limited only by the embodiment described herein, and its scope is limited. It is easy to make various modifications and changes without deviation. For example, in the above embodiment, Ml! Although the timing is set using the M address, it is not necessary to limit it to the MKM address.

For example, when the device transitions to a certain state (data transfer start state, etc.), the device itself sends a timing signal to the OPU, and the
The PU may perform the following operations.

As explained above, the present invention provides a synchronization command in the CPU, and when apty executes the synchronization command, the OPU stops until a predetermined timing signal arrives, and when it receives the timing signal, it immediately starts the next operation. By executing this, the effect is that the timing can be easily determined.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 1 is a test flowchart of the present invention. 10...MEM address setting register, 15...M
IICM address-number control circuit, MEM address match signal holding register, instruction processing circuit Patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai

Claims (1)

[Claims] a timing setting circuit that can be set externally or by a program; a timing generation circuit that generates timing according to conditions set in the timing setting circuit; and a receiving circuit that is attached to a central processing unit and receives the output of the timing generation circuit. , and a synchronous command processing circuit, wherein the synchronous command processing circuit stops processing the synchronous command until the receiving circuit receives the output of the timing generation circuit.