JPS6114548B2 - - Google Patents

Info

Publication number
JPS6114548B2
JPS6114548B2 JP5764381A JP5764381A JPS6114548B2 JP S6114548 B2 JPS6114548 B2 JP S6114548B2 JP 5764381 A JP5764381 A JP 5764381A JP 5764381 A JP5764381 A JP 5764381A JP S6114548 B2 JPS6114548 B2 JP S6114548B2
Authority
JP
Japan
Prior art keywords
time
input
processing
interrupt
interrupt processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP5764381A
Other languages
Japanese (ja)
Other versions
JPS57172431A (en
Inventor
Yasuo Ogasawara
Saburo Sakagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5764381A priority Critical patent/JPS57172431A/en
Publication of JPS57172431A publication Critical patent/JPS57172431A/en
Publication of JPS6114548B2 publication Critical patent/JPS6114548B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked

Description

【発明の詳細な説明】 本発明はリンク割込方式、特に定周期に起動す
る周期的割込処理機能と、入出力装置から報告信
号を受信して起動する入出力割込処理機能とを具
備する中央制御装置におけるリンク割込方式に関
す。
DETAILED DESCRIPTION OF THE INVENTION The present invention has a link interrupt method, in particular, a periodic interrupt processing function that starts at regular intervals, and an input/output interrupt processing function that starts by receiving a report signal from an input/output device. This invention relates to a link interrupt method in a central control unit.

例えば電子交換機の中央制御装置においては、
発呼検出、ダイヤパルスの受信計数等は、定周期
(例えば4ミリ秒あるいはその整数倍)に起動さ
れる周期的割込処理機能により実行され、また入
出力装置が中央制御装置から指示された入出力動
作を終えたことを報告する報告信号を中央制御装
置に伝達すると、中央制御装置は入出力割込処理
機能を起動作して事後処理を実行する。
For example, in the central control unit of an electronic exchange,
Call detection, diamond pulse reception counting, etc. are performed by a periodic interrupt processing function that is activated at regular intervals (for example, 4 milliseconds or an integral multiple thereof), and input/output devices are instructed by the central controller. When a report signal reporting that the input/output operation has been completed is transmitted to the central controller, the central controller activates the input/output interrupt processing function and executes post-processing.

第1図はこの種中央制御装置における従来ある
割込方式の一例を示す図である。第1図におい
て、中央制御装置1に在るクロツクパルス発生回
路2は4ミリ秒の定周期でクロツク信号aを送出
して割込種別を示すフリツプフロツプ3をセツト
する。また入出力装置4が所定の入出力動作を終
えた時に報告信号bを送出すると、中央制御装置
1のフリツプフロツプ5がセツトされる。フリツ
プフロツプ3および5の何れかがセツトされる
と、割込部6が起動され、現在実行中の処理を中
断し、中断時に中央制御装置1内に在る図示され
ぬ各種レジスタ等に蓄積されているデータ類を記
憶装置に一時退避させる等の中断処理を実行し、
また割込分析処理によりフリツプフロツプ3およ
び5のセツト状態を調査する。フリツプフロツプ
3がセツト状態に在れば周期的割込処理部7を起
動し、発呼検出、ダイヤパルス受信計数等の処理
Aを実行する。若しフリツプフロツプ5がセツト
状態に在れば入出力割込処理部8を起動し、入出
力動作終了の事後処理Bを実行する。第2図は前
記処理過程の一例を示す図である。第2図におい
て、クロツク信号aは時点t1,t7およびt1
1に4ミリ秒周期で発生し、実行中の処理Cを中
断して処理Aを実行開始させる。該処理Aがそれ
ぞれ時点t2およびt8に終了すると、中断され
た処理Cを公知の方法により再開する。一方入出
力装置4からの報告信号bはクロツク信号aとは
全く同期せずに、時点t3(報告信号b1)、t
5(報告信号b2)およびt9(報告信号b3)
に到来し、やはり実行中の処理Cを中断して、対
応する処理B1,B2およびB3をそれぞれ実行
開始する。時点t4,t6およびt10に各処理
B1,B2およびB3が終了すると、中断された
処理Cを公知の方法により再開する。
FIG. 1 is a diagram showing an example of a conventional interrupt method in this type of central control unit. In FIG. 1, a clock pulse generating circuit 2 in a central control unit 1 sends out a clock signal a at a regular cycle of 4 milliseconds to set a flip-flop 3 indicating the type of interrupt. Further, when the input/output device 4 sends out a report signal b when it completes a predetermined input/output operation, the flip-flop 5 of the central control device 1 is set. When either of the flip-flops 3 and 5 is set, the interrupt section 6 is activated, interrupts the currently executing process, and interrupts the processing that is stored in various registers (not shown) in the central controller 1 at the time of interruption. Execute interruption processing such as temporarily saving the data stored in the storage device,
Also, the set states of flip-flops 3 and 5 are investigated by interrupt analysis processing. If the flip-flop 3 is in the set state, the periodic interrupt processing unit 7 is activated and processes A such as call detection and diamond pulse reception counting are executed. If the flip-flop 5 is in the set state, the input/output interrupt processing section 8 is activated and post-processing B for completing the input/output operation is executed. FIG. 2 is a diagram showing an example of the processing process. In FIG. 2, clock signal a is clocked at times t1, t7 and t1.
1 occurs at a 4-millisecond cycle, interrupting the process C that is being executed and causing the process A to start executing. When the processing A ends at times t2 and t8, respectively, the interrupted processing C is restarted by a known method. On the other hand, the report signal b from the input/output device 4 is not synchronized with the clock signal a at all, and occurs at time t3 (report signal b1), time t
5 (report signal b2) and t9 (report signal b3)
When the process C, which is also being executed, is interrupted, and the corresponding processes B1, B2, and B3 are started. When each process B1, B2, and B3 is completed at times t4, t6, and t10, the interrupted process C is restarted by a known method.

以上の説明から明らかな如く、従来ある割込方
式は、クロツク信号aまたは報告信号b(b1乃
至b3)が発生する度に現行処理Cを中断して、
所要の処理AまたはB(B1乃至B3)を割込ん
で実行する。現行処理Cを中断する度に中央制御
装置1は現状を記憶装置に退避させ、割込み実行
中の処理AまたはB(B1乃至B3)が完了する
と、中央制御装置1は記憶装置に退避させた状態
を復元させて処理Cを再開させる。従つて処理A
およびB(B1乃至B3)を割込み実行する都
度、中央制御装置1は処理Cに関する中断処理お
よび再開処理を実行せねばならず、処理能力を消
費させられることとなる。更に処理AおよびB
(B1乃至B3)が同時に要求された場合には、
割込み実行中の処理(例えばB1)に対しより優
先度の高い処理(例えばB2)が中断を要求する
状態も生じ、中断処理および再開処理は一層複雑
となる。
As is clear from the above explanation, the conventional interrupt method interrupts the current process C every time the clock signal a or the report signal b (b1 to b3) is generated.
A required process A or B (B1 to B3) is interrupted and executed. Every time the current process C is interrupted, the central control unit 1 saves the current state to the storage device, and when the interrupt execution process A or B (B1 to B3) is completed, the central control unit 1 saves the current state to the storage device. is restored and processing C is restarted. Therefore, processing A
and B (B1 to B3), the central control unit 1 must execute the interruption process and the restart process regarding process C, which consumes processing capacity. Further treatments A and B
If (B1 to B3) are requested at the same time,
A situation also arises in which a process (for example, B2) with a higher priority requests interruption of the process (for example, B1) that is currently being interrupted, making the interruption process and restart process even more complicated.

本発明の目的は、前述の如き従来ある割込方式
の欠点を除去し、割込みに伴う中断処理および再
開処理を単純化し、中央制御装置の処理能力の負
坦を軽減することにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional interrupt method as described above, to simplify the interrupt processing and restart processing associated with the interrupt, and to reduce the burden on the processing capacity of the central control unit.

この目的は、定周期に起動する周期的割込処理
機能と、入出力装置から随時伝達される報告信号
により起動する入出力割込処理機能とを具備する
中央制御装置において、前記中央制御装置が前記
周期的割込処理機能を起動する時点で、該時点以
前に前記入出力装置から受信している前記報告信
号に基づき前記入出力割込処理機能を起動可能と
することにより実現される。
This purpose is to provide a central control device that is equipped with a periodic interrupt processing function that starts at regular intervals and an input/output interrupt processing function that starts in response to a report signal transmitted from an input/output device at any time. This is achieved by enabling the input/output interrupt processing function to be activated based on the report signal received from the input/output device before the time when the periodic interrupt processing function is activated.

以下、本発明の一実施例を第3図および第4図
により説明する。第3図は本発明の一実施例によ
るリンク割込方式を示す図であり、第4図は第3
図における処理過程の一例を示す図である。第3
図において、第1図と異なる点は、入出力装置4
から送達される報告信号bが、ゲート9を経由し
て割込種別を示すフリツプフロツプ5に導びかれ
ることにある。該ゲート9は4ミリ秒の定周期で
発生するクロツク信号aによりセツトされるフリ
ツプフロツプ3の出力により導通状態となる。従
つて、入出力割込処理部8の起動要因となるフリ
ツプフロツプ5は、報告信号bの到来時期に直ち
にセツトされることは無く、周期的割込処理部7
の起動要因となるフリツプフロツプ3がセツトさ
れるのを待ち、セツトされることとなる。その結
果割込部6の起動時期は、フリツプフロツプ3の
セツト時期(4ミリ秒の定周期)に限定される。
該時期に起動された割込部6は現行処理C(第4
図)の中断処理および割込分析処理を実行し、フ
リツプフロツプ3と共にフリツプフロツプ5もセ
ツトされておれば、周期的割込処理部7により処
理Aを実行後、続いて入出力割込処理部8を起動
して処理Bを実行させ、然る後に中断された現行
処理Cの再開処理を実行する。次に第4図により
処理過程の一例を示す。先ず時点t1にクロツク
信号aが発生し、実行中の処理Cを中断して処理
Aを実行開始する。なお時点t1以前4ミリ秒の
間には動作終了した入出力装置は無かつたので、
処理Aが時点t2に終了すると、中断された処理
Cは直ちに再開される。時点t1から4ミリ秒後
の時点t7にクロツク信号aが発生するが、それ
迄に時点t3およびt5に入出力装置4からの報
告信号b1およびb2がそれぞれ到来するが、該
時点t3およびt5では現行処理Cは中断される
こと無く時点t7迄継続される。時点t7に現行
処理Cが中断されて処理Aが実行開始され、時点
t8に処理Aが終了すると、続いて報告信号b1
に対応する処理B1が実行開始され、時点t12
に処理B1が終了すると、更に報告信号b2に対
応する処理B2が継続実行される。時点t13に
処理B2が終了すると、時点t7以前4ミリ秒の
間に到来した報告信号b1およびb2に対応する
処理B1およびB2は総べて終了するので、中断
された処理Cが再開される。同様に、時点t7か
ら時点t11迄の4ミリ秒の間に到来した報告信
号b3(時点t9)に対応する処理B3は、時点
t11に現行処理Cを中断して実行された処理A
に続き、時点t14からt15迄に実行される。
An embodiment of the present invention will be described below with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing a link interrupt method according to an embodiment of the present invention, and FIG.
It is a figure which shows an example of the processing process in a figure. Third
In the figure, the difference from Figure 1 is that the input/output device 4
The report signal b sent from the floppy circuit is led via the gate 9 to the flip-flop 5 which indicates the type of interrupt. The gate 9 is made conductive by the output of the flip-flop 3, which is set by the clock signal a generated at a regular cycle of 4 milliseconds. Therefore, the flip-flop 5, which is the activation factor for the input/output interrupt processing section 8, is not set immediately at the time of arrival of the report signal b, but is activated by the periodic interrupt processing section 7.
It waits for the flip-flop 3, which is the activation factor, to be set, and then the flip-flop 3 is set. As a result, the activation timing of the interrupt section 6 is limited to the setting timing of the flip-flop 3 (4 millisecond constant cycle).
The interrupt unit 6 activated at that time executes the current process C (fourth process).
If the interrupt processing and interrupt analysis processing shown in the figure) are executed, and flip-flop 5 is set along with flip-flop 3, then after processing A is executed by periodic interrupt processing section 7, input/output interrupt processing section 8 is executed. It starts and executes process B, and then resumes the interrupted current process C. Next, FIG. 4 shows an example of the processing process. First, at time t1, a clock signal a is generated, interrupting the process C that is being executed and starting the process A. Note that no input/output device completed its operation during the 4 milliseconds before time t1, so
When process A ends at time t2, interrupted process C is immediately restarted. Clock signal a is generated at time t7, which is 4 milliseconds after time t1, but until then, report signals b1 and b2 from input/output device 4 arrive at time t3 and t5, respectively. Current processing C continues without interruption until time t7. At time t7, the current process C is interrupted and process A is started, and when process A ends at time t8, the report signal b1 is
Processing B1 corresponding to is started to be executed, and at time t12
When the process B1 ends, the process B2 corresponding to the report signal b2 is further executed. When processing B2 ends at time t13, processing B1 and B2 corresponding to report signals b1 and b2 that arrived during the 4 milliseconds before time t7 are all completed, so that interrupted processing C is restarted. Similarly, process B3 corresponding to report signal b3 (time t9) that arrived during 4 milliseconds from time t7 to time t11 is process A that is executed by interrupting current process C at time t11.
Subsequently, the process is executed from time t14 to t15.

以上の説明から明らかな如く、本実施例によれ
ば中央制御装置1はクロツク信号aの発生する周
期(4ミリ秒)に一度だけ、現行処理の中断処理
(時点t1,t7およびt11)および再開処理
(時点t2,t13およびt15)を実行するこ
とにより、処理Aのみならず処理B(B1乃至B
3)も総べて実行されることとなる。従つて、第
2図に示される従来ある割込方式に比べ、処理B
1,B2およびB3の実行に伴う中断処理および
再開処理が不要となる。
As is clear from the above explanation, according to the present embodiment, the central controller 1 suspends and restarts the current process (times t1, t7, and t11) only once every period (4 milliseconds) in which the clock signal a is generated. By executing the process (times t2, t13, and t15), not only process A but also process B (B1 to B
3) will also all be executed. Therefore, compared to the conventional interrupt method shown in FIG.
1, B2, and B3 become unnecessary.

なお、第3図および第4図はあく迄本発明の一
実施例に過ぎず、例えば報告信号bの到来状況は
図示されるものに限定されることは無く、他の任
意の状況で到来しても本発明の効果は変らない。
またクロツク信号aの発生周期は4ミリ秒に限定
されることは無く、他に幾多の周期が考慮される
が、何れの場合にも本発明の効果は変らない。更
に割込部6、周期的割込処理部7および入出力割
込処理部8はプログラムを併用して構成すること
も考慮されるが、かかる場合にも本発明の効果は
変らない。
It should be noted that FIGS. 3 and 4 are only one embodiment of the present invention, and for example, the arrival situation of the report signal b is not limited to that shown in the figure, and it may arrive in any other situation. However, the effect of the present invention remains unchanged.
Further, the generation cycle of the clock signal a is not limited to 4 milliseconds, and many other cycles may be considered, but the effects of the present invention remain the same in either case. Furthermore, it may be considered that the interrupt section 6, the periodic interrupt processing section 7, and the input/output interrupt processing section 8 are configured by using programs together, but the effects of the present invention do not change in such a case.

以上、本発明によれば、周期的割込処理機能と
入出力割込処理機能とを具備する中央制御装置に
おいて、前記割込処理のために現行処理を中断お
よび再開する頻度が、前記入出力割込処理に関係
なく周期的割込処理により定まり、前記中断処理
および再開処理による中央制御装置の負担が最小
限に維持され、また中断処理および再開処理も単
純化される。
As described above, according to the present invention, in a central control unit having a periodic interrupt processing function and an input/output interrupt processing function, the frequency of interrupting and restarting the current process for the interrupt processing is determined by the input/output interrupt processing function. This is determined by periodic interrupt processing regardless of the interrupt processing, and the burden on the central control unit due to the interruption processing and restart processing is kept to a minimum, and the interruption processing and restart processing are also simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来ある割込方式の一例を示す図、第
2図は第1図における処理過程の一例を示す図、
第3図は本発明の一実施例によるリンク割込方式
を示す図、第4図は第3図における処理過程の一
例を示す図である。 図において、1は中央制御装置、2はクロツク
発生回路、3および5はフリツプフロツプ、4は
入出力装置、6は割込部、7は周期的割込処理
部、8は入出力割込処理部、9はゲート、aはク
ロツク信号、b,b1,b2およびb3は報告信
号、A,BおよびCは処理、t1乃至t15は時
点、を示す。
FIG. 1 is a diagram showing an example of a conventional interrupt method, and FIG. 2 is a diagram showing an example of the processing process in FIG.
FIG. 3 is a diagram showing a link interrupt method according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of the processing process in FIG. 3. In the figure, 1 is a central control unit, 2 is a clock generation circuit, 3 and 5 are flip-flops, 4 is an input/output device, 6 is an interrupt section, 7 is a periodic interrupt processing section, and 8 is an input/output interrupt processing section. , 9 is a gate, a is a clock signal, b, b1, b2 and b3 are report signals, A, B and C are processing, and t1 to t15 are times.

Claims (1)

【特許請求の範囲】[Claims] 1 定周期に起動する周期的割込処理機能と、入
出力装置から随時伝達される報告信号により起動
する入出力割込処理機能とを具備する中央制御装
置において、前記中央制御装置が前記周期的割込
処理機能を起動する時点で、該時点以前に前記入
出力装置から受信している前記報告信号に基づき
前記入出力割込処理機能を起動可能とすることを
特徴とするリンク割込方式。
1. In a central control device comprising a periodic interrupt processing function activated at regular intervals and an input/output interrupt processing function activated by a report signal transmitted from an input/output device from time to time, the central control device A link interrupt method characterized in that, at the time of activating the interrupt processing function, the input/output interrupt processing function can be activated based on the report signal received from the input/output device before the time.
JP5764381A 1981-04-16 1981-04-16 Link interrupting system Granted JPS57172431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5764381A JPS57172431A (en) 1981-04-16 1981-04-16 Link interrupting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5764381A JPS57172431A (en) 1981-04-16 1981-04-16 Link interrupting system

Publications (2)

Publication Number Publication Date
JPS57172431A JPS57172431A (en) 1982-10-23
JPS6114548B2 true JPS6114548B2 (en) 1986-04-19

Family

ID=13061567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5764381A Granted JPS57172431A (en) 1981-04-16 1981-04-16 Link interrupting system

Country Status (1)

Country Link
JP (1) JPS57172431A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62249236A (en) * 1986-04-23 1987-10-30 Mitsubishi Electric Corp Program executing system for sampling controller
US4897727A (en) * 1988-05-09 1990-01-30 Thomson Consumer Electronics, Inc. Television tuning system allowing rapid response to user initiated commands

Also Published As

Publication number Publication date
JPS57172431A (en) 1982-10-23

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