JP2002215421A - Debugging device and breaking method for debugging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a debugging device capable of normally executing program debug even though the operation clock frequencies of microprocessors are different from each other, and a breaking method. SOLUTION: In this debugging device 1a provided with a plurality of microprocessors 10a and 20a which transmit and receive the data of a predetermined instruction through a shared temporary storing means 30a and in which an interrupting means 60a controls operation stop for debugging when a breakpoint detecting means 40a detects a breakpoint, the operation clock frequencies of the microprocessors 10a and 20a are different from each other, and the microprocessor 10a reads contents stored in the shared register 30a when the microprocessor 10a performs an instruction just before stop to be able to perform normal debugging because the microprocessor 20a writes predetermined desired data in the shared register 30a before the microprocessor 20a is stopped even though the microprocessor 20a is stopped for debugging.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for debugging a program mounted on a microcomputer, and more particularly to a method for breaking a program to be debugged on a plurality of processors when the operating clock frequency and the number of pipeline stages of the processors are different. The present invention relates to a debugging device in which the operation of an interrupt generation circuit for a break signal to be generated is improved.

[0002]

2. Description of the Related Art In recent years, control systems equipped with microprocessors have become multiprocessors. Information exchange among a plurality of processors is provided with a shared register, and each processor is most required to realize necessary functions. It has become necessary to increase the performance of the entire system by selecting a suitable processor.

[0003] For example, both signal processing calculation and control are required,
A system that needs to further reduce power consumption requires a low power consumption and has high computational performance.
SP (Digital Signal Process)
or) and a microcomputer for control to assemble a system that satisfies required performance and required functions.

In such a system, the clock frequency of the DSP is different from the clock frequency of the microcomputer, and the number of pipelines for executing instructions is also generally different.

[0005] An example of a program debugging apparatus for the above-described multiprocessor system is disclosed in Japanese Patent Application Laid-Open No. 6-75820. Referring to FIG. 5, which shows a configuration of an interrupt device in a multiprocessor system described in the publication in correspondence with the present invention, the interrupt device includes a first processor 11, a second processor 21, and a breaker connected to the processor 11. A first address monitoring device 43 including a point table 44; a second address monitoring device 53 connected to the processor 21 and including a breakpoint table 54;
First and second local memories 4 respectively occupied by 21
7 and 57, and an interrupt device 71 including a processor number mask 72.

This device is, for example, an address monitoring device 42
An address for breaking a program is stored in advance in the break point table 44 of the above, and the address monitoring device 42 compares the break address with the address output by the processor 11 via the signal line 141, and when they match, An interrupt signal is output to the interrupt device 61 via the interrupt signal line 143. Processor 2
1 and the address monitoring device 52 operate similarly.

The interrupt device 71 which has received the interrupt signal
If the processor preset in the processor number mask 72 is, for example, the processor 11, a break signal is output to the processor 11 via the interrupt signal line 145, and the operation of the processor 11 receiving the break signal is performed. Debug mode by stopping. If the processor set in advance is the processor 21, the processor 21 is set to the debug mode.

Therefore, a plurality of processors can perform register dump and memory dump necessary for program debugging after a break.

However, the above-mentioned conventional interrupt device is
Nothing is disclosed about the case where the clock frequencies of a plurality of processors are different from each other.

On the other hand, referring to FIG. 6 showing an outline of the configuration of another conventional debugging device, a shared register 31 shown by a dotted line in the figure between a first processor 12 and a second processor 22 is shown. Insert and connect to add
Processor 12 is 10 MHz, processor 22 is 50M
It operates at different clock frequencies, such as Hz.

The shared register 31 stores the first processor 1
The signal is transmitted to and from the second processor 22 via a signal line 157, and is transmitted to and from the second processor 22 via a signal line 158.

That is, in response to the shared register write command, the data of the second shared register signal 158 output from the second processor 22 is input and held. In addition, the stored data is transferred to the first processor 12 in response to the shared register read instruction.

Similarly, the first shared register signal 15 output from the first processor 12 in response to the shared register write command is also sent to the first processor 12.
7 is inputted and held. In addition, in response to the shared register read command, the stored data is transferred to the second processor 22.

In the above-described conventional example, a plurality of processors are simultaneously stopped at the time of a break. However, in an example having a shared register among a plurality of processors, the shared register 31 is used.
To prevent simultaneous access by multiple processors.

[0015]

As described above, in a conventional example in which a plurality of processors have a shared register and the clock frequencies of the processors are different from each other, the plurality of processors operate so as not to access the shared register at the same time. There is a problem that program debugging cannot be performed depending on the timing at which the processor is stopped for program debugging.

For example, referring to FIG. 7 showing a timing chart for explaining the operation of a conventional example having a shared register, first, in the case of an operation without stopping the processor, the second
After executing the K instruction, the processor 22 writes data to the shared register 31 through the second shared register signal line. Thereafter, the first processor 12 transmits the data written to the shared register 31 to the instruction execution stage (EX).
At the time of execution of the A instruction, the read instruction is input to the first shared register signal line and executed.

At the time of program debugging, when the first and second break signals 156 are simultaneously applied to a plurality of processors for program debugging, the second processor 22 has a higher clock frequency than the first processor 21. Therefore, the second processor 22 stops the fetch operation of the instruction I in the instruction fetch stage (IF) and stops until the execution of the instruction H by receiving the second break signal 156. . That is, the operation is stopped before the first processor 21.

When the first processor 12 reads and inputs data from the shared register 31 and executes the A instruction because the first processor 12 stops at the instruction H before the instruction K which is a data write instruction to the shared register 31, Since the processor 22 is stopped by the H instruction, the contents held in the shared register 31 are different from the contents when the processor is not stopped, so that the operation is also different and the program cannot be debugged. There is. It is obvious that the same problem as in the above-described example occurs even when the number of pipeline stages is different, and thus the description is omitted here.

An object of the present invention has been made in view of the above-mentioned disadvantages of the related art. Even when the clock frequency and the number of pipeline stages of the processor are different, the operation when the processor is not stopped, that is, the operation clock frequency is high. The operation of writing data to the shared register with a shared register write instruction to the processor and then reading the data from the shared register with a shared register read instruction to the processor with a lower operating clock frequency is a state in which the program is stopped for program debugging. An object of the present invention is to provide a debugging device that can execute normally even if there is any.

[0020]

According to the present invention, there is provided a debugging apparatus comprising: a plurality of microprocessors having different operating clock frequencies; shared temporary storage means shared among the plurality of microprocessors; and a break on the plurality of microprocessors A debugging device for debugging a program mounted on the plurality of microprocessors having an interrupting means, wherein the interrupting means transmits a break signal to the microprocessor having a low operation clock frequency to the microprocessor having a low operation clock frequency. Is output at the time of fetching the instruction to read the held data of the shared temporary storage means, and a command to read the held data by the microprocessor having the low operation clock frequency to output a break signal to the microprocessor having a high operation clock frequency. Characterized in that it comprises a break generating means for outputting delayed until line stage end.

Another feature of the debugging device of the present invention is that the data is transmitted / received by writing or reading data of a predetermined instruction via shared temporary storage means, and the breakpoint detection means detects a breakpoint. A debugging device comprising a plurality of microprocessors, the operation of which is stopped for debugging by interrupt means is controlled, wherein the plurality of microprocessors includes:
One of the operation clock frequencies is higher one is lower than the other, and the operation clock frequency is given to the shared temporary storage means after a break signal for stopping the operation is given to the microprocessor having the lower operation clock frequency. The predetermined means is written and held from the higher microprocessor, and the interrupt means performs a timing adjustment function for reading the held data by the lower microprocessor of the operation clock frequency immediately before the operation is stopped. Is to have.

Another feature of the debugging device of the present invention is that
One of a plurality of microprocessors for executing a predetermined debug program by pipeline processing executes a data write instruction in the shared temporary storage means in its own pipeline instruction execution stage, and the other microprocessor executes its own pipeline instruction execution stage. And the stop of the pipeline processing operation of the debug program is controlled by the break signal generated by the interrupt means in response to the break point detection signal detected by the break point detection means. The break control means and the break signal are previously sent to the other microprocessor having an operating clock frequency higher than the operating frequency of one of the plurality of microprocessors having different operating clock frequencies. It is to have a break adjustment means for providing delayed by time stipulated.

Further, the predetermined time may be an execution end time of a read instruction in one of the microprocessors in a pipeline instruction execution stage.

Further, the shared temporary storage means may be provided for program debugging of the microprocessor having different operation clock frequencies and different numbers of pipeline stages.

Still further, the predetermined time is such that the address match signal input to the first stage of the cascade-connected flip-flops for the number of pipeline stages of the one processor is synchronized with the operation clock signal of the one microprocessor. Thus, the time may be delayed by the number of pipeline stages.

The break adjusting means breaks the one microprocessor at the timing of generation of an address match signal corresponding to an address designated by each of the plurality of microprocessors having different operating clock frequencies, and breaks the other microprocessor. The microprocessor has a delay address coincidence signal obtained by delaying the generation timing of the address coincidence signal corresponding to the address designated by itself and the address coincidence signal corresponding to the address designated by the one microprocessor by a predetermined time by a delay circuit. Breaks at any of the occurrence timings.

Further, the break adjusting means breaks the one microprocessor at the timing of generating an address coincidence signal corresponding to an address designated by each of the plurality of microprocessors having different operating clock frequencies, and breaks the one microprocessor. The microprocessor has a delay address obtained by delaying the generation timing of the address match signal corresponding to the address specified by itself and the address match signal corresponding to the address specified by the one microprocessor by a predetermined time by a delay circuit. There is a configuration in which a break occurs at any of the coincidence signal generation timings.

[0028] A debug device of the present invention operates at a first operating clock frequency and stops operating for a predetermined period in response to a first break signal; and a higher frequency than the first microprocessor. A second microprocessor that operates at an operation clock frequency of and stops operating for a predetermined period in response to a second break signal;
A single shared storage means for temporarily storing data written by the microprocessor with the shared storage means write instruction, and holding the stored data until the first processor executes the shared storage means read instruction to read out the data; A first breakpoint table in which addresses of breakpoints of the first microprocessor are set in advance, and a set value of the first breakpoint table and an address signal set by the first microprocessor are input; And a first address monitoring device that outputs a first address match signal when they match,
Having a second breakpoint table in which addresses of breakpoints of the microprocessor are set, comparing a set value of the second breakpoint table with an address signal set by the second microprocessor, A second address monitoring device that outputs a second address match signal when they match, and a delay that delays the first address match signal until an instruction execution end time of an instruction execution stage in pipeline processing of the first microprocessor Means for receiving the output signal of the delay means and the second address coincidence signal to generate the second break signal, and the first and second address coincidence means. A second OR circuit for receiving the respective signals to generate the first break signal; , Characterized in that it comprises, respectively.

The interrupt means is cascaded to delay the first address match signal until an instruction execution end time of an instruction execution stage in pipeline processing of the first microprocessor. Has a plurality of flip-flops whose operating clock frequencies are supplied as synchronous clock signals, and the output signals of the final stage of the plurality of flip-flops and the second
A third OR circuit for generating the second break signal by inputting the first and second address match signals, respectively, and generating the first break signal by inputting the first and second address match signals, respectively. And fourth OR means for performing the above operation.

Further, the plurality of microprocessors or the first and second microprocessors have the same operation clock frequency, and have different numbers of pipeline stages.

The debugging method of the debugging device according to the present invention comprises:
One of a plurality of microprocessors for executing a predetermined debug program by pipeline processing executes a data write instruction in the shared temporary storage means in its own pipeline instruction execution stage, and the other microprocessor executes its own pipeline instruction execution stage. And the stop of the pipeline processing operation of the debug program is controlled by the break signal generated by the interrupt means in response to the break point detection signal detected by the break point detection means. In addition, the interrupt means sends the break signal to the other microprocessor having an operation clock frequency higher than the operation frequency of one of the plurality of microprocessors having different operation clock frequencies. The predetermined data is written to the shared storage means in the shared storage means before the other microprocessor stops, and the written data is written in the shared storage means. The data is maintained in the same data storage state for a certain period until the one microprocessor reads the data in the instruction execution stage.

Another feature of the break method of the debugging device of the present invention is that one of a plurality of microprocessors for executing a predetermined debug program in a pipeline process is shared and temporarily stored in its own pipeline instruction execution stage. Means for executing a data write instruction and the other executing a data read instruction in its own pipeline instruction execution stage, and a break generated by the interrupt means in response to a breakpoint detection signal detected by the breakpoint detection means. The signal controls the stop of the pipeline processing operation of the debug program, and the break adjusting means of the interrupt means sends the break signal to one of the microprocessors having different operating clock frequencies. With respect to the other microprocessors than the operating frequency of the processor with the operating clock frequency of the high frequency is to provide delayed by predetermined interval of time.

Further, the break adjusting means breaks the one microprocessor at the timing of generating an address coincidence signal corresponding to an address designated by each of the plurality of microprocessors having different operating clock frequencies, and breaks the one microprocessor. The microprocessor has a delay address match obtained by delaying the generation timing of the address match signal corresponding to the address specified by itself and the address match signal corresponding to the address specified by the one microprocessor by a predetermined time by delay means. A break can be set at any of the signal generation timings.

Another feature of the break method of the debugging apparatus according to the present invention is that a plurality of microprocessors having different operation clock frequencies or different numbers of instruction pipeline stages, a temporary storage means shared among the plurality of microprocessors, A method for debugging a program mounted on the plurality of processors with interrupt means for breaking a processor, wherein the break generation means of the interrupt means is provided for a microprocessor having a low operating clock frequency. A break signal is output at the time of the fetch of an instruction by which the microprocessor with a low operating clock frequency reads data held in the shared temporary storage means, and a break signal to a microprocessor with a high operating clock frequency is output.
The microprocessor having a low operation clock frequency outputs the held data with a delay until the end of an instruction execution stage for reading the held data.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the first embodiment of the debugging device of the present invention. In the following description, the reference numerals assigned to the signal lines are replaced with the reference numerals of the signal names. For example, a signal transmitted to the address signal line 101 is referred to as a first address signal 101. Also, the first and second microprocessors, the first and second address monitoring devices, the first and second breakpoint tables, the first and second OR gates, and the respective output signals are shown in FIG. "First" and "second"
Are omitted, and microprocessors are described as processors and are distinguished by reference numerals. For example, the first microprocessor is assumed to be a processor 10a.

Referring to FIG. 1, the debugging device 1a of the present invention has a first operation clock frequency, for example, 1
0 MHz, and a first break signal 106 to be described later.
, A first microprocessor 10a that stops operating for a predetermined period in response to the first microprocessor 10a, and operates at an operation clock frequency higher than that of the first microprocessor 10a, here, for example, at an operation clock frequency of 50 MHz, and responds to a second break signal 107 described later. Microprocessor 2 that stops operating for a predetermined period of time
0a.

In the debug device 1a, the second microprocessor 20a sends a command to write to the shared temporary storage means (hereinafter, referred to as a write command).
The data (second shared register signal) 109 written by the shared register write instruction is temporarily stored, and the first microprocessor 10a stores the stored data in a shared temporary storage unit read instruction (hereinafter referred to as a shared register read instruction). ), And holds the data until the data is read out as data (first shared register signal) 108.
0a.

The debugging device 1a has a first breakpoint table 41 in which addresses of breakpoints of the first microprocessor 10a are set in advance, and the set value of the first breakpoint table 41 and the first breakpoint table 41 are stored. It has a first address monitoring device 40a that inputs and compares the address value of the first address signal 101 set by the microprocessor 10a and outputs a first address match signal 103 when they match.

The debug device 1a has a second breakpoint table 51 in which the address value of the first address signal 102 of the breakpoint of the second microprocessor 20a is set in advance. 51 setting value and the second microprocessor 2
0a is compared with the set address value of the address signal 102, and a second address monitoring device 50a that outputs a second address match signal 104 when they match.

The debugging device 1a has delay means (delay circuit) 61 for delaying the first address match signal 103 until the instruction execution end time of the instruction execution stage in the pipeline processing of the first microprocessor 10a.
A first OR circuit (hereinafter referred to as an OR gate) 62 for receiving the output signal 105 of the delay circuit 61 and the second address coincidence signal 104 to generate a second break signal 107 and an address coincidence signal 103, respectively. And a second OR gate 63 for receiving a first break signal 106 and a second break signal 106, respectively.
(Interrupt means).

Next, the operation of this embodiment will be described. Referring to FIG. 1 described above and FIG. 2 showing a timing chart for explaining the operation of the present embodiment, first, the debug device 1a starts operation and the programs to be debugged are sequentially executed. When the program proceeds to an address predetermined for debugging, the address signal 101 output from the first microprocessor 10a matches the address preset in the first breakpoint table 41, and the first address Assuming that the coincidence signal 103 has been output, the operation at that time will be described.

It is assumed that the address "A" is set in the first breakpoint table 41. When the first microprocessor 10a outputs the address “A” as the address signal 101, the first microprocessor 10a
a outputs a first address match signal 103 when it matches an address “A” preset in the first breakpoint table 41.

The second OR gate 63 in the interrupt device 60a receives the first address coincidence signal 103 at the logical level "1". At this time, the second address match signal 104 is inactive and at the logical level “0”, so that the second OR gate 63 outputs the first break signal 106
And outputs it to the first processor 10a.

The first processor 10a stops the fetish operation of the “B” instruction fetch stage (IF) by inputting the first break signal 106, and also “A”
After executing the instruction decode stage (ID) and the "A" instruction execution, the operation of the instruction execution stage (EX) is stopped.

Delay circuit 61 in interrupt device 60a
The first processor 10a outputs at least the second shared register signal 109 of the second processor 20a from the time when the first address match signal 103 is input.
An address coincidence signal 105, which is a signal delayed by T1 until the execution of the “A” instruction, is output to the first OR gate 62.

The first OR gate 62 outputs a first break signal 107 to the second processor 20a. Second
Receives the first break signal 107, stops the operation of the “S” instruction fetch stage (IF), and executes the “R” instruction decode stage (ID) and the “R” instruction execution stage (EX) After performing the processing up to, the execution of the instruction is stopped. By delaying the break signal of the second microprocessor 20a having an operation clock frequency higher than that of the first microprocessor 10a by "T1" time, the second microprocessor 20a continues its operation, and the second microprocessor 20a As a result, the data write instruction “K” is executed for the shared register 30a.

After data is written to the shared register 30a by the second microprocessor 20a, the first processor 10a whose operating clock frequency is lower than that of the second microprocessor 20a is transmitted from the shared register 30a to the second microprocessor. A data read instruction “A” for reading data written by the processor 20a is executed.

By executing the data read instruction "A", the data written by the second processor 20a is transferred to the first microprocessor 10a.

To summarize the break method in the above-described debug device 1a, one of the microprocessors 10a and 20a that executes a predetermined debug program by pipeline processing is shared by its own pipeline instruction execution stage. A data write instruction is executed to the register 30a, and the other microprocessor 10a executes an instruction to read data written from the microprocessor 20a in its own pipeline instruction execution stage.

In response to a breakpoint detection signal (address coincidence signal) 103 detected by the address monitoring device 40a as a breakpoint detection means, the interrupt device 6
The break signal 106 generated at 0a controls the stop of the pipeline processing operation of the debug program of the microprocessor 10a.

Subsequently, the delay circuit 61 as a break adjusting means of the interrupt device 60a converts the address coincidence signal 103 to the microprocessor 20a having an operation clock frequency higher than the operation frequency of the microprocessor 10a having a different operation clock frequency. Against
Predetermined time (determined by delay amount of delay circuit 61)
The delay is given as a break signal 106.

The break timing adjustment by the break adjusting means 61 is performed by setting a break to one of the microprocessors 10a at the generation timing of the address coincidence signals 103 and 104 corresponding to the addresses designated by the plurality of microprocessors 10a and 20a having different operation clock frequencies. The other microprocessor 20a receives the generation timing of the address coincidence signal 104 corresponding to the address signal 102 specified by itself and the address coincidence signal 103 corresponding to the address signal 101 specified by one microprocessor 10a as a delay circuit. At 61, a break is set at one of the generation timings of the delayed address coincidence signal 105 delayed by a predetermined time.

That is, the break generating means 61, 62, 63 of the interrupt device 60a outputs the break signal 1 to the microprocessor 10a having a low operation clock frequency.
06 is output at the time of the instruction fetch of the instruction "A" for reading the data held in the shared register 30a of the microprocessor 10a having the low operation clock frequency, and the break signal 107 to the microprocessor 20a having the high operation clock frequency is output. Is delayed until the end of the instruction execution stage (EX) for reading the data held in the shared register 30a.

As described above, even if the microprocessors 10a and 20a are stopped for program debugging, the conventional problem described in the section of the problem to be solved by the present invention, that is, the shared register between a plurality of processors, In the conventional example in which the clock frequencies of the processors are different from each other, the plurality of processors operate so as not to access the shared register at the same time. However, depending on the timing at which the processor is stopped for program debugging, program debugging cannot be performed. The problem will not occur.

As described above, even if the microprocessors 10a and 20a having different operation clock frequencies are stopped for program debugging, predetermined data is stored in the shared register in the microprocessor 20a.
a is written and held by the microprocessor 20a before the stop of the multiprocessor a, the microprocessor 10a can read the held contents at the time of executing the instruction immediately before the stop and perform normal debugging. Contributes to improved efficiency.

Next, a second embodiment of the present invention will be described.

The difference from the first embodiment is that the delay circuit 61 in the interrupt device 60a in the first embodiment is different from the first embodiment.
Is further devised. That is, referring to FIG. 3 which shows a block diagram of the configuration of the second embodiment, the interrupt device 60b transmits the first address match signal 123 to the instruction execution stage (EX) in the pipeline processing of the first microprocessor 10b. ), A plurality of flip-flops 66 connected in cascade to delay the instruction execution end time and supplied with the operation clock frequency 10 MHz of the first microprocessor 10 b as a synchronous clock signal.
~ 68. Further, the interrupt device 60a receives the output signal of the final stage 68 of the plurality of flip-flops 66 to 68 and the second address coincidence signal 124, and
OR gate 64 that generates break signal 129 of
And a fourth OR for inputting address match signals 123 and 124 to generate a first break signal 128, respectively.
And a gate 65.

The above-described configuration is equivalent to the second break signal 12
9 instead of delaying the first address match signal 124 input to the third OR gate 64 until the execution of the instruction "A" of the first microprocessor 10a is completed by the delay circuit 61 in FIG. The first address coincidence signal 123 is set to the internal clock signal of the operation clock frequency of 10 MHz of the first microprocessor 10b as a synchronous clock by the flip-flops 66 to 68 corresponding to the number of pipeline stages of the first microprocessor 10b. By delaying the address match signal 123 by the number of pipeline stages of the first microprocessor 10b,
To the first OR gate 64 described above.
The same operation and effect as those of the embodiment can be obtained.

Next, the operation of this embodiment will be described.

Referring to FIG. 3 and FIG. 4 showing a timing chart for explaining the operation of the present embodiment, similarly to the first embodiment, first, the debugging device 1b starts the operation, and When the program is sequentially executed to advance to a predetermined address for debugging, the first address signal 121 output from the first microprocessor 10b matches the address of the first breakpoint table 42, First address match signal 1
23 is output, and the operation at that time will be described.

It is assumed that the address "A" is set in the first breakpoint table 42. When the first microprocessor 10b outputs the address “A” as the address signal 121, the first microprocessor 10b
b outputs a first address match signal 123 when it matches the address “A” set in the first breakpoint table 42 in advance.

The fourth OR gate 65 in the interrupt device 60b receives the first address coincidence signal 123 at the logical level "1". At this time, since the fourth address match signal 124 is inactive and at the logical level “0”, the third OR gate 65 outputs the first break signal 128
And outputs it to the first processor 10b.

The first processor 10b stops the "B" instruction fetch by inputting the first break signal 128, and executes the "A" instruction decode and the "A" instruction execution stage (EX). And stop executing the instruction.

When the first address match signal 123 is input to the D terminal of the flip-flop 66, the flip-flop 66 performs address match in synchronization with the rising timing of the internal clock signal 10 MHz input from the first processor 10b. The signal 125 is output from the output terminal Q.

Similarly, the flip-flop 67 outputs the first address coincidence signal 1 output from the flip-flop 66.
25, an address match signal 126 is output from the output terminal Q in synchronization with the next rising timing of the internal clock signal 10 MHz, and the flip-flop 68 outputs the address match signal 126 output from the flip-flop 67 to the internal clock signal 10 MHz. The address match signal 127 is output from the output terminal Q to one input terminal of the third OR gate 64 in synchronization with the next rising timing.

That is, the first address match signal 123
Are sequentially shifted by flip-flops 66 to 68,
In the third OR gate 64 receiving the shifted first address match signal 127, the second address match signal 124, which is the other input, is "0". The signal 127 is output to the second microprocessor 20b as the second break signal 129.

That is, since the first address coincidence signal 123 is shifted to the third clock after it is generated, it corresponds to a delay of three stages of the pipeline.

By inputting the second break signal 129, the second processor 20b executes the instruction fetch up to the "R" instruction and suspends the subsequent "S" instruction fetch.

The fetched "R" instruction proceeds to the next instruction decode stage (ID). After being decoded, the instruction is executed in the next instruction execution stage (EX). Processor 20b stops operating.

The second microprocessor 20 having an operation clock frequency higher than that of the first microprocessor 10b
b of the first microprocessor 1
By delaying the processing time of three stages of pipeline 0b, the second microprocessor 20b continues the operation,
The data write instruction “K” is executed on the shared register 30b by the second microprocessor 20b.

After data is written to the shared register 30b by the second microprocessor 20b, the first processor 10b whose operating clock frequency is lower than that of the second microprocessor 20b is sent from the shared register 30b to the second microprocessor 20b. A data read instruction “A” for reading data written by the processor 20b can be executed.

By executing the data read instruction "A", the data written by the second processor 20b is passed to the first microprocessor 10b.

Therefore, in the second embodiment, as in the first embodiment, even if the microprocessors 10b and 20b are stopped for program debugging, the conventional problem, that is, the shared problem among a plurality of processors. If the processor has a register and the clock frequencies of the processors are different from each other, the plurality of processors operate so as not to access the shared register at the same time, but depending on the timing of stopping the processor for program debugging,
The problem that program debugging cannot be performed does not occur. Even if the microprocessors 10b and 20b having different operating clock frequencies are stopped for program debugging, predetermined data is stored in the shared register in the microprocessor 20b.
Is written and held by the microprocessor 20b before the operation is stopped, the microprocessor 10b can read the held contents at the time of executing the instruction immediately before the operation is stopped, and perform normal debugging. Contribute to improvement.

Although the present invention has been described with reference to the embodiment between two processors, a plurality of microprocessors may be provided with the configuration of the present embodiment between two processors among the plurality of microprocessors. It is apparent that the processor is not limited to the above embodiments, and that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.

[0076]

As described above, according to the present invention, the generation of a break signal to a microprocessor having a high clock frequency is delayed by the delay means until the instruction execution of the microprocessor having a low operation clock frequency is completed. Writing data to a register is performed in the same way as writing a shared register write instruction of a microprocessor with a high clock frequency and then reading with a shared register read instruction of a low clock frequency when the microprocessor is not stopped. Processor, the operating clock frequency is high,
As described in the problem described in the section of the problem to solve the problem, it is possible to provide a debugging device and a break method of a multi-processor mounted program that has solved the problem caused by stopping a plurality of microprocessors,
It contributes to improving the efficiency of debugging work.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment.

FIG. 5 is a block diagram showing a configuration of a conventional interrupt device according to the present invention.

FIG. 6 is a block diagram showing a configuration of another conventional debugging device.

FIG. 7 is a timing chart for explaining the operation of an example of another conventional debugging device.

[Explanation of symbols]

 1a, 1b Debugging device 10a, 10b First microprocessor 20a, 20b Second microprocessor 30a, 30b, 31 Shared register 40a, 40b, 43 First address monitoring device 41, 42 First breakpoint table 47, 57 local memory 51,52 second breakpoint table 50a, 53 second address monitoring device 60a, 60b, 71 interrupt device 61 delay circuit 62,63,64,65 OR gate 66,67,68 flip-flop 106,128 First break signal 107,129 Second break signal 108,157 First shared register signal 109,158 Second shared register signal 101,121 First address signal 102 Second address signal 103,123 First Address of Coincidence signal 104 and 124 the second address coincidence signal

Claims (14)

[Claims] A plurality of microprocessors each having a different operation clock frequency; shared temporary storage means shared between the plurality of microprocessors; and interrupt means for breaking the plurality of microprocessors. In the debugging device for debugging a program mounted on a microprocessor, the interrupt unit reads a break signal to a microprocessor having a low operation clock frequency, and the microprocessor having a low operation clock frequency reads data held in the shared temporary storage unit. Output at the time of fetching an instruction, and output a break signal to a microprocessor with a high operation clock frequency delayed until the instruction execution stage at which the microprocessor with a low operation clock frequency reads the held data ends. A debugging device comprising a break generating means. 2. The method according to claim 1, further comprising: writing or reading data of a predetermined instruction via the shared temporary storage means to transfer the data, and when the breakpoint detection means detects a breakpoint, the interruption means performs debugging. A debugging device comprising a plurality of microprocessors, the operation of which is controlled to be stopped, wherein the plurality of microprocessors have one operation clock frequency higher than the other and lower than the other, and the operation clock frequency is lower. After a break signal for stopping the operation is given, predetermined data is written and retained in the shared temporary storage means from the microprocessor having the higher operation clock frequency, and the retained data is transferred to the shared temporary storage means. Immediately before, the lower clock of the operating clock frequency A debug device, wherein the interrupt unit has a timing adjustment function for reading by an microprocessor. 3. A microprocessor which executes a predetermined debug program by pipeline processing, wherein one microprocessor executes a data write instruction in the shared temporary storage means in its own pipeline instruction execution stage, and the other microprocessor executes its own. In the pipeline instruction execution stage, the data read instruction is executed, and the break signal generated by the interrupt means in response to the break point detection signal detected by the break point detection means is used to execute the pipeline processing operation of the debug program. Break control means for controlling stoppage, and the other microprocessor having an operating clock frequency higher than the operating frequency of one of the plurality of microprocessors having the different operating clock frequencies. And a break adjusting means for delaying the delay by a predetermined time. 4. The debugging device according to claim 4, wherein the predetermined time is an execution end time of the read instruction in the pipeline instruction execution stage by the one microprocessor. 5. The debugging device according to claim 1, wherein said shared temporary storage means is provided for program debugging of said microprocessors having different operation clock frequencies or different numbers of pipeline stages. 6. The predetermined time is such that the address match signal input to the first stage of the cascade-connected flip-flops for the number of pipeline stages of the one processor is synchronized with the operation clock signal of the one microprocessor. 5. A time delayed by the number of pipeline stages.
Debug device as described. 7. The break adjusting means breaks the one microprocessor at a timing of generation of an address match signal corresponding to an address designated by each of the plurality of microprocessors having different operating clock frequencies, and breaks the one microprocessor. The microprocessor has a delay address match in which the generation timing of the address match signal corresponding to the address specified by itself and the address match signal corresponding to the address specified by the one microprocessor are delayed by a predetermined time by a delay circuit. 7. The debugging device according to claim 6, wherein a break is provided at any of signal generation timings. 8. A first operation which operates at a first operation clock frequency and stops operation for a predetermined period in response to a first break signal.
A second microprocessor that operates at an operation clock frequency higher than the first microprocessor and stops operating for a predetermined period in response to a second break signal; and A single shared storage unit for temporarily storing data written by the shared storage unit write instruction and holding the stored data until the first processor executes the shared storage unit read instruction to read the stored data; A first breakpoint table in which addresses of breakpoints of the microprocessor are set, and a setting value of the first breakpoint table is compared with an address signal set by the first microprocessor; A first address monitoring device that outputs a first address match signal when they match. A second breakpoint table in which addresses of breakpoints of the second microprocessor are set in advance; and a set value of the second breakpoint table, an address signal set by the second microprocessor, A second address monitoring device that outputs a second address match signal when they match, and an instruction execution end of an instruction execution stage in a pipeline process of the first microprocessor that outputs the first address match signal to the first microprocessor. First OR means for inputting the output signal of the delay means and the second address match signal to generate the second break signal, and the first and the second And a second OR circuit for receiving the two address match signals and generating the first break signal. Debugging apparatus comprising: an interrupt unit, respectively. 9. The first microprocessor according to claim 1, wherein the interrupt means is cascaded to delay the first address match signal until an instruction execution end time of an instruction execution stage in pipeline processing of the first microprocessor. Having a plurality of flip-flops whose operation clock frequencies are supplied as synchronous clock signals, and receiving the output signal of the last stage of the plurality of flip-flops and the second address match signal, respectively, and A third OR circuit for generating a signal and the first and second address coincidence signals, respectively, and
9. The debugging device according to claim 8, further comprising: fourth OR means for generating a break signal of the following. 10. The debugging device according to claim 1, wherein the plurality of microprocessors or the first and second microprocessors have the same operating clock frequency, and have different numbers of pipeline stages. . 11. A microprocessor which executes a predetermined debug program by pipeline processing, one of the microprocessors executes a data write instruction to the shared temporary storage means in its own pipeline instruction execution stage, and the other microprocessor executes its own. Executing a data read instruction in a pipeline instruction execution stage;
The break signal generated by the interrupt means in response to the break point detection signal detected by the break point detection means controls the stop of the pipeline processing operation of the debug program, and the interrupt means outputs the break signal. The shared temporary storage is provided by delaying a predetermined time to another microprocessor having an operation clock frequency higher than the operation frequency of one of the plurality of microprocessors having different operation clock frequencies. In the means, predetermined data is written before the other microprocessor stops, and the written data is kept in the same data storage state for a certain period of time until the one microprocessor reads in the instruction execution stage. Keep it Break method for debugging and wherein the. 12. A microprocessor which executes a predetermined debug program by pipeline processing, one of the microprocessors executes a data write instruction to the shared temporary storage means in its own pipeline instruction execution stage, and the other microprocessor executes its own. Executing a data read instruction at a pipeline instruction execution stage;
The break signal generated by the interrupt means in response to the break point detection signal detected by the break point detection means controls the stop of the pipeline processing operation of the debug program, and the break adjustment means of the interrupt means Providing the break signal to the other microprocessor having an operation clock frequency higher than the operation frequency of one of the plurality of microprocessors having different operation clock frequencies with a delay of a predetermined time. A method for breaking a debugging device. 13. The break adjusting means breaks the one microprocessor at a timing of generation of an address coincidence signal corresponding to an address designated by each of the plurality of microprocessors having different operating clock frequencies, and breaks the one microprocessor. The microprocessor has a delay address match obtained by delaying the generation timing of the address match signal corresponding to the address specified by itself and the address match signal corresponding to the address specified by the one microprocessor by a predetermined time by delay means. 13. The method according to claim 12, wherein a break is set at any of the signal generation timings. 14. A system comprising: a plurality of microprocessors having different operation clock frequencies or different numbers of instruction pipeline stages; a temporary storage means shared among the plurality of microprocessors; and an interrupt means for breaking the plurality of microprocessors. In the debugging method of a debugging device for debugging a program mounted on a plurality of processors, the break generating means of the interrupt means outputs a break signal to the microprocessor having a low operation clock frequency to the microprocessor having a low operation clock frequency. Outputs a break signal to a microprocessor having a high operation clock frequency when a command for reading the data stored in the temporary storage means is fetched, and a microprocessor having a low operation clock frequency reads the stored data. A break method for a debug device, wherein the output is delayed until the end of an instruction execution stage to be embedded.