JPS61165138A - Interruption controlling system - Google Patents

Abstract

PURPOSE:To improve the operation efficiency of a CPU by limiting an inhibition of executing an instruction, and an inhibition of an interruption, to only an actually necessary range, when changing a mask with respect to an input/output interruption. CONSTITUTION:A mask release detecting part 22 detects whether that which is changed to '1' from '0' exists or not in a mask, and executes a counting operation by setting a counter 24, if any. During this time, an interlock generating part 25 discriminates a kind of the next instruction 26, and if it is a mask changing instruction, it is delayed and prevented from being changed to '0' from '1'. A mask set detecting part 23 detects whether that which is changed to '0' from '1' exists or not in the mask, operates a counter 28, if any, turns on an interruption inhibiting signal 29, and as for an interrupting signal of an interruption receiving register 31, is input to an interruption processing part 33 is inhibited by a gate 32.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control method for input/output interrupts in a central processing unit of an information processing system.

As an example of a configuration method for a relatively large-scale information processing system, as illustrated in FIG. Equipment (M S t
J) 3 is connected to a system control unit (hereinafter referred to as MCU) 4.

Here, the MCU 4 controls the access of the CPUI and the CHP 2 to the main storage device 3, and intensively processes the transfer of control information between the C'PUI and the CHP 2, the transfer of input/output interrupt signals, and the like.

In such a configuration, there are problems caused by concentrating control on the MCU 4, and mask control of input/output interrupts is one of them.

[Conventional technology]

In order to process the transfer of input/output interrupt signals, the MCU 4 receives interrupt mask information from each CPU 1, and among the input/output interrupt signals generated by the CHF 2, refers to the mask information and others to select only the signals that should be enabled. Applicable CPUI
It is transferred as an input/output interrupt signal.

As is well known, the input/output interrupt mask is, for example, CHF2.
CPUI from each channel for each channel connected to
For example, mask information for each CPUI is information that specifies whether input/output interrupts are allowed or not (i.e., Mask release status/
setting status).

The CPUI sets/cancels this mask information by executing a specific instruction. Generally, there are a plurality of types of commands having such an effect, but in the following, they will be collectively referred to as mask change commands.

When a mask change instruction is executed by the CPU, mask information held in a control register or the like in the CPU is set to a new value, and the mask information is transferred to the MCU 4, and actual mask control is performed within the MCU 4.

In such control, after the CPU sends new mask information to the MCU 4, the MCU 4 receives the mask information and returns a new input/output interrupt signal controlled by it, and the CPU receives the interrupt signal. It may take about 10 control cycles (hereinafter simply referred to as cycles) determined by the system.

Therefore, when executing a mask change instruction, if the mask information specified by the instruction is retained in the interrupt control mechanism, the execution of the mask change instruction is completed, but from then on, the interrupt control mechanism independently Information sequentially sent to MCU
4, and interrupts are not accepted until a new interrupt signal arrives.

In such a configuration, if there are consecutive mask change instructions in a program, when the next mask change instruction is executed after the previous mask change instruction is completed, the mask by the second mask change instruction is The state in which no interrupts are accepted continues until the information has been changed.

As a result, there is a possibility that the mask information of the MCU 4 changes to the information specified by the second instruction before there is a period for accepting an interrupt signal according to the mask information by the first instruction.

To prevent such a situation from occurring, for example, as shown in FIG. 3, when a mask change instruction 10 is executed, the start of execution of subsequent instructions is unconditionally delayed by a period of time shown as a dummy cycle 11.

This delay time is such that when the subsequent instruction 12 is a mask change instruction, the mask information write timing (indicated as W in the figure) 13 to the interrupt control mechanism is after the end of the mask information transfer period 14 by the interrupt control mechanism. Make it.

Figure 3 shows the progress of processing when instruction execution is based on so-called vibe line control. Fetching of instructions is being performed.

In addition, if there is no dummy cycle 11 and there is no dummy cycle 11, in a normal instruction execution state, the D cycle of the next instruction is
The cycle is executed, but the dummy cycle 11 is inserted by inhibiting the progress of the cycle by applying a so-called ink clock to the pipeline.

[Problem that the invention seeks to solve]

According to the above control method, there are the following problems.

(a) A mask change instruction causes execution of all subsequent instructions to be delayed until the interrupt signal due to the new mask is determined.

(bl Even if the next command is a mask change command, if the only change in the mask caused by the previous mask change command is a change to the setting state (change the mask from 1 to 0), the next command will change the mask. Even if the mask is changed from 0 to 1, there is no problem in processing, but the execution of subsequent instructions is delayed even in that case.

[Means for solving problems]

The above problem is that the system control unit masks input/output interrupt signals issued by the channel control unit to the central processing unit according to interrupt mask information issued by the central processing unit, and transfers the signals to the central processing unit. When the central processing unit of the information processing system configured as follows executes a mask change command to change the mask information,
means for identifying a change in the mask information due to the mask change command to be executed, and delaying execution of a subsequent mask change command for a predetermined time when detecting that there is mask information changing from a set state to a released state; The problem is solved by the interrupt control method of the present invention, which has means for suppressing reception of the input/output interrupt signal for a predetermined period of time when it is detected that there is mask information that changes from the canceled state to the set state.

[Effect]

In other words, the change in mask information is identified from the contents specified in the mask change command and the current mask information, and control is performed accordingly. If there is, the mask is reset (from 1 to 0) while the change does not take effect.
), the start of execution of subsequent mask change instructions is delayed for the required time.

Also, if there is a change in the mask setting state (from 1 to 0), the new mask information is referenced by the MCU 4, and reception of the interrupt signal is inhibited for a certain period of time required until the correct interrupt signal arrives after the change. to prevent interrupts from occurring.

However, no control is performed to delay subsequent instructions due to the latter.

If there is a change in both masks, both of the above controls are performed in parallel.

As described above, the above problem is solved, and it is possible to avoid unnecessarily delaying subsequent instructions or inhibiting interrupts.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention in a CPUI interrupt control mechanism.

By executing the mask change instruction, new mask information transferred by the control vA20 is set in the mask register 21 in the W cycle.

The mask information set in the mask register 21 is sequentially sent to the MCU 4 via the mask sending register 30.

Prior to setting in the mask register 21, the new mask information on the control line 20 and the current mask information on the mask register 21 are compared by a mask release detection section 22 and a mask setting detection section 23.

The mask release detection unit 22 checks whether there is any mask that is changed from O to 1, and if there is a corresponding mask, sets a count value in the counter 24 and starts a counting operation.

This count value is normally the number of control cycles necessary to delay the start of execution of the next mask change instruction so as to obtain an effect corresponding to dummy cycle 11 in FIG. 'aVA 34 allows different lengths of count values to be set depending on the type of mask change command sent from the instruction execution control unit of the CPUI.

The counter 24 decrements the set count value by 1 every control cycle, and when the count value reaches O, the counting operation ends.

While the counter 24 is operating, the ink generator 25 identifies the type of the next instruction using the control line 26, and if it is a mask change instruction, the count value of the counter 24 is incremented to delay the start of execution. is not O during the period ink clock signal 27
raise.

The instruction execution control section of the CPU delays execution of the next mask change instruction and the instructions subsequent thereto until the ink clock signal 27 is turned off.

The mask setting detection unit 23 checks whether there is any mask to be changed from 1 to O, and if there is a corresponding mask, it sets the count value to the counter 28 and starts the counting operation. do.

This count value is calculated by transferring the mask information to the MCU4, which is executed in parallel, so that the interrupt signal in the new state is
The number of control cycles (in the case of the above example, 10 cycles or more) corresponds to a time not smaller than the time required for the interrupt to be sent back from the CU 4 and received by the interrupt reception register 31.

The counter 28 decreases the count value by 1 in every control cycle, and when the count value reaches O, the counting operation ends.

Since the counter 2B turns on the interrupt inhibit signal 29 while the count value is not 0, the interrupt reception register 3
The 10 interrupt signal is inhibited from being input to the interrupt processing circuit 33 by the gate 32.

Thereby, when the mask is changed from the canceled state to the set state, it is possible to prevent an interrupt from occurring due to an interrupt signal controlled by the previous mask information.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when changing the mask for input/output interrupts, inhibition of instruction execution and prohibition of interrupts are limited only to the truly necessary range, so that the central processing unit, etc. There is a significant industrial effect of improving operating efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a configuration diagram of an information processing system, and FIG. 3 is an explanatory diagram of a conventional control sequence. In the figure, 1 is the CPU and 2 is the CHP. 3 is MSU, 4 is MCU. 21 is a mask register, 22 is a mask release detection unit, 2
3 is a mask release detection section, 24 and 28 are counters, 25 is an ink clock generation section, 30 is a mask sending register, 31 is an interrupt reception register, and 33 is an interrupt processing section.

Claims (1)

[Claims] Information configured such that the system control unit masks an input/output interrupt signal issued by the channel control unit to the central processing unit according to interrupt mask information issued by the central processing unit, and transfers the masked signal to the central processing unit. When the central processing unit of the processing system executes a mask change command for changing the mask information, the mask information identifies a change in the mask information due to the executed mask change command, and changes the mask information from a set state to a canceled state. means for delaying the execution of a subsequent mask change command for a predetermined period of time when it is detected that there is mask information that changes from the release state to the set state; An interrupt control method characterized by having means for inhibiting reception for a predetermined period of time.