JPS6050070B2 - Manufacturing method of MOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a short channel MOS type semiconductor device having an extremely short effective channel length.

One effective way to increase the speed of operation of a MOS field effect transistor (hereinafter abbreviated as MOSFET) is to increase the mutual conductance by shortening the channel length. The conventional method of determining channel length based on dimensions has its limitations.
It is quite difficult to realize a channel length of about 1 μm with good reproducibility, and new photolithography techniques such as electron beam exposure are required.

Therefore, the present invention has developed a short channel M whose channel length can be realized without depending on the master pattern's dimensions and with good reproducibility.
There are some attempts to propose a method for manufacturing OSFETs.

The gist of the present invention is to determine the channel length by using the dimensions of lateral diffusion of impurities into polycrystalline silicon, and more specifically, to determine the channel length by utilizing the dimensions of lateral diffusion of impurities into polycrystalline silicon. After selectively removing the removed side surfaces, impurities are added to the removed dimensions to form a channel, and the channel length depends on the lateral diffusion depth of the polycrystalline silicon. A method for manufacturing a MOSFET according to an embodiment of the present invention will be explained in detail below with reference to the drawings.

1 to 8 are process diagrams showing the outline of the manufacturing process of an embodiment of the present invention, and show a method of manufacturing a MOSFET in which a gate and a source are formed in a ring shape around a drain.
First, as shown in FIG. 1, a thin N-type diffusion layer 2 is formed on the surface of a P-type semiconductor silicon substrate 1 using impurity doping means such as ion implantation.

Next, a field oxide film 3 having a thickness of approximately 5,000 to 10,000 Å is formed by thermal oxidation, and holes are opened in areas where transistors are to be formed. This state is shown in FIG. Next, about 1000A is applied to the area where the field oxide film 3 is opened.
A thin oxide film 4 is formed by a thermal oxidation method, and the first
A polycrystalline silicon layer 5 is deposited by chemical vapor deposition, and a protective film 6 such as a silicon nitride film or an oxide film is further deposited thereon.

Thereafter, as shown in FIG. 3, a hole is formed in the protective film in a portion where a source region is to be formed to form an opening 7. Furthermore, at this time,
The field oxide film 3 may also be opened, but in this case it is more convenient to use a silicon nitride film as the protective film 6. This is because if an oxide film is used, when it is removed in the future, the field oxide film 3 will also be etched at the same time and become thinner. A silicon nitride film is advantageous because the etching means for the oxide film can be different from that for the oxide film. After opening the protective film 6, the first polycrystalline silicon layer 5 was selectively removed by etching using the protective film 6 as a blocking film, as shown in FIG. obtain the state. Next, an N-type pure substance such as phosphorus is implanted by ion implantation, and after adding an impurity to form the source formation region 8, thermal diffusion is performed in an atmosphere containing, for example, phosphorus to form the first polycrystalline silicon layer 5. Aspects of. Diffuse phosphorus from the
At the same time as forming the source formation region 8, drive-in is performed (FIG. 4).

Note that it is necessary to make the protective film 6 sufficiently thicker than the average range Rp of the implanted ions so that impurities are not implanted into the first polycrystalline silicon layer 5 during ion implantation. For example, phosphorus is accelerated at a voltage of 100Ke (electron port)
If it is injected at 1, the Rp will be about 1200A. Therefore, the protective film 6 needs to have a thickness of at least about 3000A. Next, as shown in FIG. 5, the protective film 6 is removed, and the region 9 containing phosphorus in the first polycrystalline silicon layer is selectively etched with an aminecatechol aqueous solution (ethylenediamine 17ml, pyrocatechol 3y1, water 8ml), etc.
Boron ions are implanted by ion implantation, and heat treatment is performed to form a channel P-type region 10 in the substrate.

At this time, the amount of ion implantation is determined so that the region 10 has a higher concentration than the N-type drift region 2 and a lower concentration than the source region 8. Next, after removing the first polycrystalline silicon layer 5 and etching and removing the thin oxide film 4, the substrate surface is oxidized again to form a gate oxide film 7, and a second polycrystalline silicon layer 12 is formed on the entire surface. The apertures 7'' are formed in the same pattern as the apertures of the protective film 6.

The state is shown in FIG. That is, when forming the openings 7'', it is possible to use the same mask used for patterning the silicon nitride film 6, and the openings 7'' can be formed with high precision.Next, as shown in FIG. As shown, the second polycrystalline silicon layer 12 is opened again to form the opening 13 that will become the drain diffusion window, and the remaining second polycrystalline silicon layer 12 is used as a blocking film to form the gate oxide film 11. The drain region 14 is formed by etching and diffusing an N-type impurity such as phosphorus.At this time, the source forming region 8 becomes a source region as specified.Note that the region 8 has already been doped with an impurity. The impurities are diffused again and become highly concentrated, but
I have no reservations. Further, due to the heat treatment during source and drain diffusion, the diffusion depths of the P-type channel region 10 and the drift region 2 become somewhat deeper. As a result, a drift region 2 and a channel region 10 are present between the drain region 14 and the source region 8, and the length of the channel region is the same as that of the lateral diffusion region 9 of the first polycrystalline silicon layer.
Further, as a result of the diffusion and expansion of the source region 8 in the lateral direction, the width of the channel region 10 becomes approximately 1 to 2 μm. In this way, short channel MOS of 1 to 2 μm can be easily
FET is configured. Finally, as shown in FIG. 8, an oxide film is deposited by chemical vapor deposition, a contact window is opened for taking out the electrodes, and metal wirings 15, 16, 17 are formed to complete the structure.

In this embodiment, the impurity was diffused into the drain region 14 by thermal diffusion, but similar results can be obtained by using ion implantation.

Another embodiment in which a source region 8 and an impurity diffusion region 9 from the lateral direction within the first polycrystalline silicon layer 5 are formed will be described.

From the state shown in FIG. 3, the first thin oxide film 4 is etched using the protective film and the first polycrystalline silicon layer 5 as a blocking film to expose the semiconductor surface of the source region. Thereafter, phosphorus is diffused into the semiconductor substrate 1 and the side surfaces of the first polycrystalline silicon layer 5 by thermal diffusion, and heat treatment is performed in an oxidizing atmosphere to oxidize the surface by about 1000A. At this time, an oxide film is also formed on the side surface of the first polycrystalline silicon layer 5, but its width is 10
00A, which does not pose a problem since the formation of the channel region 10 involves lateral diffusion due to drive-in of the channel region itself. According to this method, the source formation region 8 and the impurity diffusion region 9 can be formed at the same time. In the description of this embodiment, only the formation of an N-channel FET has been described, but it is also possible to form a P-channel FET by changing the P type to N type and the N type to P type impurity. Furthermore, the source regions on the left and right sides of FIG. 7 can be used as the respective sources of separate MOSFETs, and two transistors with a common drain 14 can be formed. In this case, the source region is not ring-shaped.
That is, for example, two MOSs that are part of a logic circuit
The method for creating the connected portion of the FET can also be performed using the steps shown in the attached drawings. Furthermore, in the present invention, it is naturally possible to diffuse impurities to only one side surface of the polycrystalline silicon, and in this case, it is preferable to cover one side surface with a protective film. As described above, according to the manufacturing method of the present invention, it is possible to realize a short channel MOSFET having a channel length that does not depend on mask pattern dimensions, and it can greatly contribute to increasing the Gm and speed of MOSFETs. .

[Brief explanation of the drawing]

FIGS. 1 to 8 show a MOSFE according to an embodiment of the present invention.
It is a sectional view showing the process of the manufacturing method of T. 1...P-type silicon substrate, 2...Thin diffusion layer, 4...Thin oxide film, 5, 12...
・Polycrystalline silicon layer, 6... Protective film, 7, 13
. . . Opening portion, 8 . . . Source formation region, 9.
... Impurity diffusion region, 10 ... Channel region, 11 ... Gate oxide film, 14 ... Drain region.

Claims (1)

[Claims] 1. A step of forming a shallow diffusion layer of a second conductivity type on one main surface of a semiconductor substrate of a first conductivity type, and forming an insulating film on this diffusion layer; 1, a step of selectively laminating a polycrystalline silicon layer and a protective film; and a second conductivity type impurity region for forming a source region on the surface of the semiconductor substrate using the first polycrystalline silicon layer and the protective film as a mask. and diffusing impurities from the exposed side surfaces of the first polycrystalline silicon layer, and
selectively removing the polycrystalline silicon layer, and removing the protective film and introducing impurities of a first conductivity type into the surface of the semiconductor substrate using the remaining first polycrystalline silicon layer as a mask to form a source region. forming a channel region adjacent to the first polycrystalline silicon layer; removing the first polycrystalline silicon layer and the first insulating film, and forming a gate oxide film and a second polycrystalline silicon layer on the semiconductor surface; A method for manufacturing a MOS type semiconductor device, comprising the steps of selectively removing the polycrystalline silicon layer and the gate oxide film, and diffusing impurities of a second conductivity type to form a drain region. 2. In forming the source region, impurities of a second conductivity type are added by ion implantation, and the impurity is diffused into the side surfaces of the first polycrystalline silicon layer by thermal diffusion. A method for manufacturing a MOS semiconductor device according to scope 1. 3. Etching the insulating film using the remaining region of the two-layer film of the protective film and the first polycrystalline silicon layer as a blocking film, forming a source region by thermal diffusion and at the same time exposing the exposed region to the first polycrystalline silicon layer. A method of manufacturing a MOS type semiconductor device according to claim 1, characterized in that impurity diffusion is performed from the side surface.