JPS6048240U - Resin-encapsulated semiconductor device - Google Patents

Resin-encapsulated semiconductor device

Info

Publication number
JPS6048240U
JPS6048240U JP13916883U JP13916883U JPS6048240U JP S6048240 U JPS6048240 U JP S6048240U JP 13916883 U JP13916883 U JP 13916883U JP 13916883 U JP13916883 U JP 13916883U JP S6048240 U JPS6048240 U JP S6048240U
Authority
JP
Japan
Prior art keywords
resin
wire bonding
semiconductor device
encapsulated semiconductor
sealed semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13916883U
Other languages
Japanese (ja)
Inventor
亨 吉田
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP13916883U priority Critical patent/JPS6048240U/en
Publication of JPS6048240U publication Critical patent/JPS6048240U/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は本考案の一実施例のレジンモールド素子中の半導体
チップ構造の平面図である。 1・・・・・・半導体チップ、2a、2b・・・・・・
ワイヤポンディング部、3a、3b、3c・・・・・・
AIライン、4・・・・・・パッシベーション膜(斜線
部)、5・・・・・・A1ライン対向部のパッシベーシ
ョン除去部。
The figure is a plan view of a semiconductor chip structure in a resin molded element according to an embodiment of the present invention. 1...Semiconductor chip, 2a, 2b...
Wire bonding part, 3a, 3b, 3c...
AI line, 4... Passivation film (shaded area), 5... Passivation removed portion of the area opposite to A1 line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] AIによる配線を施す半導体チップにおいて、お互いに
隣接するワイヤポンディング部よりA1ラインを出し合
い、これを対向させて位置させたAIパターンを有し、
その上に上記ワイヤポンディング部および上記A1ライ
ン対向部の一部または全部を除いてパッシベーション膜
を被覆し、その後ワイヤホンデインク、樹脂封止工程を
経て完成することを特徴とする樹脂封止半導体素子。
In a semiconductor chip that performs wiring using AI, it has an AI pattern in which A1 lines are brought out from adjacent wire bonding parts and are positioned facing each other,
A resin-sealed semiconductor characterized in that a passivation film is coated thereon except for part or all of the wire bonding part and the A1 line opposing part, and then a wire bonding and resin sealing process is performed to complete the resin-sealed semiconductor. element.
JP13916883U 1983-09-09 1983-09-09 Resin-encapsulated semiconductor device Pending JPS6048240U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13916883U JPS6048240U (en) 1983-09-09 1983-09-09 Resin-encapsulated semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13916883U JPS6048240U (en) 1983-09-09 1983-09-09 Resin-encapsulated semiconductor device

Publications (1)

Publication Number Publication Date
JPS6048240U true JPS6048240U (en) 1985-04-04

Family

ID=30312017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13916883U Pending JPS6048240U (en) 1983-09-09 1983-09-09 Resin-encapsulated semiconductor device

Country Status (1)

Country Link
JP (1) JPS6048240U (en)

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