JPS6081652U - Resin-encapsulated semiconductor device - Google Patents

Resin-encapsulated semiconductor device

Info

Publication number
JPS6081652U
JPS6081652U JP1983173535U JP17353583U JPS6081652U JP S6081652 U JPS6081652 U JP S6081652U JP 1983173535 U JP1983173535 U JP 1983173535U JP 17353583 U JP17353583 U JP 17353583U JP S6081652 U JPS6081652 U JP S6081652U
Authority
JP
Japan
Prior art keywords
resin
lead
semiconductor chip
bed portion
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983173535U
Other languages
Japanese (ja)
Inventor
江口　善吾
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP1983173535U priority Critical patent/JPS6081652U/en
Publication of JPS6081652U publication Critical patent/JPS6081652U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図Ａ、　Ｂは従来の樹脂封止型半導体装置を示す図
で、同図Ａは樹脂封止を行なう前の状態を示す平面図で
あり、同図Ｂは樹脂封止後の状態を示す断面図、第２図
Ａ、　Ｂは本考案の一実施例に成る樹脂封止型半導体装
置を示す図で、同図Ａは樹脂封止を行なう前の状態を示
す平面図であり、同図Ｂは樹脂封止後の状態を示す断面
図、第３図及び同図Ｂはそれぞれ第２図Ａ、　Ｂに示し
た実施例の変形例を示す拡大断面図である。 １・・・ベッド部、２・・・半導体チップ、３・・・リ
ード、４・・・タイバー、５・・・ボンディングワイヤ
、６・・・樹脂モールド層、７・・・段差。Figures 1A and 1B are diagrams showing a conventional resin-sealed semiconductor device, with Figure A being a plan view showing the state before resin sealing, and Figure B showing the state after resin sealing. The cross-sectional views shown in FIGS. 2A and 2B are views showing a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 2A is a plan view showing the state before resin sealing. FIG. B is a sectional view showing the state after resin sealing, and FIGS. 3 and 3B are enlarged sectional views showing modifications of the embodiment shown in FIGS. 2A and 2B, respectively. DESCRIPTION OF SYMBOLS 1... Bed part, 2... Semiconductor chip, 3... Lead, 4... Tie bar, 5... Bonding wire, 6... Resin mold layer, 7... Step.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 熱伝導性の高い金属板から成るベッド部と、該ベッド部
から離間してその周囲に配設され、しかも前記表面レベ
ルからずらして配置された導電性金属から成るリードと
、前記ベッド部のリード側表面上にマウントされた半導
体チップと、該半導体チップ表面のポンディングパッド
を前記リードの一端に接続する導電性のボンティングワ
イヤと、前記ベッド部、リードの一端部、半導体チップ
及びボンティングワイヤを封止する樹脂モールド層とを
具備し、前記ベッド部の半導体チップがマウントされた
側とは反対側の表面を前記樹脂モールド層から露出させ
ると共に、ベッド部の樹脂封止されている側端面に段差
を設けたことを特徴とする樹脂封止型半導体装置。A bed portion made of a highly thermally conductive metal plate, a lead made of a conductive metal disposed around the bed portion at a distance from the bed portion and offset from the surface level, and a lead of the bed portion. A semiconductor chip mounted on a side surface, a conductive bonding wire connecting a bonding pad on the surface of the semiconductor chip to one end of the lead, the bed portion, one end of the lead, the semiconductor chip, and the bonding wire. a resin mold layer for sealing a resin mold layer, the surface of the bed section opposite to the side on which the semiconductor chip is mounted is exposed from the resin mold layer, and the side end surface of the bed section that is sealed with the resin A resin-sealed semiconductor device characterized by having a step.
JP1983173535U 1983-11-09 1983-11-09 Resin-encapsulated semiconductor device Pending JPS6081652U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983173535U JPS6081652U (en) 1983-11-09 1983-11-09 Resin-encapsulated semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983173535U JPS6081652U (en) 1983-11-09 1983-11-09 Resin-encapsulated semiconductor device

Publications (1)

Publication Number Publication Date
JPS6081652U true JPS6081652U (en) 1985-06-06

Family

ID=30378014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983173535U Pending JPS6081652U (en) 1983-11-09 1983-11-09 Resin-encapsulated semiconductor device

Country Status (1)

Country Link
JP (1) JPS6081652U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03293749A (en) * 1990-04-11 1991-12-25 Rohm Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03293749A (en) * 1990-04-11 1991-12-25 Rohm Co Ltd Semiconductor device

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