JPS6044679B2 - Speech synthesis control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voice synthesis control device that performs voice synthesis in voice devices such as voice calculators and voice clocks, and particularly relates to a voice synthesis control device that performs voice synthesis in voice devices such as voice calculators and voice clocks, and in particular, a voice synthesis control device that uses voice data for voice synthesis and the voice data. R for storing control programs that perform speech synthesis and other control programs.
The present invention provides a speech synthesis control device using an OM, characterized in that a data pointer indicating an address of audio data is provided independently of a program counter indicating a step position of a control program in the ROM.

In a conventional speech synthesis control device, the speech data that is the basis for speech synthesis and the control program that performs speech synthesis using this speech data are stored in separate dedicated ROMs.
However, the present invention is fundamentally different in that these are placed in the same address space.

However, voice synthesis control requires high-speed calculations due to the nature of voice, and simply arranging them in the same address space does not allow calculations to be performed while reading voice data. When reading audio data, the present invention sets its address in a data pointer and executes a READ command to read the audio data, and when executing each step of a speech synthesis control program, the program There is one that executes instructions according to a counter.

A detailed description will be given below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a voice calculator embodying the present invention. In the figure, VC is a controller composed of a 1-chip LSI, and controls key input, calculation, display, voice synthesis, etc.

This controller VC is equipped with various external connection terminals. A is an address bus, D is a data bus, and CE is a chip enable signal line, which are connected to an external ROMM. DA is an audio signal output line, and the amplifier circuit AM
Connected to P. A speaker SP is connected to the output line of this amplifier circuit AMP. Also, F is the signal that controls the power on/off of the amplifier circuit AMP.
This is one terminal of the port that outputs to. T is a key strobe signal output line, and T is a key return signal input line, which are connected to the key input device KEY. H is a common signal line, and S is a segment signal line, which are connected to the liquid crystal display device DISP. The external ROM, M, stores a main program for operating the calculator and audio data.

Further, the controller VC includes a read-only memory (ROM), a read-write memory (RAM), an arithmetic control circuit, etc., and a speech synthesis control program is stored in the built-in ROM. Because of this configuration, the controller VC has versatility as a controller for speech synthesis equipment.

In other words, even if the device is different, the words to be outputted are different, or the specifications are different, the controller itself can be changed simply by changing the memory contents of the external ROM, changing the key top display, and changing the segment configuration of the display. can also be used without any modification. FIG. 2 is a diagram showing the system configuration of the controller VC.

In the figure, RM is a ROM that stores an algorithm (processing program) for voice synthesis control, and has a capacity of 16 bits and 512 steps.

A1 to Al4 output address signals to the external ROM.
Address signal output terminals, D1 to D8 are external ROM
This is a data signal input terminal for reading data. PC is a program counter, and DP is a data pointer. The PC specifies the address of the internal memory 0MRM and the main program storage area of the external memory 0M. On the other hand, DP specifies the address of the audio demitter storage area of Gaikanzawa 0M. The RAM is a read/write memory and has a capacity of 8 bits x 64 = 512 bits, and includes an area R1 used for voice synthesis control, an area R2 used for calculator calculations, and an area R3 for display. Yes. Ru. Each bit in the display area corresponds to each segment of the liquid crystal display device, and by writing a display pattern in this area, the pattern is displayed. B is R
This is the AM address register. Sometimes a certain area of RAM is used as a stack for subroutines,
SP is a stack pointer indicating the position. , Al
．． U is an arithmetic circuit that performs arithmetic and logical operations on the signals of the internal data bus DB, the signals output from the built-in ROMRM, and the signals output from the accumulator ACC.

Further, JF is a flip-flop for discrimination, HF is a half-carry flip-flop (carry from the 4th bit), and CF is a carry flip-flop. The ID is an instruction decoder, which disables the upper 8-bit operation code output from the built-in 0MRM or the instruction output from the external λ0M, and outputs a predetermined micro-order.

is a power control section, which controls the oscillation of the clock generator CG, generation/stop of system clocks φ1 and φ2, turning on/off the display power, etc.

That is, during calculation, system clocks φ1 and φ2 are output, and the entire system operates. Further, in the displaying state, only the display control section is operated by stopping the generation of the system clock. Since this LSI is configured as a C-MOS, power consumption can be kept low by stopping the system clock. . . Box's? I is the negative power supply terminal, and GND is the ground terminal. CGl,
CG2 is a terminal to which a resistor or ceramic filter for oscillating the clock generator CG is connected.
Incidentally, this oscillation frequency is 131 kHz. 0SC
is an oscillator for a clock function, and this oscillation waveform is frequency-divided by a frequency divider circuit DIV.

Xl and X2 are terminals to which a crystal oscillator is connected. The input of the frequency dividing circuit DIV is composed of a PLA, and divides the frequency of one of the outputs of the clock generator CGl oscillator 0SC. A 1-second signal S1 is output from the final stage of the frequency dividing circuit DIV. BP is a common signal generation circuit of the liquid crystal display device, and H1 to H1 are common signal output terminals.

BP also outputs an address signal for the display area R3 of the RAM. SB is a segment buffer that outputs segment signals to the liquid crystal display device, and S1 to S25 are segment signal output terminals. K, is a 6-bit input port, and K1 to K6 are key return signal input terminals connected to a key input device.

Also, T1 is an 8-bit output port, and T1 to T8
is a key strobe signal output terminal connected to a key input device. Furthermore, F, is a 4-bit output port,
In this embodiment, the contents of the most significant bit of the address signal of the external ROM is output from F4. Furthermore, as described above, a power on/off control signal for the amplifier circuit is output from F1. P is a latch circuit that latches 8-bit audio data output from the ALU.

DAC is a D/A converter, and DA is an audio signal output terminal that outputs an analog audio signal. IC
is an impedance conversion circuit, and D. is an impedance conversion circuit. By connecting a feedback resistor between Ai and DAO, the speaker can be driven simply by connecting a simple external amplifier circuit.
CEO is a terminal that outputs a chip enable signal to the external ROM.

Although not shown, the chip enable signal generation circuit operates on a micro-order basis. Figure 3 shows only built-in 0M
FIG. 3 is a diagram showing the relationship between RM and external ROMM.

The built-in BOMRM is 16 bits long (1 address 16 bits) and has an area from addresses 0000 to 01FF.

On the other hand, the external ROMM is 8 bits long and has a rear address of 000.
It has an area from 0 to 7FFF. The built-in ROMRM stores the voice synthesis control program VP, and the external R
The OMM contains the main program MP and audio data VDL, which are used to function as a calculator, in the positional relationship shown in the figure.
VD2 is stored. The aforementioned program counter PC specifies the address of the program area with this VP, while the data pointer DP specifies the address of the entire area of the external ROMM.

That is, when reading audio data from the external ROMM, the address of the audio data to be read is set in the data pointer DP, and the above reading is performed. Furthermore, when executing program commands or main program commands for voice synthesis control, the contents of the program counter PC are counted up each time a step command designated by the program counter PC is executed, and the commands are executed sequentially. Since the speech synthesis control program has a long step of 16 bits, speech synthesis requiring high-speed calculation can be performed even with a relatively slow system clock.

The upper 8 bits are an operation code, which is output to an instruction decoder D as shown in FIG.
The bit is an operand and is output to the internal data bus DB. On the other hand, instructions read from the external ROM are input via the external data bus and input to the instruction decoder D. In addition, the data is transferred to the internal data bus DB.
is input. In addition, R, Ar! 4 can also be connected.

Like the Gaikanzawa 0M, it can be used by sharing the address bus and data bus and outputting the chip enable signal and read/write signal from the output port F to the external ROM. FIG. 4 shows a time chart for an instruction to read audio data from an external ROM. This instruction is a two-cycle instruction, and the case where this instruction occurs at the step of the contents P of the program counter PC is shown.

In the first cycle, the address of the audio data area is set in the data pointer DP, and the data is fetched, and in the second cycle, it is fetched into the internal data bus.

Thereafter, the contents of the program counter PC are counted up. The entire processing procedure is shown in the flowchart of FIG.

In other words, by executing the main program in Sotomazawa 0M, processes such as key identification, calculation, and display of calculation results are performed, and when audio notification is performed, the word code indicating the word to be outputted is sent to the accumulator ACC. By loading the speech synthesis control program and jumping (subroutine call), the speech notification of the word is performed.

According to the present invention described above, it is possible to obtain an extremely useful speech synthesis control device whose system configuration is simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the general configuration of a voice calculator embodying the present invention, FIG. 2 is a diagram showing the system configuration of the controller shown in FIG. 1, and FIG. 3 is a block diagram showing the system configuration of the controller shown in FIG.
A diagram showing the relationship between M and the address of the external ROM, Figure 4 is a diagram showing a time chart for the command to read audio data from the external ROM in the audio calculator, and Figure 5 is a processing procedure in the audio calculator. This is a flowchart showing the following.

Claims (1)

[Claims] 1. A program counter that has a ROM that stores voice data that is the basis for creating a synthesized voice and control instructions for creating a synthesized voice using the voice data, and that indicates the step position of the control instruction. A speech synthesis control device characterized in that a data pointer indicating an address of the speech data is provided independently of the above.