JPS5870350A - Integrated circuit for speech synthesizer - Google Patents

Abstract

PURPOSE:To decrease the number of component parts and to improve the general-purpose properties for the titled integrated circuit, by performing the basic control with a 1-chip LSI and at the same time connecting externally a memory that stores the programs of the arithmetic procedure, etc. and the speech data for speech synthesis. CONSTITUTION:A speech synthesizer consisting of a 1-chip LSI and other contollers VC contain various types of external connection terminals which are connected to an external ROM memory M via an address bus A, a data bus D and a chip enable signal line CE. An audio signal output line DA is connected to an audio amplifier AMP. At the same time, a strobe signal output line T and a key return signal line K are connected to a key input device KEY and then connected to a liquid crystal display device DISP via a common signal line H and a segment signal line S. A main program which works as an electronic calculator and the speech data are previously stored in the memory M, and a control program for speech synthesis is stored previously in an ROM memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speech synthesis integrated circuit, and particularly to a key human power device,
The present invention relates to an integrated circuit for speech synthesis equipment (hereinafter referred to as speech synthesis LSI) which is extremely useful and highly versatile when adopted as a device equipped with a display device and outputs audio.

In recent years, techniques have been developed to synthesize speech and other complex waveforms using essentially digital techniques.

There are many uses for such speech synthesis devices, such as electronic desktop calculators that notify calculation formulas, calculation results, etc., clocks that notify the time by voice, and other devices that provide voice instructions on how to operate the device itself. It can be widely used in the devices described.

In this way, it is predicted that speech synthesis devices will be used more widely in various fields in the future. Conventionally, speech synthesis systems have been configured using, for example, a microprocessor and a speech synthesis LSIt, and the processor has been used to A command is given to the synthesis LSI to make it emit a voice according to the command. That is, the processor stores algorithms such as voice synthesis control procedures, and the actual voice synthesis LSI stores voice data for voice synthesis. Furthermore, in devices of the scale of voice calculators, voice clocks, etc., the circuits for voice synthesis output control occupy a considerable area compared to the circuits for controlling the original functions of the entire system. When constructing a voice calculator in such a system, the calculator's original key human control, arithmetic control, display control, etc. are controlled by a microprocessor, and this microprocessor provides instructions and data to the voice synthesis LSI. It was intended to provide audio notifications.

However, such voice synthesis systems cannot perform basic controls such as voice synthesis, manual key control, and display control using only a single-chip voice synthesis LSI.
Furthermore, storing voice data for voice synthesis in a voice synthesis LSI in a fixed manner in advance in the voice synthesis LSI memory has the disadvantage that it cannot be applied to various voice output devices and the versatility is significantly reduced. .

The present invention has been made in view of various points of conventional speech synthesis systems, and in particular, basic control such as key manual control, display control, arithmetic control, and speech synthesis control, that is, microprocessor functions, is integrated into an integrated circuit for speech synthesis equipment. The number of parts is reduced by having the system built-in and performing basic control on a single-chip LSI, and by connecting externally the memory that stores programs such as calculation procedures and voice data for voice synthesis.
The object of the present invention is to provide a highly versatile integrated circuit for speech synthesis equipment.

Although there are several types of speech synthesis methods, the present invention is particularly effective for speech synthesis methods that do not require hardware circuitry such as sound source generation circuits and digital filters required for Palcall and LPC methods, such as waveform synthesis methods. .

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Fig. 1 shows a block diagram of a speech synthesis calculator which is an embodiment of the device of the present invention.

In the figure, VC is a voice synthesis and other controller composed of one chip LSI, and this controller is equipped with various external connection terminals.

A is an address bus, DH7'-tabus, C1j is a chinobu enable signal line, and a read-only memory IJ-M is connected to the outside. DA is an audio signal output line and is connected to the audio amplification device AMP. A speaker is connected to the output line of this AMP. Also F, is A
This is one terminal of a port that outputs a signal for power control of the MP to the AMP.

T is a strobe signal line, and T is a key return signal line, which is connected to the key input device KEY. H
is a common signal line, and S is a segment signal line, which are connected to the liquid crystal display device DISP.

A main program for operating as a calculator and audio data are stored in advance in the ROM'M. The VC has a built-in read-only memory, a read-write memory, an arithmetic control circuit, etc., and a speech synthesis control program is stored in advance in this read-only memory.

Because of this configuration, the controller VC has versatility as a controller for speech synthesis equipment.

In other words, even if the equipment is different, the words of the synthesized voice to be output are different, and the specifications are different, the contents of the external read-only memory M, the display of the key tops, and the segment configuration of the display section can be changed. The controller VC itself can be used without any modification.

Figure 2 is a diagram showing the system configuration of controller VC.

In the figure, 1 is a read-only memory (ROM) that stores in advance an algorithm (processing program) for voice synthesis control, and has a capacity of 16 bits and 512 steps. A and ~A14 are address signal terminals for outputting address signals to the external ROM, and D and ~D8 are data signal terminals for reading data from the external ROM. PC is a program counter, DP is a data pointer, and PC is a counter that indicates the address for voice synthesis control in the built-in ROM and the address of the main program in the external ROM. On the other hand, DP is a pointer that indicates the location (address) of audio data recorded in the external ROM. 2 is a read/write memory (RAM), which has a capacity of 8 bits x 64 = 512 bits and includes an area used for voice synthesis control, an area used for calculator calculations, and an area for display. Each bit in the display area corresponds to each segment of the liquid crystal display device, and by writing a display pattern into this area, the pattern is displayed. B is a RAM address register. A certain area of RAM is sometimes used as a stack for a subroutine, and SP is a stack pointer that indicates the location. 3 is the signal of the internal data bus, the signal output from the built-in ROM, and the accumulator A.
This is an arithmetic circuit (ALU) that performs arithmetic and logical operations on signals output from the ALU and other signals. Further, J is a flip-flop for discrimination, H is a carry (half-carry) flip-flop from the 4th bit, and C is a carry flip-flop. 4 is an instruction decoder which decodes the upper 8-bit operation code output from the built-in ROM and outputs a micro order.

Reference numeral 7 denotes a power control section, which controls oscillation/stopping of the clock generator CG, stopping generation of the system clock, and turning on/off the display power source. During the shunting operation, system clocks φ1 and φ2 are output, and the entire system operates. In addition, in the display live state, only display control is operated by stopping the generation of the system clock.

Since this LSI is composed of C-MOS, power consumption can be kept low by stopping the system clock. VOG is the negative power supply terminal of this LSI. C
G and CG2 are terminals to which a resistor or ceramic filter for oscillating the built-in CG is connected. Incidentally, this oscillation frequency is 131 KHz. O8C is an oscillator for the clock function, and this oscillation waveform is divided by the frequency divider
The frequency is divided by X, , X2 are terminals to which a crystal oscillator is connected. The input of the divider is a program logic array
(PLA), which divides the output of either the built-in CG or O8C. A 1 second signal IS is output from the final stage of the frequency divider. BP is a common signal generation circuit of the liquid crystal display device, and H1 to H4 are common signal output terminals. BP also outputs an address signal for the display area of the RAM. SB is a buffer 1 that generates segment signals to the liquid crystal display device. S and S25 are terminals connected to segment terminals of the liquid crystal display device. Ki is a 6-bit input port, a key input device is connected to K1-6, and a key return signal is input. Ti is an 8-bit output port, and a key input device is connected to T to T8, and a key strobe signal is output. Fi is a 4-bit output port, and in this example, F4
The most significant bit signal of the external ROM address signal is output. PVi is a latch circuit that launches 8-bit audio data output from the ALU. 5 is D/A
DAi, which is a converter, is a terminal that outputs an analog audio signal. Reference numeral 6 denotes an impedance conversion circuit, and by connecting a return resistor between jl) DAi and DAo, the speaker can be driven by simply connecting a simple external amplifier circuit. CEo is a terminal that outputs a chip enable signal to the external ROM. Although not shown, the chip enable signal generation circuit operates on a micro-order basis.

The operation will be explained below.

FIG. 3 shows the relationship between the addresses of the built-in ROM and the external ROM. The built-in ROM is 16 bits long and covers the area from addresses 0000 to 0IFF. External RO
M has a length of 8 bits, and the area from addresses 0000 to 7FFF can be used. vP is a voice synthesis control program, MP is a main program for functioning as a calculator, and VD.

and VD2 respectively indicate storage areas for audio data.

The aforementioned program counter PC specifies the address of the MP and the program area of the MP, while the data pointer DP specifies the address of the entire area of the external ROM. That is, when reading data from an external ROM, the address information of the data to be read is set in the data pointer DP, and the contents of the ROM are read. Further, when executing program commands or main program commands for voice synthesis control, the value of the program counter PC is counted up each time the step commands specified by the program counter PC are executed, and the commands are sequentially executed.

Since the speech synthesis control program has a long step of 16 bits, speech synthesis requiring high-speed calculation can be performed even with a relatively slow system clock. The upper 8 bits are an operation code and are output to an instruction decoder as shown in FIG. 2, and the lower 8 bits are an operand and are output to an internal data bus.

On the other hand, instructions read from the external ROM are input internally from the external data bus and input to the instruction decoder. Data is also input to the internal data bus. Additionally, RAM can also be connected externally. Similar to external ROM, the address bus and data bus are shared, and the chip enable signal and read/write signal are sent from the F port to the RAM.
It can be used by outputting to .

FIG. 4 shows a time chart for an instruction to read data (audio data) from an external ROM. This instruction is a two-cycle instruction, and the case where this instruction is present in the step of the contents Pi of the program counter PC is shown.

In the first cycle, the address of the data area is set in the data pointer DP, and the data is taken to an appropriate size.In the second cycle, the data is taken into the internal data bus.After that, the contents of the program counter PC are counted up.

FIG. 5 is a flowchart showing the processing procedure of the entire apparatus. First, by executing the main program in the external ROM, processes such as key identification, calculation, and display of calculation results are performed.When performing voice notification, the word code corresponding to a predetermined word is loaded into the accumulator and the voice is output. By jumping to the synthesis control program (subroutine call), the word is announced by voice.

Another feature of the present invention is that it incorporates a D/A converter and an impedance conversion circuit.

FIG. 6 shows that part. In the figure, PM1
~PV8 is a latch circuit for digital audio signals, and its output is connected to a ladder resistor via a gate. This ladder resistor is composed of a diffused resistor to obtain high accuracy. This output DAi is connected to the outside from a terminal of the LSi.

Therefore, the speaker can be driven by simply connecting an ordinary amplifier circuit. An impedance conversion circuit consisting of an inverter circuit is provided at the output of the D/A converter. This is an 8-9 inverter circuit, but by connecting a return resistor FR between its input and output, this inverter circuit is used as a linear amplifier. Since the resistance R of the D/A conversion circuit is on the order of several tens of ohms, the output impedance of the D/A conversion circuit is quite high. ing.

Therefore, the current can be taken out to the outside, and the speaker can be driven with a very simple emitter/talower circuit as shown in FIG.

Note that the NAND gate provided at the input of the D/A conversion circuit is controlled by the signal Amp. This signal Amp is generated with the logic Arnp=F+ (ACL+ST). As mentioned above, Fl is the signal to turn on the amplifier power (
(Also output from port F1), ACL is a signal indicating an auto-clear state, and ST is a signal indicating a displaying state. That is, if audio is being output and the state is not in the auto-clear state but in the calculation state, the N A and N D gates operate as clock gates, and the contents of the launch PVi are D/A converted. In other cases, the NAND gate output is H'', so D/
The input to the A conversion circuit becomes L''. Therefore, no current flows through the ladder resistor, and no wasteful power consumption occurs.

On the other hand, the inverter ■, analog switch AS, MO controlled by the original Amp signal of the impedance conversion circuit
S game) PM is this control circuit.

If this were not present, the input of inverter circuit A would be 11
Since the output becomes H'' when L I+, a current flows through the return resistor FR, which means that power is wasted in a state where no audio output is performed.

On the other hand, by inputting the control circuit as shown in the figure, unnecessary power consumption can be eliminated. In other words, Am
When the p signal is "L", the analog switch As is turned off, and the input of the inverter circuit A becomes "H" potential. Therefore, the potential of DAo becomes L'', and no current flows through the return resistor FR. Also, when the circuit shown in Figure 7 is connected, no unnecessary current flows to the FFL speaker when the transistor is 0. In this way, , basic controls such as voice synthesis, manual key control, and display control can be performed on a single chip LSI, and if this is used to configure a voice calculator, for example, the calculation procedures as a calculator, etc. Memo IJ-'e that stores programs and audio data used as a calculator
This can be done by connecting to the outside. The integrated circuit for speech synthesis equipment can be used as a general-purpose component in various speech synthesis equipment.

As explained above, according to the present invention, basic control of speech synthesis, such as manual key control and display control (conventional microprocessor functions), can be implemented on a single chip LSI.
By externally connecting a memory for storing a control program and voice data for voice synthesis, an extremely useful and highly versatile integrated circuit for voice synthesis equipment can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a speech synthesis calculator according to an embodiment using the speech synthesis LSI according to the present invention, Fig. 2 is a system configuration diagram of a controller in the same block diagram, and Fig. 3 is the address relationship between the built-in ROM and external ROM. Figure 4 shows the external RO
FIG. 5 is a flowchart showing the processing procedure of the entire device; FIG. 6 is a specific configuration diagram of a circuit including a D/A converter and an impedance conversion circuit; FIG. 7 is a diagram showing an example of a speaker drive circuit. In the figure, vC: controller 1M: memory. KEY: Key human power device, DISP: Display device. AMP: Audio amplification circuit, sp: Speaker, 1: Built-in R
OM, 2: RAM, 3: Arithmetic circuit, 4: Instruction decoder, 5: D/A converter, 6: Impedance conversion circuit, 7: Power control circuit Agent Patent attorney Aihiko Fuku

Claims (1)

[Claims] 1. Built-in control means for human key control, display control, arithmetic control, and voice synthesis control, as well as at least a control program (main program) for controlling the main body of the device and voice data for creating synthesized sounds. An integrated circuit for a speech synthesis device, characterized in that it is provided with means for connecting to the outside of a memory stored in advance.