JPS5887643A - Electronic calculator - Google Patents

Abstract

PURPOSE:To arbitrarily change the generation of imitation sound with the instruction in a program, and to diversify the functions of a calculator, by designating the output state of an imitation sound such as the number of repetition of the imitation sound and the generating time of imitation sound relating to the imitation sound generation instruction in the program. CONSTITUTION:A microprocessor unit MPU controlling the entire electronic calculator is connected with an input and output I/O PORT via a key input device KEY and an RAM and an ROM are connected to the RORT via a data bus, an address bus and a control bus. A clock circuit CLOCK is connected to the PORT and also a buzzer drive circuit DR connected to an imitation sound generator BUZ is connected. The output state of imitation sound such as the number of repetition of imitation sound and generating time of the imitation sound is designated from the input section relating to an imitation sound generating instruction in a program, the generation of the imitation sound is arbitrarily changed through the designation of the program to diversify the functions of the calculator.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable electronic calculator in which the generation of onomatopoeia can be programmed.

In general, programmable electronic computers can be used in a variety of ways by inputting and executing programs created according to the purpose of use.

Conventionally, the execution status of a program was output as a sound, and onomatopoeia (
BEEP), but these onomatopoeic output commands only produced a limited number of sounds.

An object of the present invention is to provide an electronic calculator that can generate different onomatopoeic sounds depending on the purpose.

FIG. 1 shows an external front view of an embodiment of the present invention. The display section 1 is a dot matrix liquid crystal display device. The character input key 2 is used to input letters of the alphabet as well as some symbols. Numerical input key 3 inputs numbers θ to 9. The input execution key [ENTERJ4 executes input of the operation contents of the input key displayed on the display section 1 into the main body of the computer.

FIG. 2 shows the system configuration of an embodiment of the present invention.

The microprocessor unit MPU provides integrated control of the entire system, and its constituent functions will be described later. Display part L
The CD is composed of a liquid crystal display element, and a display control unit DSO controls character display or lighting of symbol segments. Key human power device KEY input/output boat I10 POR
A key strobe signal is input from T, and a key return signal is output to the MPU. Read/write memory RAM
stores various registers, flags, programs, etc. The read-only memory ROM stores in advance an interpreter routine for executing programs and other control programs. Clock circuit 0L
OOK generates time data.

The buzzer sound generating body BUZ is driven by a drive circuit DR. The input/output port I10 PORT is connected to the address bus, data bus, and control bus, outputs a strobe signal to the key human power device KEY, and outputs a strobe signal to the clock circuit C!
It has interface functions for the MPU, such as inputting and outputting time data to and from LOOK and outputting drive signals to the buzzer drive circuit DR. Connector ON is a memo of RAM and ROM! J-4-%-7' Connector ON is for connecting an external data recorder, printer, input φ device, and expansion memory. The microprocessor unit ( ) MPU outputs a synchronization signal HA and a display on/off signal DISP to the display control unit DSC, and also outputs a pack plate signal H to the liquid crystal display device LCD.
Outputs 8 to H7. The display control unit DSO has a built-in display memory corresponding to each segment of the liquid crystal display device LCD, and each segment corresponds to each bit of the memory.

Therefore, desired characters and symbols can be displayed by writing a bit pattern corresponding to the display pattern.

Figure 3 shows the microprocessor unit (MPU) in Figure 2.
The internal configuration diagram is shown.

Program counter P is a 16-bit register,
It indicates the next address of the instruction currently being executed by the MPU, and is automatically incremented by +1 when the instruction is executed and the next instruction is etched by 7. stack pointer S
is a 16-bit register that indicates the address of the next available stack in the memory pushbutton or popup stack. Data registers X, Y.

Each U is a 16-bit register and is also used as a data pointer. Accumulator A is used to hold calculation results or to transfer data to and from external memory. The status register T stores various states such as carry, borrow, zero, overflow, etc. due to operation results. Address buffers are coupled to address buses A Do to AD15. The arithmetic logic operation circuit ALU performs operations such as addition, subtraction, multiplication, and division.

The operation buffer BUF is used for the above arithmetic and logic operations. The oscillation circuit O8C has a crystal oscillator or the like connected to an external terminal XLot XLt, and outputs a clock φo5 through a 1/2 frequency divider circuit (÷2). The rip-tuk control circuit is WAI
Controls generation and stop of internal clocks in accordance with the T signal. The frequency dividing circuit further divides the frequency of the clock φ and outputs a display synchronizing signal HA, and also supplies signals tr and 7 to a timer controller to be described later. The timer controller performs count control of a timer counter and timer interwoven control. timer counter is 9
It is a bit polynomial counter and counts time for timer interleaved. The interrupt control unit is connected to terminal NM1. Interrupt control is performed using interrupt requests input from the MI and signals output from the timer controller. The H counter is used to generate the pack plate signal of the liquid crystal display. The input terminal HIN of this counter is normally connected to the terminal HA. The display control circuit uses display power supplies VDIS I VA IVB and v
It receives the supply of M and outputs pack plate signals H, #H,. =PU.

PV is a general purpose flip 70 block, and DISP is a 7 flip flip block for display on/off control. Input port I No~
IN takes 8-bit data into the internal bus. The data bus control circuit is a bidirectional control circuit that writes data to or reads data from the external memory through the data bus). The infrastructural decoder and CPU control circuit have a memory write signal R/W and a memory enable signal MEo.
t Output MEI etc.

FIG. 4 shows a specific example of the buzzer drive circuit DR shown in FIG. 2. The signal S3 is a recording/playback signal output from the interface of the tape recorder, and normally a buzzer sound is output from the buzzer BUZ.

However, the signal 8. output from Ilo PORT. The AND gate is controlled to open and close, and the generation of sound can be prohibited. There is a flag FE in the RAM in Figure 2.
Inside the Ilo PORT, there is provided an FBI whose state is inverted in accordance with the set and reset state of the flag FB, and the signal So mentioned above is output as the state output of this FBI.

In the present invention, words related to onomatopoeic generation commands are rBBEP
, Format 1, Format 2, Format 3". This format 1 specifies the number of onomatopoeias. Format 2 specifies the frequency of onomatopoeia. Format 3 specifies the length of one onomatopoeia of the frequency of Format 2.

If format 2 is omitted, format 3 is automatically set to ±160. If format 2 and format 3 are omitted, format 2 =
It is set to 8. Specifically, about 230)-fz~7
The frequency of the seagull is divided into 256 and the predetermined 0
Any code from 00 to 255 is selected. Format 2 =
For example, 8 corresponds to about 4 ki.

Also, if you execute the command rBEup 0FFJ manually or from a program,
The BEEP sound output command is skipped, and furthermore, the recording of the tape recorder as an externally connected data recorder is performed.
Playback sound is prohibited.

If the command rBEEP ONJ is executed manually or from a program, the BEEP sound output command becomes valid, and furthermore, the inhibition of recording and reproduction sound output from an externally connected tape recorder is lifted.

FIG. 5 shows a 70-chart of the execution of the onomatopoeia instruction of the present invention. In this figure, FB is a flag indicating the BEEPON mode, C is a format 1 buffer, CF is a format 2 buffer, cFl is a counter, CP is a format 3 buffer, and cPl is a counter.

First, if format 1 is ON, select F'B in ml)L,
, If it is OFF, reset FB in town. If the content of format 1 is a simple numerical value or a calculation formula or numerical variable that results in a numerical value, and the flag FB is in the state 77), the content of format 1 is input to buffer 7Q in m3. Ru. If format 2 is specified, its contents are manually input to the buffer OF in m4, and if not specified, it is input to buffer OF in m6.
A predetermined value 8 is input at . If format 2 is specified and format 3 is specified, the value +
256 is input to buffer CP. If format 3 is not specified, a predetermined value 416 is input in m7.

Thereafter, onomatopoeic sounds are generated according to the three given parameters. That is, CP and CF at nl and n2
The values of are saved in the OPI and CPl counters, respectively,
Due to the countdown operation of OFl in the loop of n4→n5-n6→n4, a 1H'' level is output for a time corresponding to the value.As shown in FIG.
It is output from the o boat as a signal St. next,"
Preparations are made to output the "L" level at T t n@, and the "L" level is output for the same period of time due to the countdown operation of OFM in the loop of n9-Fjto-'Fixt→n.

In this way, a rectangular wave, which is the minimum unit waveform of BEEP, is output. This square wave is n 12-n l3-n2
By repeating the program, only the value of CP is continuous. The FJ14 wait time is for not making any sound for the time indicated by T in FIG. In this way, the program for generating a signal in which the rectangular wave is repeated 02 times and paused for a time T is repeated from "lli→Garo" to "nl", and after this repetition has been executed C times, the program ends.

According to the present invention, whether or not an onomatopoeia occurs depending on the program 9
Occurrence time! # Since the number of returns can be specified arbitrarily, the functions of the programmable computer can be diversified.

[Brief explanation of the drawing]

FIG. 1 is an external front view of an embodiment of the present invention, FIG. 2 is a block diagram showing the entire system of the embodiment of the present invention, FIG. 3 is a block diagram showing the internal configuration of the MPU shown in FIG. 2, and FIG. FIG. 2 is a circuit diagram showing a specific example of the buzzer drive circuit DR, FIG. 5 is a flowchart showing a command execution program for generating onomatopoeia of the present invention, and FIG. 6 is a waveform diagram of onomatopoeia according to an embodiment of the present invention. . 1...Display section 2...Character key 6...Numeric key BUZ...Onomatopoeia generator (buzzer) BEEF...Onomatopoeic command C...Buffer OF for storing the number of onomatopoeic repetitions...
・Buffer CP that stores onomatopoeic frequencies...Onomatopoeic 1
buffer that remembers the duration of times

Claims (1)

[Claims] (1) In a programmable electronic calculator equipped with an input section, an output section, an onomatopoeia generator, and a memory for storing programs, the output status of onomatopoeia, such as the number of onomatopoeic repetitions and the time of onomatopoeic occurrence, can be determined by the onomatopoeia in the program. An electronic calculator characterized in that the electronic calculator is configured to be able to be specified by the input section in relation to a generated instruction.