JPH052253U - Electronic device using external memory - Google Patents

Abstract

(57) [Summary] [Purpose] The optimum access timing can be selected according to the type of external memory, enabling control that matches the characteristics of the memory. [Structure] The switch 24a of the key input unit 24 is operated to specify whether the external memory 27 is a RAM or a ROM. CPU
Reference numeral 23 determines the type of the external memory 27 based on the key input signal from the key input unit 24, selects the optimum access timing according to the type, and performs control according to the characteristics of the memory.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an electronic device using an external memory.

[0002]

[Prior Art]

 2. Description of the Related Art Conventionally, there is known an electronic device in which an external memory including a RAM or a ROM is mounted and used. In such an electronic device, the mounted external memory is accessed by the CPU. FIG. 7 is a diagram showing access timing when an SRAM (static RAM) is used as an external memory in a conventional electronic device. In the case of writing data, that is, in the case of (WRITE) in FIG. 7, the address cannot be changed in the writable state. Therefore, as shown in A of FIG. I am writing. That is, the address change timing is set to be performed in the first pulse period of one cycle. In the case of reading the data, that is, in the case of (READ) in FIG. 7, the address is changed in the first pulse period of one cycle similarly to the writing, and then the reading is performed by the data read clock from the CPU. In this case, when the RAM has a large capacity, it is necessary to take a long time from the chip enable (B in FIG. 7) to the data read clock. If the time from the output of the chip enable to the output of the data read clock is to be shortened, the supply voltage must be set high, otherwise the data read will malfunction.

[0003]

[Problems to be solved by the device]

 By the way, when a ROM is used instead of the RAM, access is conventionally made at the same timing as in the case of the RAM, so that there is a disadvantage that the speed cannot be increased.

The present invention has been made to solve the above problems, and an electronic memory using an external memory that can select the optimum access timing according to the type of the external memory and can perform control in accordance with the characteristics of the external memory. Intended to provide equipment.

[0005]

[Means for Solving the Problems]

 In order to solve the above problems, the present invention comprises a designating means for designating whether the external memory is a RAM or a ROM, and an access means for accessing the external memory at different timing according to the designation of the designating means. Is characterized by.

[0006]

【Example】

 An embodiment of the present invention will be described below with reference to the drawings. Note that this embodiment shows an example applied to an electronic wrist watch.

FIG. 1 is a sectional view showing the internal structure of an electronic wrist watch to which the present invention is applied. In the figure, 1 is a wristwatch case. The wristwatch case 1 is made of, for example, stainless steel or synthetic resin, and a watch glass 2 is mounted on the upper surface thereof. A housing 3 made of synthetic resin is incorporated inside the wristwatch case 1. Below the watch glass 2, a dot matrix type liquid crystal display 4 is supported by a housing 3. Below the liquid crystal display 4, an LS I 5 having an electronic circuit built therein is mounted on a circuit board 6. A battery 7 for power supply is connected to the circuit board 6 through a terminal 8 and an external memory 9 is electrically connected through a connection terminal 10. A detachable back cover 11 is attached below the wristwatch case 1 and is sealed by the back cover 11.

FIG. 2 is a block diagram showing a circuit configuration of the electronic wrist watch. In the figure, reference numeral 21 denotes an oscillation circuit, which oscillates a clock pulse which serves as a reference for various operations and timing. The clock pulse oscillated by the oscillation circuit 21 is supplied to the timing clock generation circuit 22. The timing clock generation circuit 22 generates timing clocks such as various timing signals according to the type of external memory, a reference clock, and a clock signal based on the clock pulse output from the oscillation circuit 21, and supplies the timing clocks to the CPU 23. The CPU 23 performs a timing process for measuring the current time and an operation control process for each unit according to a key input signal from the key input unit 24 in accordance with the timing clock supplied from the timing clock generation circuit 22. The program ROM 25 storing the micro program for is specified and the micro program is read.

The key input unit 24 includes a plurality of push button switches including a mode selection switch 24 a, and outputs a key input signal according to switch operation to the CPU 23.

In addition to the timing clock generation circuit 22, the key input unit 24, and the program ROM 25, the CPU 23 is connected with a RAM 26, an external memory 27 (external memory 9 in FIG. 1), a display character ROM 28, and a display buffer 29. Has been done. The RAM 26 stores various data and is addressed by the CPU 23 to control input / output of data. The external memory 27 is composed of RAM or ROM, is addressed by the CPU 23, and is supplied with a timing clock according to the type of memory to input / output data.

The display character ROM 28 is a memory that stores display character data corresponding to all preset characters. The CPU 23 outputs the display data to the display buffer 29. The display buffer 29 stores the display data and outputs it to the display driver 30. The display driver 30 obtains a display drive signal based on the display data, and drives and controls the display unit 31 composed of the liquid crystal display 4 by the display drive signal to display and output the data.

Next, the memory configuration of the RAM 26 will be described with reference to FIG. As shown in the figure, the RAM 26 includes a display register 26a, a clock register 26b, and a mode register M. The display register 26a is a register for storing the display data displayed on the display unit 31. The clock register 26b is a register for storing current time data counted by the CPU 23, for example, every one second. The mode register M is a register for storing mode data which is sequentially incremented by the operation of the mode selection switch 24a and takes a value of "0" to "2". "M = 0" is a time display mode and "M = 1" is For example, a RAM is used as the external memory 27, and a telephone number mode for storing, reading and displaying a name and a telephone number, "M = 2", for example, a Kanji ROM is used as the external memory 27 and corresponds to an input kana character. This is a translation mode in which kanji data is read from the external memory 27 and displayed.

Next, the operation of the above embodiment will be described with reference to FIG. Normally, the CPU 23 is in the HALT state of step S1 until a key input signal is output from the key input unit 24 or a timing signal is output from the timing clock generation circuit 22.

When the timing signal is output, the timing is determined to be timing in step S1, and the process proceeds to step S2. In the time counting process of step S2, the current time data stored in the time counting register 26b is updated. The process proceeds from step S2 to step S6. In the display processing of step S6, the display data stored in the display register 26a is displayed on the display unit 31. After execution of step S6, the process returns to step S1.

When a push button switch (not shown) is input, the key input unit 24 outputs a key input signal to the CPU 23. As a result, it is determined that the key is present in step S1, and the process proceeds to step S3. In step S3, it is determined whether or not the input switch key is a mode selection switch. If YES, the process proceeds to step S4, and if NO, the process proceeds to step S5.

When the mode selection switch is input, the process proceeds from step S3 to step S4. In step S4, the content of the mode register M is incremented by 1 to change the mode. For example, if the mode selection switch is input in the time display mode "M = 0", the telephone number mode "M = 1" is set, and the mode selection switch is input in the telephone number mode "M = 1". And the translation mode becomes "M = 2". However, when “M = 2” is exceeded, it is reset to “M = 0”. After execution of step S4, the process proceeds to step S6. If NO in step S3, the process proceeds to step S5. In step S5, key processing according to the mode is executed. For example, in the telephone number mode, the input name and telephone number are stored in the external memory 27, and read out and displayed. The Kanji data is read out as described above. After that, it progresses to step S6.

FIG. 5 is a diagram showing access timing when the external memory 27 configured by SRAM is mounted in the telephone number mode. That is, when "M = 1", the access shown in FIG. 5 is performed. In the write operation, the write enable signal WE is once set to the “H” level to bring it into the read state, and during this time, the address data output to the address bus is rewritten to change the address. Next, the write enable signal WE and the chip enable signal CE are set to "L" level, respectively, and the data output to the data bus is written in the SRAM. In the read operation, when the address change is completed, the chip enable signal CE becomes “L” level, the data is output from the SRAM to the data bus, and the data is read into the CPU23 at the time when the data read clock is output. .. These accesses are the same as shown in FIG.

FIG. 6 is a diagram showing access timing when the read-only external memory 27 configured by the mask ROM is attached in the translation mode. That is, in the "M = 2" mode, the chip enable state (A in FIG. 6) is set at the start of one cycle, data is output from the mask ROM to the data bus, and the data read clock is output. Data is read into. That is, when the external ROM 27 is constituted by a ROM, it is not necessary to perform writing, so that the chip enable signal CE is immediately output at the start of one cycle, resulting in speeding up.

In addition, although the example applied to the electronic wrist watch has been described in the above embodiment, the present invention is not limited to this, and the present invention can be widely applied to other electronic devices such as a personal computer and an electronic notebook. Also, an example of a telephone number mode when a RAM is used as the external memory 27 and a translation mode when a ROM is used is shown, but it goes without saying that it can also be applied to the storage and reading of other data. Absent.

[0020]

[Effect of the device]

 According to this invention, the optimum access timing can be selected according to the type of the external memory, control can be performed according to the characteristics of the memory, and faster memory access processing can be executed.

[Brief description of drawings]

FIG. 1 is a sectional view showing an internal configuration of an electronic wrist watch to which the present invention is applied.

FIG. 2 is a block diagram showing a circuit configuration of the electronic wrist watch.

FIG. 3 is a diagram showing a memory configuration.

FIG. 4 is a flowchart showing the overall operation.

FIG. 5 is a timing chart showing SRAM access timing.

FIG. 6 is a timing chart showing mask ROM access timing.

FIG. 7 is a timing chart showing SRAM access timing in a conventional example.

[Explanation of symbols]

 1 ... Wristwatch case 3 ... Liquid crystal display 23 ... CPU 24 ... Key input section 25 ... Program ROM 26 ... RAM 27 ... External memory 31 ... Display section

Claims (1)

[Claims for utility model registration] 1. A designation means for designating whether the external memory is a RAM or a ROM, and an access means for accessing the external memory at different timing according to the designation of the designation means. An electronic device using an external memory characterized by the above.