JPS599938B2 - microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer in which, in addition to an internal ROM, a ROM in which instructions are written can be connected to the outside.

A data memory that stores data on one semiconductor chip (hereinafter abbreviated as LSI), an arithmetic unit that performs arithmetic or logical operations on the data stored in the data memory,
It includes an instruction memory for storing instructions, a program counter for addressing the instruction memory, a decoder for decoding the instructions output from the instruction memory, and various registers for controlling the data memory, arithmetic unit, input/output terminals of the LSI, etc. One-chip microcomputers are incorporated into various electronic devices and put into practical use. This type of microcomputer generally has an internal ROM for writing instructions, but depending on the function, the internal ROM alone is insufficient, and an external ROM is often added. . Conventionally, when connecting an external ROM to a 1-chip microcomputer, the number of bits of the program counter is increased to access the external ROM.
The added part accesses the external ROM. For example, if the number of bits of the program counter is 12 bits, the address specified by bits 0 to 11 (16
Addresses 000 to FFF in base number are used to access the internal ROM, and addresses 1000 to FFFF are used to access the external ROM. According to such an access method, external R
Accessing the OM causes an increase in the number of bits in the program counter, and the increase in the number of bits in the program counter concomitantly increases the number of bits in peripheral registers, such as stack registers that store return addresses from subroutines. This results in an increase in the chip size of the LSI, which increases the price of the LSI and causes a decrease in chip accuracy and yield. The present invention provides a microcomputer that eliminates the drawbacks of the conventional LSI described above, minimizes the increase in the chip size of the LSI, and allows connection of an external ROM. explain.

In Figure 1, the CG forms an oscillation circuit with a crystal resonator or passive elements such as resistors and capacitors connected to terminals 1 and 2 of the LSI, and the CG output of this oscillator is connected to the LSI.
It is supplied as the operation clock frequency of I to each section to be described later to form the operation timing, and is also supplied to the frequency division stage DIV.

The frequency dividing stage DI is composed of 15 stages, and outputs f1 to Fl5 are obtained from each stage of the frequency dividing stage, but in this embodiment, the output Fl
, f3, f, and FlO are derived and supplied to the output frequency control register F, and a desired frequency is derived from the output terminal 22 as an LSI output. ACCl and ACC2 are accumulators consisting of 4-bit general-purpose registers. ALL is an arithmetic unit that executes an arithmetic or logical operation, and in this embodiment, the operation is performed between the accumulator ACCl and the accumulator ACC2, the accumulator ACC, or the accumulator ACC2 and R.
It can be executed between AM (data memory) and accumulator ACC, or between either accumulator ACC2 and ROM (instruction memory). Accumulator A
A flip-flop C connected to CC has a function of holding a carry generated as a result of an operation, and the flip-flop C can be set or reset by a command. Input terminals 3 to 6 are connected to general-purpose registers of the accumulator ACC, and input terminals 3 to 6 are connected to the general-purpose registers of the accumulator ACC.
The signal (data) given to 6 is transferred to general-purpose register AC
Store in Cl. The input/output terminals 7 to 10 are connected to the general-purpose register of the accumulator ACC2, and data signals can be sent and received according to commands. The input/output terminal 12 and the output terminal 13 function as general-purpose output terminals when the LSI functions as a normal one-chip microcomputer, and when an external ROM is added to the LSI as shown in FIG. , terminal 12 serves as an input terminal for instructions, and terminal 13 serves as the input/output terminal 3 to 10 and 12.
It has a function of supplying an access timing signal for writing instructions to and from an external additional memory via the RW connected to the output terminal 13, and provides timing for reading and writing. The ROM is an instruction memory that stores various instructions according to the functions of the microcomputer, and the stored instructions are read out by specifying an address by the program counter PC.

Here, the number of bits of the program counter PC is the number necessary to access the instruction memory ROM provided inside the LSI, without having to increase the number of bits specifically to access the external ROM added as in the conventional device. Designed to the number of bits. ID is an instruction decoder, which has the function of decoding instructions read from the instruction memory ROM or external ROM and giving instructions to each part of the LSI. IG inserted between instruction memory ROM and instruction decoder ID
Is it a gate circuit and the command given to the command decoder ID is output from the command memory ROM inside the LS?
It switches whether to input the external ROM instructions read from terminals 3 to 10 and 12 of the LSI to the instruction decoder ID. As mentioned above, the program counter PC is designed to have the number of bits necessary to access the instruction memory ROM. The configuration and operation of the present invention, which allows the program counter PC to access an external ROM, will be explained using FIG.

In FIG. 3, the micro order B1 given from the instruction memory ROM is "1" when the LSI is powered on.
A signal that goes to a high level sets the initial state of the LSI, as has been conventionally done for this type of LSI.

The micro-order B2 given to the inverter A is output from the instruction memory ROM and gives an instruction to execute the instruction from the external ROM from the next step during the normal operation of the LSII). Nand Gate A
A micro-order B3 which holds the next step and subsequent steps at a high level is outputted through a 4- and D-type flip-flop A5. On the other hand, the micro order B4 is an instruction to execute the instructions in the instruction memory ROM from the next step, and is given to the NOR gate A2 from the instruction decoder ID by an instruction from the external ROM. A6 is a T-type 7-lip flop to which the micro-order B3 is input, and when the micro-order B3 is at f1 high FV level, a signal having a period of Σ of the clock signal φ is output to the AND gate A7 and the AND gate A8. Micro order B5 and micro order B6 are output. In FIG. 3, when micro order B3 becomes W6 high 11 level, it means that an instruction from the external ROM is input to the instruction decoder, and micro orders B5 and B6 are output. FIG. 4 shows the external R
Select terminals 1E0-1E8 to which OM commands are input, or terminal 1 to which internal command memory ROM commands are input.
Controls whether the 10-118 side is selected. That is, external R
When micro order B2 is given as an OM drive command, micro order B5 is 1 high, 11 micro order B6 is 1 low, and the signals given to terminals 1E0 to IE8 to which commands from the external ROM are input are at the Wl level. , output terminal 1. -18 and given to the instruction decoder ID provided at the next stage. That is, as an instruction, the instruction decoder I
D will be given instructions from an external ROM.
On the other hand, in the state where the instruction in the internal instruction memory ROM is executed, micro order B4 becomes 1 high and 51 level, therefore micro order B3 becomes WV low 1 W level, micro order B5 also becomes 1 W low 1 level, and the Instruction 110- from the internal instruction memory ROM inputted by
The 118 side is selected and given to the instruction decoder ID.
That is, the instruction decoder ID is given an instruction output from the internal instruction memory ROM. In the figure, A,6 to A44 are D-type flip-flops. As described above, by switching and controlling with a gate circuit whether an instruction to be read is an instruction from an external ROM or an instruction from an internal instruction memory ROM, a special number of bits can be assigned to the program counter PC. External ROM can be added without increasing the number. In FIG. 1, RAM is a data memory, and data can be exchanged between the two accumulators ACC and ACC2.

Addressing of the data memory RAM is given from register H and register L consisting of 4 bits. Register H specifies the upper 4 bits, and register L specifies the lower 4 bits. In this embodiment, P3 and P4 are both composed of 4-bit registers, and are connected to the accumulators ACCl and A.
Data can be input from either CC2.
Output terminals 14-17 and 18-21 are terminals for outputting the contents of register P3 and register P4, respectively. S
Rl and SR2 are stack registers that hold the contents of the program counter PC.
This register is used to store the return address while the subroutine address is being specified, and is composed of two stages of stack registers. Terminal 24 connects LS to GN
D, and the terminal 25 is connected to the power supply VDD. Output terminals 38 to 44 and 26 to 37 are terminals for connecting numeric display light emitting diodes, etc. Output terminals 38 to 44 output seven types of segment signals, and output terminals 26 to 37 output normal digit signals. A desired digit is displayed by a combination of the segment signal and the segment signal. S connected to the segment output terminal is a 4-bit register for holding display numerical data, and SD is a segment decoder that converts the contents of register S into necessary characters or symbols. Output terminals 27-36
outputs a digit signal for display when the LSI is running normal operations using only the functions within one chip.
When an external additional memory is provided, the address signal of the external ROM is output and the instruction code written to the specified address of the external ROM is given to the LSI through the input/output terminals 3 to 10 and 12. . Output terminal 27~
Switching between the above-mentioned display drive and external memory addressing operation of 36 is performed by the contents of a 4-bit register ST. The contents of the register ST can be rewritten by data transfer from the accumulator ACCl or the accumulator ACC2 according to a command from the ROM. Necessary data from the contents of the register ST is selected by the gate circuit G and outputted from the output terminals 26-37. As described above, according to the present invention, a gate is provided for switching between reading an instruction from an external ROM or an instruction from an internal ROM, and a gate control instruction for reading an instruction from an external ROM is written in advance to form an LS. , an external ROM can be added to a one-chip microcomputer without increasing the number of instruction bits, and unlike conventional devices, there is no need to increase the number of peripheral circuit bits as the number of instruction bits increases, and the chip size can be reduced. To obtain a highly functional microcomputer by minimizing the increase in the size of a one-chip microcomputer, which is extremely limited, and to obtain a microcomputer that can be used in a wide range of applications.

Also, a signal for addressing the external ROM to be added is given using the display device driving output terminal provided on the one-chip microcomputer, and the output terminal of the external ROM is given to the data input of the one-chip microcomputer. Since the address line and data line are configured independently, the external ROM can be directly addressed from the microcomputer, and unlike conventional devices, there is no need for a circuit to temporarily store addresses, resulting in slow operation speed. I have no fear.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcomputer according to the present invention, FIG. 2 is a diagram showing the microcomputer connected to an external ROM, and FIGS. 3 and 4 are detailed block diagrams of the main parts of the microcomputer. ROM: internal instruction memory, PC: program counter,
IG: gate circuit, ID: instruction decoder.

Claims (1)

[Claims] 1 a data memory that stores data, an arithmetic unit that performs arithmetic or logical operations on the data, an instruction memory that stores instructions, a program counter that addresses the instruction memory, a decoder that decodes the output of the instruction memory, and the data memory , a one-chip microcomputer that includes an arithmetic unit and a register that controls input/output terminals of an LSI, etc., and that drives a display device based on an output signal, an output terminal to which an output signal for driving the display device is given, and an external command. A gate circuit for switching and outputting signals read from the external instruction memory or internal instruction memory based on instructions written in the memory and internal instruction memory, and for addressing the external instruction memory output from the gate circuit. and an input terminal connected to an output terminal of the external instruction memory and to which data is supplied. Features a microcomputer.