JPS6043538B2 - Memory-switching circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention makes it possible to use the RAM located in the same address space as the startup ROM after the power is turned on and the execution of the program in the startup ROM is completed. This relates to a memory switching circuit.

Among the CPUs recently used in various industrial fields, Intel's 8080 and 8085, for example, start executing from memory address 0 when the power is turned on.

For this reason, it is necessary that the ROM has at least several bytes starting from the 0th address of the memory, and its contents do not disappear even when the power is turned off. However, the storage capacity of ROM per chip is as small as a water byte, and as large as a storage byte, so even if you use a ROM of a few bytes, it will range from $000 to $07FF in binary numbers. The address space before the address will be exclusively occupied by the startup ROM (so-called boot ROM), and RAM whose memory contents can be freely changed and ROM that stores programs other than the startup program will be placed at addresses after that address. I needed to. However, since the startup ROM as described above is used only once when the power is turned on, there is a problem in that it is extremely inconvenient for a large address space to be occupied by such a rarely used memory. The present invention was made to solve these problems of the conventional example, and after the power is turned on and the execution of the program in the starting ROM is completed, the same ROM as this starting ROM is used. 3. It is an object of the present invention to provide a memory switching circuit capable of writing and reading data to and from a RAM arranged in an address space.

The configuration of the Chigi invention will be described with reference to illustrated embodiments.

Figures 1a and 1b show circuit diagrams of an embodiment of the present invention, in which 1 is a starting ROM (so-called boot ROM), and 2 is a ROM in which data can be read and written freely. It is a RAM that can be used for These ROMs
I and RAM2 have an 8-bit data terminal and an 11-bit address terminal, and the 8-bit data terminal is connected to the eight data buses D of the CPU3. -D7, and the 11-bit address terminal is 1 of CPU3.
6 address buses A. -AO~Al of Al5
Connected to O. By the way, these data buses DO
-D7 or address bus A. -ROM1 and RAM in Al5
If two or more memories like 2 are connected at the same time, data will be confused, so ROM1 and RAM2 each have chip select terminals. is provided, and the memory operates only when this chip select terminal is at L level. Further, the RAM 2 is provided with a write signal terminal W which becomes L level when writing data. 4 is an initial reset circuit that operates when the power is turned on, and the power supply voltage Vcc
When becomes H level, capacitor C is charged via resistor R, and its terminal voltage increases.

As a result, the output of the inverter 5 becomes L level some time after the power is turned on. Therefore, until the level reaches this L level, the reset input R of the flip-flop 6 is temporarily at H level.
Since the level is set, the flip-flop 6 is reset. As a result, the O output of the flip-flop 6 becomes H level, so the NAND gate 7 opens and the ROM1
A chip select signal is sent to the chip select terminal CS. At this time, the Q output of the flip-flop 6 is at L level, so the NAND gate 8 is closed and the RAM
No chip select signal is sent to the second chip select terminal section. Therefore, immediately after the power is turned on, the starting ROM1. selected and the CPU
3 reads out a starting program from address 0 in this ROM1 and executes it. When the execution of the program progresses and a data write signal WT is output to write data to the RAM 2, the NAND gate 9 A set input is input to the set terminal 100 of Flipflop 6 through
As a result, the Q output of flip-flop 6 becomes H level.
? The output becomes L level. Therefore, NAND gate 8
is open and the NAND gate 7 is closed, so a chip select signal is sent only to RAM2, a chip select signal is sent to ROM1, and no chip select signal is sent to ROM1. By the way, the flip-flop 6 is reset only by the output of the initial reset circuit 4, so either press the reset button (not shown) to activate the initial reset circuit 4 again, or turn off the power and then reset it again. The starting ROM1 will not be connected to the CPU 3 unless the power is turned on. Figure 2 is a memory map showing the above operation,
As shown in the figure, the entire address space of CPU3 is from address 0 to $
Of the FFFF addresses, a starting ROM (
In other words, a boot ROM 1 is arranged, so that when the power is turned on, the CPU 3 first executes a starting program in the starting ROM 1. However, this ROM1 blocks-transfers the necessary portion of its own memory contents to other RAM2a as appropriate, and this RAM2a
The CPU jumps to a specific address in RAM 2a and operates the CPU according to the contents stored in the RAM 2a. If you do not want to perform block transfers of data in this way,
In addition to the starting ROM1, another ROM that is always connected to the CPU may be provided in place of the RAM2a. However, as the program progresses, RAM2
When a write control signal W is sent to ROM1, ROM1 becomes C
It is separated from PU3 and replaced with RAM2. Since such a write control signal WT is generally used only for RAM and not for ROM, ROM1 is replaced with RAM2 only after RAM2 is used. It is something that Furthermore, once the write control signal is sent to RAM2, the address space of ROMl is exclusively occupied by RAM2, and ROMl cannot be used unless the power is turned off or reset. It is. The present invention is configured as described above, and includes a starting ROM that can store a starting program;
This startup ROM and a RAM located in the same address space are reset when the power is turned on, and the RAM
Since the chip is selected by the output of the flip-flop set by the write control signal for M, after turning on the power and executing the program in the starting ROM, this starting When using RAM in the same address space as ROM, the first write control signal disconnects the starting ROM from the CPU and switches it to RAM. This has the advantage of preventing the startup ROM, which is only used, from occupying a large address space in the memory, and making effective use of the limited address space.

[Brief explanation of the drawing]

1A and 1B are circuit diagrams of one embodiment of the present invention, and FIG. 2 is a memory map for explaining the operation of the same. 1 is a ROM12, a RAM13 and a CPU16 are flip-flops, and 7 and 8 are NAND gates.

Claims (1)

[Claims] 1 When the power is turned on, a starting R is connected to the CPU that reads instructions from a specific address on the memory and starts execution, and a starting program is written from the above specific address.
OM, a RAM arranged in the same address space as the starting ROM, and a flip-flop that is reset by an initial reset signal when the power is turned on and set by a write control signal for the RAM; A memory switching circuit comprising a switching circuit which sends a chip select signal to a starting ROM when resetting a flip-flop, and sends a chip select signal to the RAM when setting a flip-flop.