JPS5846453A - Memory switching circuit - Google Patents

Abstract

PURPOSE:To utilize address space effectively, by allowing writing to and reading from an RAM located in the same address space with a starting ROM, after the execution of a program of the starting ROM. CONSTITUTION:A chip selection terminal CS' is provided to an ROM1 and an RAM2. The memory operates only when the terminal CS' has a level L. The RAM2 is provided with a signal terminal WT' which goes down to the level L during writing operation. An inverter 5 goes down to the level L after being powered up through an initial resetting circuit 4. An FF6 is reset up to said point of time and its output Q' has a level H, sending a signal to the ROM1. At this time, the output Q has the level L, so no signal is sent to the terminal CS' of the RAM2. Therefore, the ROM1 for starting is selected right after the power source is turned on. Once a write signal WT' is outputted to the RAM2, a set input is supplied to the FF6 and while the output Q goes up to H, the output Q' goes down to L. Consequently, the signal CS' is sent to only the RAM2.

Description

[Detailed Description of the Invention] The present invention is designed so that after the power is turned on and execution of the program processor B in the startup ROM is completed, the RAM located in the same address space as the startup ROM can be used. The present invention relates to a metric switching circuit.

Among CPUs recently used in various industrial fields, Intel's 8080 and 8085, for example, start execution from memory address 0 when the power is turned on. For this reason, it is necessary that the ROM retains the stored contents of at least several bytes starting from address 0 of the memory even when the power is turned off. However, the storage capacity of KROM is about 2 to 1 byte per 1 chip, and a small one is about 8 bytes, so even if you use a 2 byte ROM, it will cost $000 in hexadecimal.
The space from address 0 to $07FF will be exclusively occupied by the startup ROM (so-called default ROM), and the memory contents can be freely changed in RAM and programs other than the startup program. The stored ROM had to be placed at an address after that. However, the above-mentioned starting Figure 2 procedural amendment (voluntary) dated January 9, 19811, case description 1982 Patent Book No. 1449042, title of the invention, seven-way switching circuit3, Relationship with the case of the person making the amendment Patent applicant Location 1048 Oaza Kadoma, Kadoma City, Osaka Name (583) Matsushita Electric Works Co., Ltd. Representative Zen Kamimae - 4, agent Sponsored Figure 1 attached on the attached page It is sufficient to provide another ROM in place of the RAM (2a). As the execution of the program progresses, RAM (ROMFl) is separated from CPU +31 and replaced with RAM (21). The write control signal WT is generally used only for RAM and is not used for ROMK.
ROMf for the first time after using AM+21
l+ is replaced by RAM (21). Also, once the write control signal is sent to RAM (21), the attribution space of RoM (+) is replaced by RAM (21). M (exclusively used by 2j, unless the power is turned off or reset, ROM +11
is no longer available.

The present invention is constructed as described above, and includes a starting ROM that can store a starting number and a ROM for starting.
and a RAM arranged in the same address space are configured to be chip-selected by the output of a flip-flop that is reset when the power is turned on and is set by the write control signal for the RAMK. After executing the program in the starting ROM by inputting the starting ROM, when using a RAM in the same space as the starting ROM, the first write control signal causes the starting ROM to be It is now possible to disconnect from the CPU and switch to RAMK, so 1 at startup.
This has the advantage that the startup ROM, which is only used once, can be prevented from occupying a large address space within the memory, and the limited address space can be used effectively.

4. Brief explanation of the drawings Figures 1 (a) and (b) are circuit diagrams of one embodiment of the present invention, and Figure 2 is a memory map for explaining the operation of the same.
is a ROM, (21 is a RAM, +31 is a flip-flop for the CPU 161, and (7) +81 is a NAND gate.

Agent: Patent Attorney Ishi 1) Chief 7 Figure 2 Procedural Amendment (Voluntary) January 9, 1981 16 Indication of the Case ■ (Japanese Patent Application No. 144904 2, Name of the Invention Meshiri 1) Switching circuit 3, relationship with the case of the person making the amendment Patent applicant Location 1048 Oaza Kadoma, Kadoma City, Osaka Name (583) Matsushita Electric Works Co., Ltd. Representative Yoshi Kamimae - 4, Sponsored by the agent Figure 1 Complete paper Correct as follows.

Claims (1)

[Claims] fil A starting ROM that is connected to a CPU that reads instructions from a specific address on the memory and starts execution when the power is turned on, and a starting ROM in which a starting program is written from the above-mentioned specific address, and a starting ROM for this starting ROM. &RAM, which is arranged in the same address space as &RAM, a flip-flop that is reset by the initial rear 1 seat signal when the power is turned on, and a write control signal for the RAM, and a ROM for starting when the flip-flop is reset.
The memory switching circuit is characterized in that it is provided with a switching circuit for sending a chip select signal to the RAM and a switching circuit for sending a chip select signal to the RAM at the time of flip D selection.