JPS604252A - Semiconductor integrated circuit memory device - Google Patents

Abstract

PURPOSE:To offer the title device of high performance and high capacitance, being sped up and has high reliability, by reducing the wiring resistance of a word line formed of a polycrystalline Si film. CONSTITUTION:The polycrystalline Si film 4 as the word line of an MOS-FET is connected to the first metallic mutual wiring 10 via contact hole C3. It is sufficient that the mutual wiring 10 has a small film thickness of approx. 0.5mum for the use only of reducing the wiring resistance of the word line. The second interlayer insulation film 8 can be made thinner than by the conventional method because of the small film thickness of the mutual wiring 10, and therefore has no possibility of disconnection at the opening of the stepwise part even when the second metallic mutual wiring 11 crosses the first one 10. The second wiring 11 is connected to a polycrystalline Si wiring 3 via contact hole C4 opened through the first interlayer insulation film 5 and the second one 8. Since the word line 4 is backed with the first wiring 10, the propagation speed of the word line is high, and the connection thereof can be performed at any points in arbitrary places according to the length of the line.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a MO8iO
The present invention relates to a semiconductor integrated circuit memory device using eight field effect transistors.

In recent years, semiconductor integrated circuit memory devices using MO8 field effect transistors have become larger in size, and the performance of the devices has improved significantly. In particular, the speed of operation of storage devices has increased significantly. However, new problems have arisen in promoting speed increases. In other words, as the capacity of devices increases, the width of the signal line (word H) for selecting an address within a memory cell becomes smaller, and the distance from the decoder to the far end of the memory cell becomes longer. hand,
The delay in signal propagation speed on word lines has become large. For this reason, the delay time in the word line accounts for a large proportion of the operating speed of the device, which has become a major hindrance to increasing the speed of the device.

Taking the flip-flop memory cell shown in Figure 1 as an example,
To explain, polycrystalline silicon is used as the wiring for the word line W connected to one gate pole of the transistors T1 and T2, and digin l-lines (D, D) intersect with the word line.
Is there aluminum wiring? I was using it. However, 1 Normally, polycrystalline silicon has a layer resistance of about 20 Ω/[j (film thickness: 0.5 μm) and aluminum (layer resistance of about 0.03 Ω
/ [l, film thickness 1.2 μm), which is two orders of magnitude larger than
When the capacity is increased like 64 or 256 bit memory, the signal propagation delay in the word line using polycrystalline silicon is large, and the operating speed of the device becomes slow, making it difficult to increase the speed of the device. .

As one method of reducing the delay time in the word line, conventionally, a two-metal interconnection 4 as shown in FIG.
1η construction is adopted. In other words, mutual arrangement, 1. When forming the ml- metal interconnection 6 (g thickness 1.0 to 12 μm) for i, the first metal interconnection 7 connected to the polycrystalline silicon 4 as a word line is also formed at the same time. next,
As the second interlayer insulating film 8, a vapor grown oxide film (CVD8
i02) (film thickness 1.0μ), a through hole 2) for connecting the first metal interconnect 7 and the second metal interconnect 9 connected to the polycrystalline silicon film 4 is formed. Open the second metal interconnection 9 () film thickness 1.0-1,2
μm). In this way, the polycrystalline silicon film 4 serving as the word line is connected to the second metal interconnection 9 at (iiJ locations) as necessary, and the signal propagation delay in the word line can be suppressed to a small level. .

However, in this conventional structure, the first metal interconnect as a mutual helix. Since a thick film thickness of about 1.0 to 1.2μ is required, CVD Sin can be used as an interlayer insulation trap.
The step coverage and alignment of the first metal interconnection 6 and 7 of the two films 7 is poor, and the second metal interconnection 9 is disconnected or on the verge of disconnection at the step. ，
This caused a decrease in yield and reliability.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a highly reliable, high-speed, high-performance, large-capacity semiconductor integrated circuit storage device.

A feature of the present invention is that it is used as a signal line for selecting an address in a memory cell in a semiconductor integrated circuit storage device having a two-layer metal interconnection formed on the entire surface of a semiconductor substrate on which a predetermined circuit element is mounted. The polycrystalline silicon film of .
Through a first contact hole opened through a first interlayer insulating film.

The second metal interconnect is directly connected to the first metal interconnect at at least two places, and serves as the main interconnect. The contact hole is connected to the internal element through a second contact hole formed through the second interlayer insulating film and the second interlayer insulating film for insulating the second metal interconnection. , in the semiconductor integrated circuit memory device, the film thickness of the first metal interconnection is thinner than that of the second metal interconnection.

An embodiment of a semiconductor integrated circuit device according to the present invention will be described with reference to the drawings. In FIG. 3, a polycrystalline silicon film 4 serving as a word line is connected to a first metal interconnection 10 (film thickness 0.5 μm) via a contact hole (C3). The second metal interconnection 10 is used only for the purpose of lowering the wiring resistance of the word line, so it has a thickness of about 0.5 μm (depending on the case).

A thin J film thickness may be used (it may be less than that). The interlayer insulating film 8 is made thinner than the second glabellar insulating film 8 (1 μm) in the conventional method shown in FIG. be able to. In other words, even with a thickness of about 0.5 μm, the step coverage at the first metal interconnection 100 step portion (opening l) presents a shape with no problem. Even if it crosses, it returns to the step part (0),
There is no risk of disconnection. The second metal interconnect 11 is connected to an internal element (for example, a polycrystalline silicon interconnect 3) through a contact hole (C4) formed through the first interlayer insulating film 5 and the second interlayer insulating film 8. Connected.

According to the above-described structure, the word line formed of the polycrystalline silicon film of the memory cell is backed by the first metal wiring, so that the word line propagation speed is high. Connections can be made at any number of locations depending on the length of the word line. In this way, even if the capacity of the device is increased, the signal propagation delay on the word line can be kept small, and the speed of the device can be increased.

In addition, since the metal wiring number i is formed thinner than the film thickness of the metal wirings P and 2, the thickness of the first metal interconnection of the second metal interconnection as seen in the conventional method is There is no need to worry about wire breakage at the stepped portion. Therefore, the problems of lower yield and lower reliability of the device are also solved.

As described in detail above, according to the present invention, it is possible to realize a highly reliable, high-performance mass storage device with excellent operating speed, and its effects are significant.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a flip-flop memory cell, Figure 2 is a cross-sectional view of a conventional two-layer metal interconnection structure, and Figure 3 is a cross-sectional view of a conventional two-layer metal interconnection structure.
Figure 1 shows two-layer metal mutual arrangement according to an embodiment of the present invention 1J4-6
FIG. In the figure, 1... semiconductor substrate, 2...
... Field oxide film, 3 ... Polycrystalline silicon wiring, 4 ... Polycrystalline silicon wiring (word line), 5 ... First interlayer insulating film, 6 ．． 7.10・
...First metal interconnection, 8...Second interlayer insulating film, 9.11...Second metal interconnection? f, 1
．． (CI), (C3)...First contact hole. (C2)...Through hole, (C4)...
...Second contact hole, (a), (b)...
- step of metal interconnection; It is. Menu 1 individual menu Z @ 11) 3 times 1 bite)

Claims (1)

[Claims] A polycrystalline silicon film is used as a signal line for selecting an address in a memory cell in a semiconductor integrated circuit memory device having two-layer metal interconnections formed on the entire surface of a semiconductor substrate on which predetermined circuit elements are mounted. The first metal interconnect is directly connected to the first metal interconnect at at least two or more locations through the first contact hole formed by tracing the interlayer insulating film of the thread. A second metal interconnect is connected to the second interlayer insulating film through a second contact hole drilled through the second interlayer insulating film for insulating the second metal interconnect. , connected to an internal element, and wherein the film/l of the first metal interconnection is thinner than the second metal interconnection.