JPS6041818A - Timer device mounted on satellite - Google Patents

Abstract

PURPOSE:To improve the reliability by constituting triply a clock signal generating section, a counter section and a program section to obtain an output from a majority decision gate circuit. CONSTITUTION:When a signal for two systems' share from clock signal generating sections 1a-1c formed as a triple system is outputted respectively via majority decision circuits 7a-7c, the majority decision is applied by the 2nd majority decision gate circuit 7d via counter sections 2a-2c and program sections 3a-3c, and a control signal is outputted to a load side by a decode section 8 and an output section 4. The control signal is outputted normally even if one optional system of the input is missing, and no output is given out of the majority decision gate circuit even if any of the systems mulfunctions as runaway or the like, then the high reliability is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a timer device mounted on a satellite and used to ignite and disconnect the satellite at preprogrammed times.

Conventional configurations and their problems Conventional timer devices mounted on satellites include a single type timer device as shown in FIG. 1 or a dual type timer device as shown in FIG. 2.

In the single type timer device shown in FIG. 1, the output of the clock signal generator 1 is multiplied by the counter unit 2, and when the count value reaches a value predetermined by the program unit 3, a control signal is outputted via the output unit 4. This control signal was used to control the ignition or disconnection of the rocket carrying the satellite. In the dual system shown in FIG. 2, the clock signal is generated by two clock signal generators 1a and 1b.
In order to improve reliability, a clock signal switching circuit 5 is provided which switches to the other one of the clock signal outputs when one of the clock signal outputs stops.

However, in the single type timer device shown in FIG. 1, the oscillation of the clock signal generating section 1 may stop or the oscillation frequency may shift, and the counter section 2. Program section 3. Output errors may occur due to non-operation or malfunction of any of the output units 4,
There were problems that caused the satellite to lose sales. Further, even in the dual system shown in FIG. 2, sufficient reliability could not be obtained because the stages after the clock switching circuit 6 were of the single system.

OBJECTS OF THE INVENTION It is an object of the present invention to eliminate the drawbacks of the above-mentioned conventional examples and to provide a highly reliable satellite-mounted timer device.

Structure of the Invention In order to achieve the above object, the present invention has a triple configuration of the clock signal generation section, the counter section, and the program section, which are critical blocks in the timer device, and furthermore, a majority gate circuit is used to generate three systems of signals. High reliability is achieved by configuring the system to output when only two or more systems are input.

Description of examples An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 3, 1a to 1c are clock signal generators, 7
Reference numerals a to 7c are first majority gate circuits, 2a to 2C are counter sections, and 3a to 3C are program sections, all of which are comprised of three sets, forming a triple system. 7d is a second majority gate circuit, 8 is a decoding section, and 4 is an output section.

Next, the operation will be explained. Each of the clock signal generators 1a to 1C outputs an IHz signal, and the first majority circuit 7a outputs an IHz signal.
Input three input systems in parallel to each of ~7C. each first
The majority circuits 78 to 7C are configured to output if two of the three input systems exist. Money plan 1
The input signals of the majority gate circuits 7a to 7C are A, B, and C.
And if the output signal is represented by Fl ~ F3, then Fl
=A・B+A−C+B meeting C・・・・・ （1）F
2=A-B+A@C+B fist C... (2)
F3=A@B+A-C+B-C・・・・・・・・・(3
) is expressed by equations (1) to (3), so if A
Even if there is no input, Fl to F3 are output normally.

On the other hand, if A goes out of control and is input earlier than inputs B and C, Fl to F3 will no longer be output.

The outputs of the first majority circuits 7a to 7C are input to the second majority gate circuit 7d via counter sections 28 to 2c and program sections 3a to 3C, respectively. The program units 3a to 3c convert the second time setting signal of the timer output l signal into a programmable read-only memory (
P-ROM) where the counter section 2 is stored.
By inputting the output signals of a to 2c to the addresses of the P-ROM and inputting their outputs to the second majority gate circuit 7d, even if any one of the inputs is missing, the output signals can be outputted to the timer device. It operates in such a way that it does not affect the operation. Further, even if one of the systems outputs a malfunction due to runaway or the like, the second majority gate circuit d does not output. The output of the second majority gate circuit 7d is decoded by the decoding section 8 and sent as a control signal from the output section 4 to the load side.
Outputs for seconds and controls ignition, cutting, etc.

As described in detail, according to the present invention, the parts where reliability is required are configured in a triple configuration, and the output is determined by majority decision, so that there is no possibility of the clock signal stopping or running out of control.
Furthermore, it has the advantage of ensuring high reliability against malfunctions at each stage.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the structure of a conventional satellite-mounted timer device, and FIG. 3 is a block diagram showing the structure of a satellite-mounted timer device according to an embodiment of the present invention. 1a to 1C...Clock signal generation section, 2a to 2
C...Counter section, 3a-3C...Program section, 4...Output section, 7a-7d...
. . . Majority gate circuit, 8 . . . Decoding section.

Claims (1)

[Claims] a plurality of clock signal generators, a plurality of sets of first majority gate circuits into which the outputs of the plurality of clock signal generators are input, and a clock circuit that receives the outputs of the first majority gate circuits, respectively. a plurality of program sections that receive input via a counter section and output a signal when a preset second setting value is exceeded; and a second majority gate circuit that receives the outputs of the plurality of program sections. A satellite-mounted timer device, comprising: decoding the output of the second majority gate circuit to obtain a timer control signal.