JPH02188040A - Monitoring circuit - Google Patents

Abstract

PURPOSE:To vary the bit rate of a monitoring signal which is inputted to a stand-by system over the entire permissible range of the standard of the stand-by system and to monitor the operation of the stand-by system by varying the frequency of a clock signal which is inputted to a pattern generating circuit. CONSTITUTION:A coincidence detecting circuit 3a controls the clock signal Ca for a specific monitoring time so that the bit rate of a monitoring signal Ma outputted from the pattern generating circuit 2a varies over the entire permissible range of the standard. Namely, the coincidence detecting circuit 3a outputs a frequency control signal FC to a variable clock frequency source 1a to control the frequency of the clock signal Ca. Consequently, the monitoring signal Ma which varies the bit rate over the entire permissible range of the standard is inputted to the stand-by system 4 for the specific monitoring signal and the stand-by system monitoring output signal Na corresponding to the signal Ma is outputted from the stand-by system 4. This monitoring signal Ma and stand-by system monitoring output signal Na and matched, bit by bit, by the coincident detecting circuit 3a to judge that the stand-by system 4 is normal when both signals coincide with each other and abnormal when not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a monitoring circuit in a transmission device having active and standby devices.

[Conventional technology]

FIG. 2 shows a block diagram of a conventional monitoring circuit.

A pattern generation circuit 2, which receives a clock signal C of a fixed frequency from a fixed clock source 1, outputs a monitor signal M having a bit rate determined by the frequency of the clock signal C. This monitor signal M is input to the coincidence detection circuit 3 and the backup system 4 to be monitored. The standby system 4 outputs a standby system monitor output signal N to the coincidence detection circuit 3 in accordance with the input monitor signal M. The coincidence detection circuit 3 performs bit comparison between the input monitor signal M and the standby system monitor output signal N, and if the two signals match, the standby system 4 is considered normal, and if they do not match, the standby system 4 is judged to be abnormal. It had been.

[Problem to be solved by the invention]

However, in the conventional monitoring circuit described above, the fixed clock source 1 can only generate the clock signal C of a fixed frequency, so the bit rate of the monitor signal M1 output from the pattern generation circuit 2 to the backup system 4 is fixed. It has become a thing. Therefore, it has not been possible to confirm the operation of the backup system 4 over the entire standard allowable range of the bit rate of the input signal in the backup system 4.

For example, if the backup system 4 operates normally with the monitor signal M of a predetermined bit rate, but operates abnormally with other bit rates within the allowable range according to the standard, an abnormality in the backup system 4 is recognized. I couldn't do it.

[Means to solve the problem]

The monitoring circuit of this invention has the following means.

(a) A pattern generation circuit that outputs a monitor signal with a bit rate corresponding to the frequency of an input clock signal, (b)
) A coincidence detection circuit that performs bit matching between the monitor signal and the standby system monitor output signal output from the standby system that inputs this monitor signal, and outputs a frequency control signal; Variable clock frequency system.

[Effect]

The frequency of the clock signal output from the variable clock frequency source is changed in accordance with the frequency control signal output from the coincidence detection circuit, and a monitor signal with a set rate corresponding to the frequency of this clock signal is output from the pattern generation circuit to the backup system. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Reference numeral 1a denotes a variable clock frequency source that changes the frequency of the clock signal Ca and outputs it according to the variable clock frequency control signal FC input from the coincidence detection circuit 3a. 2a is a pattern generation circuit that outputs a monitor signal Ma having a bit rate according to the clock signal Ca. The standby system 4 outputs a standby system monitor output signal Na in response to the monitor signal Ma. −
The output circuit 3a performs bit comparison between the standby monitor output signal N& and the monitor signal Ma, and outputs a frequency control signal FC to the variable clock frequency source 1a.

Next, the operation will be explained. - The output circuit 3a controls the clock signal Ca such that the bit rate of the monitor signal Ma output from the pattern generation circuit 2a varies over the entire allowable range according to the standard during a predetermined monitor time. In other words, the output circuit 3& outputs the frequency control signal FC to the variable clock frequency source 1a to generate the clock signal Ca.
control the frequency of As a result, during a predetermined monitoring time, the monitor signal Ma whose bit rate fluctuates over the entire allowable range according to the standard is input to the standby system 4, and the standby system monitor output signal Na corresponding to this monitor signal M& is input to the standby system 4.
is output from. This monitor signal M& and the standby system monitor output signal NIL are bit-verified by the match detection circuit 3a, and if these two signals match, the standby system 4 is normal.
If they do not match, it is determined that the backup system 4 is abnormal.

〔Effect of the invention〕

As explained above, according to the present invention, the bit rate of the monitor signal can be changed by changing the frequency of the clock signal input to the pattern generation circuit, so the bit rate of the monitor signal input to the backup system can be changed. It becomes possible to monitor the operation of this standby system by changing it over the entire standard tolerance range of this standby system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1a @...variable clock frequency source, 2a...pattern generation circuit, 3a...-layout output circuit, Ca
...Facility clock signal, Fc*a**frequency control signal, Ma...@11 monitor signal, Na...standby system monitor output signal.

Claims (1)

[Claims] A pattern generation circuit that outputs a monitor signal with a bit rate corresponding to the frequency of an input clock signal to a backup system, and a backup system monitor that outputs this monitor signal and the backup system to which the monitor signal is input. A monitoring circuit comprising: a coincidence detection circuit that performs bit comparison with an output signal and outputs a frequency control signal; and a variable clock frequency source that changes the frequency of the clock signal in accordance with the frequency control signal.