JPS6373350A - Transfer equipment - Google Patents

Abstract

PURPOSE:To reduce system-down by providing plural channel data parts and plural clock control parts corresponding to the above-mentioned data parts. CONSTITUTION:An error detection circuit 5 is connected so that the error signal 101 of a memory access part 1 and the error signal 102 of a channel control part are supplied to the circuit 5, and the clock control parts 6, 7 and 8 are connected so that the output from the circuit 5 is supplied to them. The circuit 5 and the control parts 7 and 8 are connected in order that the error signal 103 of a channel data part 3 is supplied to them. The access part 1 and a control part 3 are connected in order that the output from the control part 6 is supplied to them and the data part 3 is connected in order that the output from the control part 7 is supplied to it, the data parts are respectively connected in order that the outputs from the control parts are supplied to the data parts. Thus, no far as the control part 2 or the channel data parts 3 and 4 issue faults simultaneously, the system is not down, so that the system-down can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transfer device, and particularly to a transfer device having a plurality of channel data sections.

[Conventional technology]

Conventionally, this type of transfer device has a clock control section 15 for a memory access section 10, a channel control section 11, and a plurality of channel data sections 12, 13, as shown in FIG.
One unit is provided, and the clock of the clock control unit 15 is stopped when an error detection circuit 14 detects a failure in each unit.

[Problem that the invention seeks to solve]

Since the above-mentioned conventional transfer device has only one clock control unit, there is a drawback that even if one unit fails, the clock of the entire device is stopped and the system goes down.

lj Means for Solving Problems] The transfer device of the present invention includes a clock control unit that generates a clock, a memory access unit to which the clock from the clock control unit is supplied, a channel control unit, and a plurality of channel data units. In a transfer device having an error detection circuit that detects errors from each of these sections and controls the clock control section, the error signals of the channel data sections corresponding to the plurality of channel data sections are transmitted to the respective other clock control sections. and the error detection circuit that detects errors in the channel data and controls other clock control units corresponding thereto.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, this embodiment includes a memory access section 1, a channel control section 2, a plurality of channel data sections 3 and 4, a fault detection circuit 5, and a plurality of clock control sections. Error signal 101 of memory access unit 1 and error signal 1.0 of channel control unit
2 are connected to be supplied to the error detection circuit 5, respectively, and the output of the error detection circuit 5 is supplied to the clock control units 6 and 7.
8. The error signal 103 of the channel data section 3 is supplied to the error detection circuit 5 and the clock control section 7, which are connected so as to be supplied to the error detection circuit 5 and the clock control section 8 of the channel data section 4.

The output of the clock control unit 6 is connected to be supplied to the memory access unit 1° and the channel control unit 3.

The output of the clock control section 7 is connected to be supplied to the channel data section 3, and the output of the clock control section 8 is connected to be supplied to the channel data section 4. Next, the operation of the transfer device of this embodiment will be explained. Here, it is assumed that the error signal has a logic of "1" for normal operation and a logic of "0°" when a failure occurs.

=4- First, when a failure occurs in the memory access section 1 or the channel control section 2, the error signal 101 or error signal 102 changes from logic "1" to logic "0". Therefore, the output of the error detection circuit 5 also changes from logic "1'°" to logic "0". When the output of the error detection circuit 5 becomes logic "0", all the outputs of the clock control unit 6, 7.8 become logic "0", and the clock of the entire device stops (the system goes into a down state).6 Next, the channel data When a failure occurs in the section 3, the error signal 103 changes from logic "1" to logic "0", and the output of the clock control section 7 becomes logic "0", and the clock of the channel data section 3 stops.

However, since clocks are normally sent to the other channel data sections 4, the system does not go down.

Also, when a fault occurs in the two channel data sections 3 and 4 at the same time, the error signals 103 and 104 simultaneously change from logic "1" to "0".
'', the error detection circuit simultaneously detects that a failure has occurred, sets the output of the error detection circuit 5 to logic ``0'', stops the clock of the entire device, and brings the system down.

〔Effect of the invention〕

Since the transfer device of the present invention has a plurality of channel data sections and a plurality of corresponding clock control sections, the clock is stopped only in the channel data section where a failure occurs in one of the plurality of channel data sections. This has the effect of making it possible to operate using other channel data sections.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional transfer device.

Claims (1)

[Claims] A clock control unit that generates a clock, a memory access unit, a channel control unit, and a plurality of channel data units to which the clock from the clock control unit is supplied, and detects errors from each of these units and controls the clock control unit. In the transfer device having an error detection circuit for controlling, a plurality of other clock control units each corresponding to the plurality of channel data sections, and supplying an error signal of the channel data section to each of the other clock control sections. and the error detection circuit for detecting an error signal in the channel data section and controlling another clock control section corresponding thereto; A transfer device characterized in that when at least one clock control section becomes a failure, another corresponding clock control section is controlled to enable operation of other channel data sections.