JPS6040152U - デ−タサンプリング回路 - Google Patents
デ−タサンプリング回路Info
- Publication number
- JPS6040152U JPS6040152U JP13064783U JP13064783U JPS6040152U JP S6040152 U JPS6040152 U JP S6040152U JP 13064783 U JP13064783 U JP 13064783U JP 13064783 U JP13064783 U JP 13064783U JP S6040152 U JPS6040152 U JP S6040152U
- Authority
- JP
- Japan
- Prior art keywords
- data
- signal
- counter
- memory
- latch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 title claims description 3
- 238000010586 diagram Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Landscapes
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13064783U JPS6040152U (ja) | 1983-08-24 | 1983-08-24 | デ−タサンプリング回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13064783U JPS6040152U (ja) | 1983-08-24 | 1983-08-24 | デ−タサンプリング回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6040152U true JPS6040152U (ja) | 1985-03-20 |
| JPH0117880Y2 JPH0117880Y2 (enrdf_load_stackoverflow) | 1989-05-24 |
Family
ID=30295630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13064783U Granted JPS6040152U (ja) | 1983-08-24 | 1983-08-24 | デ−タサンプリング回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6040152U (enrdf_load_stackoverflow) |
-
1983
- 1983-08-24 JP JP13064783U patent/JPS6040152U/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0117880Y2 (enrdf_load_stackoverflow) | 1989-05-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6040152U (ja) | デ−タサンプリング回路 | |
| JPH04326138A (ja) | 高速メモリic | |
| JPS6118153B2 (enrdf_load_stackoverflow) | ||
| JPS5941336B2 (ja) | バツフアメモリ装置 | |
| JPS5861540U (ja) | シリアル−パラレル変換回路 | |
| SU1667082A1 (ru) | Устройство мажорировани | |
| SU1376074A1 (ru) | Устройство дл программируемой задержки информации | |
| JPH01302918A (ja) | データ設定回路 | |
| SU1605244A1 (ru) | Устройство дл сопр жени источника и приемника информации | |
| JPS60135869U (ja) | インタリ−ブ用ramの読出し書込みパルス発生回路 | |
| JPH0522363A (ja) | データ受信回路 | |
| JPS60144332U (ja) | シリアルデ−タ入力−パラレルデ−タ出力回路 | |
| JPS6364698A (ja) | 記憶装置 | |
| JPH0215086B2 (enrdf_load_stackoverflow) | ||
| JPH0358737U (enrdf_load_stackoverflow) | ||
| JPS599639U (ja) | コ−ド変換回路 | |
| JPH03175527A (ja) | Fifo制御回路 | |
| JPS58195343U (ja) | キ−入力検出回路 | |
| JPH0172653U (enrdf_load_stackoverflow) | ||
| JPS60100851U (ja) | メモリ−装置 | |
| JPS6271747U (enrdf_load_stackoverflow) | ||
| JPS6079834U (ja) | クロツクパルス検出回路 | |
| JPS61139832A (ja) | ランダムデ−タ発生装置 | |
| JPS5860397U (ja) | シフトレジスタ装置 | |
| JPS61160556U (enrdf_load_stackoverflow) |