JPS6038823A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6038823A
JPS6038823A JP58146923A JP14692383A JPS6038823A JP S6038823 A JPS6038823 A JP S6038823A JP 58146923 A JP58146923 A JP 58146923A JP 14692383 A JP14692383 A JP 14692383A JP S6038823 A JPS6038823 A JP S6038823A
Authority
JP
Japan
Prior art keywords
layer
limited
solder
nicr
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58146923A
Other languages
English (en)
Inventor
Katsuaki Yanagisawa
柳沢　克明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58146923A priority Critical patent/JPS6038823A/ja
Publication of JPS6038823A publication Critical patent/JPS6038823A/ja
Pending legal-status Critical Current

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は半導体装置の裏面電極構造に関するものである
。
トランジスター等の半導体素子の裏面電極、１１４成及
びその後面電極構、或方法は、従来酸々の構造及びその
構ｌ戊方法がとられてｊ＝−９、最も一般的に用いられ
てきた構造としては蒸着等で金（へＵ月漠を形成し、熱
でアロイするものがあげられる。これらのＡｕアロイ素
子全基板等にマウントする場合には、いわゆるハードソ
ルグ（例えばＡｕ片又はＡｕ−８ｂ片等）にて、マウン
）ｋ行うのが常であった。しかし１、上記ハードソルダ
一方式はベレットサイズが大きいとベレットクラック衾
Ｉ、φこしたり、又、ハードソルク”−は全音用いてい
るため、。
その価格が高いという欠点があった。
そこで、近年ｔま、ハードソルダ一方式から、上記欠点
を補９目的でノットソルダー（ｉ′ｂ−８＋＋　−Ａｇ
　）方式が、かなり使われるようにな・っでさた。この
場合ペレット素子の裏面も従来のＡｕＪｕイ構造のもの
をそのま寸ソフトソルダーに使用し、た場合、Ａｕが収
容芒れ裏面抵抗が増加して［７“ま９ため、素子の裏面
構造も変更する必要を生じ一般にオーミック性の点など
を考慮、して、ＩＮ　ｉ層、Ａｕ層合金順次メッキ法ど
で形成したり、１１１層、Ａ、９層、Ａｌ１層を蒸着方
法で順次形成する方法がしはしげ用いられている。こＣ
で従来方法の一例ｆｆ：ｉ＋図に示す。半導体基板１１
の裏面をエツチングしたものに、へ１層１２　、　Ａｇ
層１３．ＡｕＪｍ１４’に順次蒸着し、しかる後、約５
００°０で１０分シンターする。しかし、」１記のよう
な従来構造のものであると、Ｎ１膜は元来あ−Ｉ８す密
層性が良くないため、ハンダにくわれたり、膜ハガレを
秒こしたりし、又、Ｎ＋−へＵ膜のものでは、シンター
により、Ａｕ及びＳｉ　がＮ１中に拡散し、Ａｕ−８ｊ
合金ケ作るため、ソフトソルダーとなじ！：ないなどの
欠点があり、又、Ａｇは酸化しやすいためハンダとなじ
まなくなったりするなどという欠点があった。
そこで本発明は、上記欠点であるハンダとのヌレ性の改
善及び、膜の密層性の向上を目的としたもので、本発明
は、半導体基体の裏面に第一層としてニッケルクロム（
Ｎｉｅｒ）層が形ＩｊＺさｉＬ、Ｎｌｅｒ層上に第２層
として、パラジウム層か形成でれ、第３層として第３の
導体層が形成さす１．ていること′ｆ３：特徴とする半
導体製置である。
以下に本発明を実施例をもとにして、第２図を参照しな
がら、説明する。
Ｓｌ　ウェハー２１の裏Ｉｆｉ金研磨した区、スパッタ
法により、３０００人＋７）　Ｎ　ｉ　（、ｌ　ｒ層２
２　、２ｏｏｏＡの１ｄ７ｉ２３　、４ｏｏｏＡのＡｕ
層２４を順次、形成する。しかる後、約５００υで１０
分シンターする。
以上のようにして本発明により、作られ７′（、半導体
素子は、〕７トソルダーによるマソント金行っても裏面
抵抗の増ＩＡＪもなく、又、１“４ｉＣｒは、′藩着性
が良く、ハンダを７二も強い７ｔめ、ハンダにも強いた
め、ハンダによるクヮレもなく、又、パラジウム層が中
間にはいっているため、シンター熱による１ｓＩＩｃｒ
及びＳｌの拡散も防げ、ハンダとのなじみも、すぐれて
いる。なお本実施？ｌＪ　ｒはＮ１Ｕｒ（１０００Ａ）
　−）’　ｄ　（２（ＪＯＯＡ）Ａｕ　（４０ＵＯＡ）
　（Ｄ例ｆｚあけたが、膜厚はもちろんこの限りではな
く、又、構成方法もスパッタ法ｒあげたが、こＪしもこ
の限りでなく、蒸オｆ方法でも良い。それに膜構成も、
３層とは限らずＮｉＣｒ−Ｐｄ　−Ａ、９−ＡＬ＋％７
；、の４層あるいは、更にそれ以上でも良い。又拡散防
止層もパラジウムとは限らず、同等のものならば良い。
以上のように本発明は、ン７トソルクーーマウント方式
を可能にし、信頼性のすぐれ、がっ、経済的な牛導体装
置金、提供することができる。
【図面の簡単な説明】
第１図は従来技術ｒ示す図てあり、第２図は本発明によ
る実施り１ｊを示す図であ、５゜図中で、１１．２１・
・・・・・８ｉウエハー、１２・・・・・・Ｎｉ層、２
２・・・・・・Ｎ１（ｊｒ層、１３・・・・・・Ａ！Ｉ
ｌ書、２３−−−−−−Ｐａ１ｗ、１４，２４−−・−
Ａｕ、＋＜≧；、全それぞれ示す。 代理人　升理土　日　原　晋

Claims (1)

    【特許請求の範囲】
  1. 牛４体基体の裏面に、第１層としてニッケルクロム層が
    形成され、該ニッケルクロム層上に第２層としてパラジ
    ウム層が形成され、その上に第３層として導体層が形成
    されていること全特徴とする半導体装置。
JP58146923A 1983-08-11 1983-08-11 半導体装置 Pending JPS6038823A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58146923A JPS6038823A (ja) 1983-08-11 1983-08-11 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58146923A JPS6038823A (ja) 1983-08-11 1983-08-11 半導体装置

Publications (1)

Publication Number Publication Date
JPS6038823A true JPS6038823A (ja) 1985-02-28

Family

ID=15418623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58146923A Pending JPS6038823A (ja) 1983-08-11 1983-08-11 半導体装置

Country Status (1)

Country Link
JP (1) JPS6038823A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0253691A2 (en) * 1986-06-17 1988-01-20 Fairchild Semiconductor Corporation Silicon die bonding process
JPS63310552A (ja) * 1987-06-12 1988-12-19 Ushio Inc 白熱電球の製造方法
JPH0351854U (ja) * 1989-09-28 1991-05-20
JPH0414750A (ja) * 1990-05-08 1992-01-20 Koito Mfg Co Ltd ウエッジベースバルブにおけるリード線の封止方法
EP0701281A3 (de) * 1994-09-07 1996-09-11 Heraeus Gmbh W C Substrat mit bondfähiger Beschichtung

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586143A (ja) * 1981-07-02 1983-01-13 Matsushita Electronics Corp 半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586143A (ja) * 1981-07-02 1983-01-13 Matsushita Electronics Corp 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0253691A2 (en) * 1986-06-17 1988-01-20 Fairchild Semiconductor Corporation Silicon die bonding process
JPS63310552A (ja) * 1987-06-12 1988-12-19 Ushio Inc 白熱電球の製造方法
JPH0351854U (ja) * 1989-09-28 1991-05-20
JPH0414750A (ja) * 1990-05-08 1992-01-20 Koito Mfg Co Ltd ウエッジベースバルブにおけるリード線の封止方法
EP0701281A3 (de) * 1994-09-07 1996-09-11 Heraeus Gmbh W C Substrat mit bondfähiger Beschichtung

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