JPS6035567A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase both of the integration density of an MOS-RAM memory cell and the accumulated capacitance by a method wherein the peak position of the profile of impurity concentration of a region doped with the first conductivity type impurity is at a position deeper than a region doped with the second conductivity type impurity. CONSTITUTION:A field oxide film 31 and a p<+> type layer channel stopper 32 are formed by oxidation of a low concentration p type Si substrate 30 by the method of selective oxidation. Next, a thin oxide film 33 is formed on the surface of the Si substrate 30, and thereafter boron ions B<+> are implanted to the Si substrate 30 at a high energy with a photo resist film 34 as a mask, resulting in the formation of a p<+> layer 35. Then, the film 34 is removed after etching of the oxide film 33 with the film 34 as a mask, and the polycrystalline Si 36 of the first layer doped with a high concentration n type impurity is deposited. The reason why the ions B<+> are implanted at a high energy is to obtain a large capacitance of depletion layer. In other words, implantation of the ions at a high energy to the Si and heat treatment allow a deep region in the Si to have the peak.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory cell of a dynamic type MOS random access memory (hereinafter abbreviated as MOS-RAM), and particularly to a memory cell that stores a large amount of signal charge. ? The present invention relates to memory cells with a large stacking capacity and high integration density.

That is, the present invention provides a semiconductor memory with a small memory cell area and a large storage capacity.

[Background of the invention]

There are various forms of MOS-RAM,
The one with the smallest number of transistors is the 11-transistor type MO3-RAM. Conventional 1-transistor type MO8
-RAM, as shown in Fig. 1, is a memory cell consisting of an insulated field effect transistor (hereinafter referred to as MO3+- transistor) for switching and a capacitor of 2 for storing information. Selection is made using a word line made up of an electrode 3 and a data line made up of a diffusion layer 4. Here, 5 is a Si substrate, 6 is an insulating film for isolation between elements (SiO, etc.), and 7 is a gate insulating film (SiO2-AQ2
0. , Si3N, etc.), 8 is the first layer of polycrystalline silicon]
9 is a layer r[M# film (S i O2 etc.), 10
11 is an inversion layer produced by applying a voltage to polycrystalline silicon @8; 2 is polycrystalline silicon 4! (to Game 1), and the capacity M2 is the polycrystalline silicon electrode 8 and the inversion layer 12.
is formed between.

As can be seen from FIG. 1, since the capacitor 2 for storing information is simply two-dimensionally arranged on the same plane as the switching transistor 1, the area of the memory cell is large. Further, in the IMO8+- transistor type RAM, the charge stored in the storage capacitor is proportional to the read voltage, and it is desirable that this read voltage is large in terms of the circuit. Therefore, it is desirable that the storage capacitance be large in order to extend the charge retention time and operate the circuit stably.

However, in order to increase the storage capacity, it is necessary to increase the area of the capacitor section, which reduces the degree of integration.

In JP-A No. 53-4483, the inventors of the present invention have previously reported that by stacking capacitor sections for storing electric charge three-dimensionally, the vertical direction of the element can be used in a succinct manner to increase the integration density and increase the storage capacitance. We have proposed a memory cell with a configuration that increases the 5-tacked C.
5 is a cross-sectional view showing the configuration of an apacitor 5 structure. As shown in FIG. 2, a region adjacent to the diffusion W110 which becomes the source or drain of the field effect transistor 1 in the insulating gate 1 and forming a conductivity type opposite to that of the substrate 5 (an opposite conductivity type region is formed by an impurity layer) is shown in FIG. (Although it may be formed, an inversion layer is used in this example) J,
J, J-], the layer electrode (in this example, the voltage application electrode for forming the inversion layer 11) 8-
1-, an interlayer insulating film 14 for forming a capacitor is provided. Next, a counter electrode 15 is provided thereon, one end of which is connected to the diffusion layer 10.

Thereafter, an interlayer insulating film 9 and an AQ electrode 3 serving as a word line are provided as in the conventional case.

In this way, the electrode 8 and the counter electrode 15 form a capacitor JKc+ via the interlayer insulating film 14, and the storage capacitance is C
I+COX+Cn. , CI is the capacitance formed between the inversion layer 11 and the electric potential f@8 via the Ca oxide film 7b, and CI is the capacitance formed between the inversion layer 11 and the substrate 5 via the depletion layer. .

That is, as shown in FIG.
By adopting a structure in which the electrode 15 is provided on the second side of the f1 pole 8 through the electrode 15, the storage capacitance can be made larger than the conventional CQλ+G o. Urge me,
If conventional memory cell storage capacity and turning values are used, the area 1g of the memory cell can be significantly reduced.

This S '1' C memory allows the insulating film 14 forming the capacitor to be arbitrarily selected by stacking the capacitor → jtAIN on the element, and it is possible to arbitrarily select the insulating film 14 that forms the capacitor.
It has the advantage that N, a film, etc. can be used.

However, in this STC memory, in order to increase the storage capacity, the insulating film 1.4 is used.

When using a thin Sj, 3N film, there is a limit to the increase in storage capacity due to problems such as leakage current. Furthermore, the diffused Ji connected to one electrode of the storage capacitor
Since 10 is in direct contact with the low concentration group 795, what is the external radiation including radiation? There is a loss of charge due to 'f, which becomes a cause of memory malfunction.

In addition, the IMO3+- transistor type RAM shown in FIG.
As an improvement, there is a capacitor-embedded structure proposed in Japanese Patent Application Laid-Open No. 53-34435. As shown in FIG. 3, this capacitor embedded memory has a diffusion layer 13 serving as a storage capacitor and a source or train of an insulated gate field effect 1 to a transistor 1, and a substrate 5 which has the same conductivity as a substrate 5 installed below the diffusion layer 13. This method utilizes a pn junction between the region 16 and the highly impurity-rich region 16.

This capacitive embedded memory has a structure in which part 11 (volume) A is embedded in the substrate, and unlike the discarded gate structure of the memory shown in Fig. 1, multilayer wiring is required because the electrode 8 is not used. It is a small area memory cell.

However, this capacitive embedded memory has a limited capacity in terms of leakage current and breakdown voltage of the pn junction.

Furthermore, since the capacitance per unit area of a pil junction is smaller than that of an oxide film or the like, a large area is required to obtain a large storage capacity, which is disadvantageous in terms of integration.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a device configuration that can increase both the integration density and storage capacity of a MOS-RAM memory cell compared to a conventional MO'5-RAM memory cell.

[Summary of the invention]

The memory cells constituting the MOS-RAM semiconductor memory of the present invention have the insulating film capacitance shown in FIG. 2 and the p
It is a memory cell having a capacitance consisting of two n-junction capacitances, and is a mocha-structured memory cell which is reasonable in terms of increasing the volume and improving the integration density.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

Embodiment 1 FIGS. 4(A) and 4(B) are a sectional view and an equivalent circuit diagram showing a first embodiment of the IMOS transistor type memory cell of the present invention.

In the memory cell shown in FIG. 4, the storage capacitor ff1c is composed of two capacitors, one of which is a nitride film (Si3N4 film) with a high dielectric constant, an alumina film (AQ,
The first layer polycrystalline silicon WJ is
22 and the second WI polycrystalline silicon layer 23.
One is the n''' type WJ formed in the ■] type Si substrate 26.
24 and the p4 type layer 25 between the p11 junction. Further, in the memory cell shown in FIG. 4, addresses Mos+ to transistor 1 are connected to n+ type layers 24 and 27 which serve as sources and drains, and gates #I! ! It is composed of a green film 28 and a gate electrode 29 made of third layer polycrystalline silicon. In FIG. 4, 201 is a data line, 202 is a word line, and 203 is a line that applies a DC bias potential (positive predetermined voltage V a c or ground potential Va ) to the electrode 23.

The two capacitances Ca + * and CJ are MOS shown in Figure 4 (B).
・As shown in the equivalent circuit of RAM memory cell,
Address MO8I - connected in parallel to transistor 1, storage capacity C1l of the entire memory cell is CBIII and C
It becomes the sum with 1I. Two capacitances Cat n and C.

Since they are three-dimensionally formed in the same location, a large storage capacity can be obtained with a small area.

Furthermore, since the n″″ diffusion WJ 24 in contact with the electrode 22 on one side of the storage capacitor is almost covered with the high concentration p-type JfJ 25, there is a potential barrier between the TI″ diffusion layer and the low concentration p-type substrate 26. Therefore, even if charges flow into the memory section due to external noise such as radiation, the existence of a potential barrier prevents the charges from entering the n''' diffusion layer of the storage capacitor section, increasing noise resistance. It turns out.

Assuming that the cell area is 60 .mu.nr and the address MO3 transistor has the same configuration, the storage capacitance values of the MOS/RAMs shown in FIGS. 1 to 4 are as follows.

■ MOS-RAM condition i in Figure 1) 5un-Iff '7 Film thickness of b'f, x=
35 nmjf) Sheet resistance 84 of polycrystalline Si layer 8
007 storage capacity Cs= Cox= ] OOX I 0-4P Ii”
/bit■ MOS・■kuΔM in Figure 2
li thickness ra+n=35 nm Storage capacitance C11=C1llllI+C0X=250x10-'Pl
i'/it ■ MOS-RAM in Figure 3 Conditions x) Impurity concentration of n'' layer 13 = 10''-10''ai-' ji) Impurity concentration of p'' layer 16 = 8X10''am-
' Storage capacity Cs = CJ = 50 x 10- ' P F
/bit■ MOS-RAMC present invention in Fig. 4) Conditions i) Film thickness of S1aN41]121 'l'aIm=
35 n lTl1i) Impurity concentration of n+ layer 24 =
t o 11~10"cm-3 iii) Impurity concentration of P+ layer 25 = 8XiO1'-1 Storage capacitance Ca" Ca i bart C,1=450X
1. Each MO8-RAM'r, AT L/XM, and OS transistor 1 above O-'PF/bi
depth 0.3/jnl provided in the surface area of
, an n'-type source with an impurity concentration of 10" to 10"an-',
Drain region 24.27 (10,4) and film thickness 35n
It consists of a polycrystalline silicon gate electrode 2S) (12) with a Si-1 resistance of 30 Ω/hole and a Si-1 resistor of 30Ω/hole.

Example 2 FIG. 5 (Δ), ([3) shows the MOS-RA of the present invention.
A cross-sectional view of a memory cell and an equivalent circuit diagram of a second embodiment of M are shown.

In the embodiment shown in FIG. 5, similar to the embodiment shown in FIG.
? ? The volumetric capacitance a is composed of both the insulating film capacitance M, Ca*++, and the junction capacitance*CJ. @ green membrane l1tCIIiN is address M OS
It is formed astride the gate 1 of the transistor 1 and the pole 29. Therefore, the surface roughness of the isolated B film capacitor portion becomes large, and the capacitance values Cn and N become large.

n″″ layer 24 and P″′ formed in the silicon substrate 26
The I) n junction capacitance nL C,+ with layer 25 is the same as in the embodiment of FIG. Therefore, in the memory cell of this embodiment, the overall storage capacity f is maintained while maintaining a high integration density.
f, cs can be increased. Under the same conditions as ``Example'', Cs = 650 x 10-' P F
/bit.

Note that 204 is a terminal for applying a potential to the ground 11 to the bias applying electrode (polycrystalline Si) 205 of the element 3#.

In addition, in the memory cell of FIG. 5 (Δ), the goo 1-electrode 29
are formed as the first layer polycrystalline Si, JFJ, and 22.23 are respectively formed as the second layer and the first layer polycrystalline SiK'I.

Embodiment 3 FIGS. 6(Δ) and (13) show a memory cell sectional view 1 equivalent circuit diagram of a MOS-RAM third embodiment of the present invention.

The storage capacity of this memory cell is composed of three capacitors, and the first capacitor is composed of the first layer of polycrystalline silicon 22 and the second layer of polycrystalline silicon 22.
Capacity W'CCar due to insulating film 21 such as nitride film or alumina film sandwiched between layers of polycrystalline silicon 23
n, and the second capacitance is an oxide film 28' between the first layer polycrystalline silicon 22 and the n+ layer 24 in the silicon substrate 26.
The third capacitance is the depletion layer capacitance CJ formed in the silicon substrate 26 by the junction between the n''' scrap 24 and the p'' layer 25. All three capacities are three-dimensionally formed in the same place, with a large storage capacity of 51 ca in a small mount.
can be obtained, and the value of the storage capacitance Cs is the same as that of the conventional memory cell 3 in FIG.
．． A value of 5 times 4 times is obtained.

Note that 206 is a line for setting the polycrystalline Si electrode 22 to the ground potential.

Embodiment 4 FIGS. 7(A) and (+3) show a memory cell sectional view 1 equivalent circuit diagram of a fourth embodiment of the MOS-RAM of the present invention.

This memory cell has a structure with the largest storage capacity among the previous embodiments. The major feature of this memory cell that differs from the aforementioned memory cells is that it is formed within a silicon substrate. , +, + junctions are stacked in multiple stages to form a plurality of them, and the sum of their depletion layer capacitances contributes to the storage capacitance Ca, and the capacitance due to AlIn is added to these capacitances, resulting in a very large storage capacity. capacity will be realized.

This structure can be applied to all of the various types of memory cells mentioned above. The structure shown in FIG. 7 is obtained by applying the structure of this embodiment to the memory cell shown in FIG. 6, and is composed of at least five storage capacitors of 08. That is, the first capacitance is the T1-1 sandwiched between the first layer of polycrystalline silicon 22 and the second layer 11 of polycrystalline silicon 23.
Capacity r+Ca due to insulating film 21 such as Ride film or alumina film
tw, the second capacitance is the capacitance Cox caused by the oxide film 28', etc. between the first layer polycrystalline silicon 22 and the silicon substrate 26, and the third capacitance is " nu depletion layer capacitance CJ r between "/fW24a and p" WI25a, and the fourth capacitance is between p+ layer 25a and n9
The fifth capacitance is the depletion layer capacitance C between the n4 layer 24b and the p+ layer 25b. The multi-stage depletion layer capacitance can be increased within the range permitted by the manufacturing process. 8r bim are connected by an n+ layer 24G with deep diffusion depth j'?
Therefore, each depletion layer capacitance is connected in parallel with all "C".

Therefore, the storage capacitance Ca of the memory cell according to this structure can be very large, 5 to 10 times that of the conventional memory cell shown in FIG. 1, which has the same area but only has an oxide film capacitance.

Example 5 Next, a planar structure of a Mo2-RAM memory cell according to the present invention will be described. FIG. 8 shows one design example of a memory cell according to the present invention, taking the memory cell shown in FIG. 4 as an example. The storage capacitor section is the shaded area in the figure, and the high dielectric constant insulating film storage and l) n
Junction capacitors are stacked three-dimensionally. Therefore, in this design example, the M precision capacitance Ca of the memory cell is 4.5 times as large as that of a conventional memory cell consisting of only oxide film capacitance in the same area, and the operation The ability to stabilize is 1'+J.

Example 6 Next, the H'J fabrication process of a memory cell according to the present invention will be described. We will discuss the case where there is one stage and the case where there are multiple stages of 11" + junctions formed in the silicon method plate. Figure 9 shows the
This is a manufacturing process of a memory cell having the structure shown in FIG. 4 with one stage of +-P+ junctions. A low concentration p-type silicon substrate 3o is oxidized by a selective oxidation method to form a field oxidized IFA (SiO□) 31 with a thickness of 0.5 to ]μII+ and a P1 type layer channel stopper 32 (FIG. 9 (Δ)). ).

Next, 30-50 nm of FIL' oxidized fibers (Sin2
) 33 is formed on the surface of the silicon substrate 30, and then boron ions B+ are deposited using the photoresist film 34 as a mask.
A high energy of 0 to 400 KeV is implanted into the silicon substrate 31 to form a p+ layer 35 of approximately 1-3 x 10'' row 2 (FIG. 9(B)).Next, a thin oxide film (Sin) is implanted using the photoresist film 34 as a mask. , ) 33, the film 34 is removed from the photoresist 1, and the first layer of polycrystalline silicon 36 doped with a high concentration type II impurity is etched by 0.1~
0.3 .mu.m is deposited and then 20-50 nm of a high dielectric constant R@edge film 38, such as a thin T1-Ride H'A or alumina 1138, is deposited on the polycrystalline silicon-1-. In this case, in the region where the polycrystalline silicon 36 and the silicon substrate 30 are in direct contact, the n-type impurity in the polycrystalline silicon diffuses into the silicon crystal plate and an I-type WI 37 is formed (see FIG. 9). C)). Next, the insulating film 38 and the polycrystalline silicon 36 are simultaneously etched using a plasma etching method (FIG. 9(D)). After that, a second layer of polycrystalline silicon 39 containing a high concentration of n-type consumables is deposited with a thickness of 0.2 to 0.4 μm.
A pattern is formed so as to cover the insulating film 38 by photo-etching after the m-deposition (FIG. 9(E)). Next, remove the thin oxide IFJ (Sin,,) 33, and
The oxidation is carried out at a temperature of 1,000° C. to form a thin gate oxide 11'J(SiO,) 40 of 20-50 nm. In this case, since the polycrystalline silicon of the second layer contains a high concentration of type 71 impurity, a thick oxide film (SiO7) 4J of 100 to 200 nrn is formed. Thereafter, the gate electrode 42 is formed using a third layer of polycrystalline silicon or a metal such as aluminum, molybutton, or tungsten.
and using this as a mask, high concentration n is formed in a self-aligned manner.
#412: I'll! Form 77743 (9th
Figure (F)). Then, 0.5-1μ■1 PSG119
+44 is deposited, a contact hole is made, and finally I45 is formed on the aluminum fd (Fig. 9 (0)).The reason for implanting boron ions B4 with high energy in the step of Fig. 9 (13) is , in order to obtain a large depletion layer capacitance. That is, as shown in Fig. 10, if boron ions are implanted into silicon at a high energy of 3 (10 to 400 KaV) and heat treated at 1000°C for about 20 minutes, a distribution like 101 in the figure is obtained. It has a peak in a deep region of about 0.6 μm inside the silicon.

Such p"PJ'l and n'" layers (impurity concentration distribution 1
Compared to the depletion layer capacitance between the p1 layer and the 11+ layer, as shown in distribution 102, which has a peak on the silicon surface, the depletion layer capacitance between the A large depletion layer capacity can be obtained. FIG. 11 shows the applied voltage dependence of the depletion layer capacitance according to the distribution 101 and the depletion layer capacitance according to the distribution 102 in FIG. 10, respectively. ．． 11.2.

Embodiment 7 FIG. 12 shows a manufacturing process of a memory cell in which ++p+ junctions are formed in multiple stages and has the structure shown in FIG. A p0 junction is partially formed on the surface of the low concentration p-type silicon substrate 46 by ion implantation or thermal diffusion. In this case, p''JF147 is formed of boron, and the n1 layer has two regions: a region 48 to which impurities with a small diffusion coefficient such as arsenic or antimony are doped, and a region jtC49 to which impurities with a large diffusion coefficient such as phosphorus are doped. Divided. After that.

A thin oxide film (Sin2) 50 with a thickness of 10 to 50 nm is formed on the surface of the silicon substrate 46, and a resist 11015 is formed on the surface of the silicon substrate 46.
Using 1 as a mask, place 10 boron ions 52 on the surface of 03 layer 48.
12 to 1013 an-" ion implantation (Fig. 12 (Δ)). Next, oxidize ffJ5 of the silicon substrate coating 11i7.
After removing the resist film 51 and the resist film 51, a low concentration p-type silicon layer 53 having an impurity concentration of about 111 m is grown on the surface of the silicon substrate by an epitaxial method. In this case, the boron impurity ion-implanted into the surface of the 03 layer 48 is also doped into the epitaxial p-type layer, forming a groove 54. Furthermore, the +1” layer 49 is doped with impurities with a large diffusion coefficient such as phosphorus.
extends into the epitaxial diagonal layer during epitaxial growth, and nJ55 having a deep diffusion depth is formed (FIG. 12(B)). After that, Selection 41'i! A field oxide film (Sin2
) 56 and a p-type layer channel stopper 57 is formed.

Next, a thin sulfur oxide film (Sin2) of 20-50 nm 58
Formed on the surface of the axial p-type layer, and using the photoresist film 59 as a mask, an n-type impurity 60 such as a phosphor wire is added to
13-1014csn-2 ion implanted n-type layer 61
(Fig. 12(C)). Next, a first shoulder polycrystalline silicon 62 is deposited to a thickness of 0.1 to 0.3 μm, and a high dielectric constant insulating film 63 of 20 to 50 nSN is formed on top of the first polycrystalline silicon 62, for example, a nylonite film (s i , N4) and alumina film (AQ203). After that, 0, 3-0, 4 are attached to the side surface of the polycrystalline silicon 62 using an oxide ball frame.
'5 p tn cover oxidation 11S! (SiO2) 64 is formed (FIG. 12(D)). Next, a bright oxide film (Sin
, ) 58 is removed in part a), the second layer of polycrystalline silicon 65 containing a high concentration of n-type impurities is Q, 2-0.
, 3 μm thick (FIG. 12(E)).

Next, after removing the thin oxide film 58, a thin gate oxide film (Sin) 66u20=50 nm is formed.
100 to 200 n for layered polycrystalline silicon 65-H
A thick oxide VIA (Sin, ) 67 of m is formed. Next, a gate electrode 68 is formed from a third layer of polycrystalline silicon or a metal such as aluminum, molybdenum, or tungsten, and using this as a mask, a high concentration T1 type diffusion layer 69 is formed in a self-aligned manner (the twelfth layer). Figure (F)). Next, 7 layers of PSG film with a thickness of 0.5 to 1.0 μin are deposited, a contact hole is made, and finally an aluminum electrode'/
1 (FIG. 12(G)).

As mentioned above, the present invention allows high i! ! A dynamic memory cell with a large storage capacity can be realized with Tr+ density, and stable operation of a large capacity MO8-RAM is possible.

As described above, in the structure according to the present invention, a memory cell having a large storage capacity with L is obtained, but in order to further increase the signal voltage, it is necessary to maintain the Z1 value of the data 8111.

Embodiment 8 fIS13 The structure shown in FIG. 13 is the structure according to the present invention described in 1- above, with a structure that further reduces the data line capacitance.7 That is, the MOS/RAM memory cell structure shown in FIG. After forming a contact hole in the layer [J of I) S
II! J74 was deposited to a thickness of 0.5 to 1.0 μm, contact holes were opened again, and data lines were formed using Aρ75. With this structure, the PS under the AQ wiring 75
The G film can be made about twice as thick as the conventional structure, and the parasitic capacitance of the All wiring can be reduced by half accordingly.

Therefore, the signal voltage from the memory cell becomes even larger due to the increase in the storage capacity and the decrease in the data line capacitance wall.

〔Effect of the invention〕

As described above, according to the present invention, M
A dynamic memory cell with a large fJ'f capacity can be realized, and stable operation of the MO8-RAM can be achieved.

[Brief explanation of drawings]

1st, 2nd, and 3 are cross-sectional views showing the structure of a conventional MOS/RAM memory cell, flS4. l! ? l+
Figure 5. 6 and 7 are diagrams showing the surface configuration and equivalent circuit of an actual example of the MOS-RAM memory cell of the present invention, and FIG. 8 is a diagram showing an example of the planar pattern of the MOS-RAM memory cell of the present invention. Figure 9 is a cross-sectional view showing an example of the manufacturing process of the MOS/RAM memory cell of the present invention, Figure 10 is a diagram showing the 13 degree distribution of the impurity layer forming the pn junction capacitance, and Figure 11 is the impurity concentration. Figure 12 shows the difference in applied voltage dependence of p11 junction capacitance due to differences in distribution.
Another part of the manufacturing process of OF,・■kuhe P51 memory cell
A cross-sectional view showing 7q; Figure 1 is a MOS-RA of the present invention.
FIG. 7 is a sectional view showing another example of the M memory cell. 20...Field oxide film (S, i02, etc.), 2
1... Insulating film for capacitive part (S i, N,, A Q20
a, etc.), 22° 23... 8 part electrode (polycrystalline silicon R), 24... n'''' type impurity layer, 25..., +
" type impurity layer, 26...■) type silicon substrate, 27.
...n'-shaped i-shaped layer, 28...gate insulating film (S
iOp, etc.), 29...Gate electrode (polycrystalline silicon or metal), 201...Data line, 202...Word line, 203...Bias connection (ground or first (2) second port) 3 m C 4 mouth (A) 6 (B) A no. Applied voltage (Sx IZ (A) (0) 13 Fig.

Claims (1)

[Claims] An insulated gate field effect transistor formed on a first conductivity type semiconductor substrate includes a charge storage capacitor, and the storage capacitor includes a first electrode formed in a stacked manner on the semiconductor substrate;
an insulating container composed of an insulating film and a second electrode; a second conductivity type impurity doped region formed in a surface region of the semiconductor substrate; and a second conductivity type impurity doped region in contact with the second conductivity type impurity doped region. The gate electrode of the insulated gate field effect transistor includes a depletion layer capacitance constituted by a first conductivity type impurity doped region formed at a deeper position than the doped region, and the gate electrode of the insulated gate field effect transistor has the first and second f! A semiconductor formed by a step after the electrode is formed, and wherein the peak position of the impurity concentration distribution in the impurity doped region of the first conductivity type is located at a deeper position than the impurity doped region of the second conductivity type. memory.