GB1591429A

GB1591429A - Fabrication methods for the high capacity ram cell

Info

Publication number: GB1591429A
Application number: GB51332/77A
Authority: GB
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 1976-12-20
Filing date: 1977-12-09
Publication date: 1981-06-24
Also published as: DE2756855A1; JPS5394782A; US4112575A

Description

PATENT SPECIFICATION

( 11) ( 21) Application No 51332/77 ( 22) Filed 9 Dec 1977 ( 31) Convention Application No.

752 598 ( 32) Filed 20 Dec 1976 in ( 33) United States of America (US) ( 44) Complete Specification published 24 June 1981 ( 51) INT CL ' H Ol L 27/10 ( 52) Index at acceptance HIK 11 A 3 11 B 3 11 B 4 l C 1 B 11 C 4 11 D 1 l ID 1 CA 1 FE 1 FF 4 C 11 4 C 14 9 B 1 9 B 1 A 9 D 1 9 N 2 9 N 3 GAB ( 72) Inventors HORN-SEN FU THOMAS C HOLLOWAY AL F TASCH JR.

PALLAB K CHATTERJEE ( 54) FABRICATION METHODS FOR THE HIGH CAPACITY RAM CELL ( 71) We, TEXAS INSTRUMENTS INCORPORATED, a Corporation organized according to the laws of the State of Delaware, United States of America, of 13500 North Central Expressway, Dallas, Texas, United States of America, do hereby declare the invention, for which_ we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to semiconductor memories, and more particularly to binary random access memories (RAM) having an array of improved memory cells.

During the past several years, much time, effort,-and money has gone into the development of high density, low cost memories.

This is because the computer industry has continually demanded more and more storage capacity As a result of this past memory development work, the number of bits of storage per chip has increased from 16 to 16,000 In addition, the cost per bit has been decreased by a factor of approximately 200.

A major reason for this progress has been the development of small, reliable memory cells, Thousands of these cells are formed on a single chip; and the chips are interconnected to form larger memories The cost in the production of semiconductor chips is such that most of the expense is in bonding, packaging, testing, handling, and the like, rather than in the cost of the small chip of silicon which contains the actual circuitry Thus, any circuit which can be contained withn a chip of a given size, for example, 30,000 square mils, will cost about the same as any other By forming large numbers of memory cells in a chip, large economies in the cost per bit can result if reasonable yields are obtained However, as the size of a chin increases, the yield decreases; so that the advantages of larger chip sizes are outweighed by reduction in yields Presently, chips of about 150-250 mils on a side are commonly made in the semiconductor industry Accordingly, it is desirable to reduce the area occupied by 50 each cell.

Three types of cells are currently used in the construction of semiconductor memory chips These memory cell types are called the one transistor cell (-T cell), the double 55 level polysilicon cell (DLP cell), and the charge coupled cell (CC cell) The two former cell types are described in U S Patent 3,387,286 by R H Dennard and U S Patent 3,720,922 by W F Kosonocky, respectively 60 The CC RAM cell is described in British Patent No 1 542288.

As alluded to earlier, the 1-T cell, the DLP cell, and the CC cell each is the product of many years of work and refinement 65 Thus, it could be expected that large improvements in such a developed field are unlikely However, the present invention includes a novel cell-termed a " high capacity" or "hi-C" cell-which has several 70 significant advantages over the prior art.

One important limitation of the 1-T, DLP, and CC cells is that they all have less charge capacity per unit area than is desirable A high charge capacity per unit area 75 is desired because as the number of bits per chip increases, the size of each cell must necessarily decrease Thus the amount of charge that can be stored in each cell decreases And eventually, a point is reached 80 beyond which the cell cannot be reduced further because the amount of charge that the cell can store is indistinguishable from noise Thus, charge capacity per unit area is a fundamental limitation on the minimum 85 cell size.

The 1-T and DLP cells are also deficient in a second parameter which is called leakage current The leakage current is a measure of the quantity of electron-hole 90 pairs that are thermally generated in a cell.

These charge carriers are undesirable because they alter the amount of charge that is stored as information, and eventually they 1 591 429 1 591 429 totally cancel the information charge In order to avoid this cancelling effect, the information charge in the cell must be periodically refreshed at certain minimum intervals The refresh period is inversely proportional to the leakage current in the cell It is an experimentally verified fact that leakage current in the 1-T and DLP cells is typically 3 to 8 times greater than that of the CC cell But on the other hand, charge capacity of the of the CC cell is only approximately half the charge capacity of the 1-T or DLP cells Thus, no single cell type has the best of both parameters.

According to one aspect of the present invention there is provided a method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone, comprising the steps of: forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which define a cell area for each cell of said array, the cells being interconnected by zones comprising bit lines and formed subsequently adjacent one channel stop region; introducing ions of a first conductivity type throughout said cell areas, thereby forming a shallow ion layer throughout each cell area; introducing ions of a second conductivity type throughout said cell areas at a level lying below said shallow ion layers, thereby forming a deep ion layer throughout each cell area; disposing a first insulating layer on said first surface overlying said cell areas; forming a patterned layer of conductive material in said insulating layer to define a storage gate region partially overlying each of said cell areas and spaced apart from said one channel stop region; removing from each of said cell areas, the portions of said shallow ion layer lying between said storage gate regions and one channel stop region; introducing ions of said first conductivity type, throughout the portion of each cell area lying between said storage gate regions and said one channel stop regions, at approximately the same depth and concentration as said deep ion layer lying therein; disposing a second insulating layer at least on said storage gate regions; forming a patterned layer of conductive material on said second insulating layer to define a transfer gate region partially overlying and spaced from said storage gate region in each of said cell areas; and introducing ions of said first conductivity type into each of said cell areas between said transfer gate regions and said one channel stop regions so as to define said bit line zones.

According to another aspect of the present invention there is provided a method of constructing an array of high capacity of memory cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone, comprising the steps of: forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions 70 which define a cell area for each cell of said array, the cells being interconnected by zones comprising bit lines and formed subsequently adjacent one channel stop region; disposing a first insulating layer on said first surface 75 overlying said cell areas; forming a patterned layer of conductive material on said first insulating layer to define transfer gate regions overlying a portion of each of said cell areas and spaced apart from said one 80 channel stop region; introducing ions of a first conductivity type, throughout the portion of said cell areas not covered by said transfer -gate regions, thereby forming a shallow ion layer in each of said cell areas; 85 disposing a second insulating layer at least on said transfer gate regions; exposing said substrate to a high temperature atmosphere to diffuse said shallow ion layer laterally and partially under said transfer gate regions 90 and subsequently introducing ions of a second conductivity type throughout said portions of said cell areas not covered by said transfer gate regions, at a level lying below said shallow ion layers, thereby form 95 ing in each cell area a deep ion layer lying laterally within said shallow ion layer of that cell area; forming a patterned layer of conductive material on said second insulating layer to define a storage gate region 100 partially overlying and spaced from said transfer gate region in each of said cell areas; and introducing ions of said first conductivity type into each of said cell areas between said transfer gate regions and said 105 one channel stop regions so as to define said bit line zones.

According to another aspect of the present invention there is provided a method of constructing an array of high capacity memory 110 cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone, comprising the steps of:

forming in a first surface of a semiconductor substrate, channel stop regions and over 115 lying field insulator regions which define a cell area for each cell of said array, the cells being interconnected by zones comprising bit lines and formed subsequently adjacent one channel stop region; introducing 120 ions of a first conductivity type, throughout said cell areas, thereby forming a shallow ion layer throughout each of said cell areas; disposing a first insulating layer on said first surface overlying said cell areas; masking 125 each of said cell areas so as to expose a storage region lying within each of said cell areas and spaced anart from said one channel stop region; introducing ions of a second conductivity type into each of said 130 1 591 429 storage regions at a level lying below said shallow ion layers to form a deep ion layer in each of said cell areas; forming a patterned layer of conductive material on said first insulating layer to define a storage gate region overlying each of said storage regions; removing the portion of said shallow ion layers lying between said storage gate regions and said one channel stop region; disposing a second insulating layer at least on said storage gate regions; forming a patterned layer of conductive material on said second insulating layer to define a transfer gate region partially overlying and spaced from said storage gate region in each of said cell areas; and introducing ions of said first conductivity type into each of said cell areas between said transfer gate regions and said one channel stop regions so as to define said bit line zones.

According to another aspect of the present invention there is provided a method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone, comprising the steps of: forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which define a cell area for each cell of said array, the cells being interconnected by zones comprising bit lines and formed subsequently adjacent one channel stop region; masking each of said cell areas so as to expose a storage region lying therein and spaced apart from said one channel stop region; introducing ions of a first conductivity type throughout each of said storage regions thereby forming a shallow ion layer in each cell area; masking each of said cell areas so as to expose said storage region except in the area lying closest to said spaced apart one channel stop region; introducing ions of a second conductivity type throughout said partially exposed storage regions and at a level lying below said shallow ion layer lying therein to form a deep ion layer in each of said cell areas; disposing a first insulating layer on said first surface overlying said cell areas; forming a patterned layer of conductive material on said first insulating layer to define a storage gate region overlying said storage region of each of said cell areas; disposing a second insulating layer at least on said storage gate regions; forming a patterned layer of conductive material on said second insulating layer to define a transfer gate region partially overlying and spaced from said storage gate region in each of said cell areas; and introducing ions of said first conductivity type into each of said cell areas between said transfer gate regions and said one channel stop regions so as to define said bit line zones.

According to another aspect of the present invention there is provided a method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS capacitor sharing a common 70 semiconductor zone, comprising the steps of: forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which define a cell area for each cell of said array, 75 the cells being interconnected by zones comprising bit lines and formed subsequently adjacent one channel stop region; masking each of -said -cell areas so as to expose a storage region lying therein and spaced apart 80 from said one channel stop region; introducing ions of a first conductivity type throughout each of said storage regions, thereby forming a shallow ion layer lying therein in each cell area; introducing ions 85 of a second conductivity type throughout said storage regions at a level below said shallow ion layer lying therein, thereby forming a deep ion layer in each cell area; disposing a first insulating layer on said 90 first surface overlying said cell areas; forming a patterned layer of conductive material on said first insulating layer to define a storage gate region for each of said cell areas lying above said storage regions, and 95 to further define a transfer gate region for each of said cell areas lying between and spaced apart from said storage gate regions and said one channel stop regions; and introducing ions of said first conductivity 100 type into the portions of each of said cell areas lying between said storage gate region and said transfer gate region and between said transfer gate region and said one channel stop region 105 The invention itself, as well as other features and advantages thereof will best be understood by reference to the following detailed description of particular exemplary embodiments, read in conjunction with the 110 accompanying drawings wherein:

FIGURE 1 is a schematic diagram of an array of Hi-C memory cells; FIGURE 2 is a circuit digram of two memory cells which are contained in the 115 array of FIGURE 1; FIGURE 3 is a greatly enlarged crosssectional view of one of the memory cells of FIGURE 2; FIGURE 4 is a greatly enlarged top view 120.

of one of the memory cells of FIGURE 2; FIGURES 5 a-5 j are cross-sectional: views of one cell taken at various steps in a first construction process; FIGURES 6 a-6 j are cross-sectional views 125 taken through one cell at various steps in another construction process; FIGURES 7 a-7 e are cross-sectional views of one cell taken at various steps in still another construction process; 130) 1 591 429 FIGURES 8 a-8 e are cross-sectional views of one cell taken at various stages of a process which is a modification of the process illustrated in FIGURES 7 a-7 e.

FIGURES 9 a-9 e are cross-sectional views taken through one cell at various stages in still another construction process; FIGURES l Oa-l Oc are cross-sectional views taken through one cell of a process which is a modification of that illustrated in FIGURES 9 a-9 e; and FIGURES lla-lle are cross-sectional views taken through a second embodiment of one Hi-C cell of various steps in the construction process.

Referring now to FIGURE 1, a schematic diagram shows an array 11 of Hi-C memory cells Array 11 is used as part of a memory system as described and claimed in copending British patent application Serial No 44772/77 (Serial No 1 591 428).

Each Hi-C memory cell 30 has a transfer gate 41 that is used to address the cell.

The transfer gate selectively couples to one of several " row" or " word " lines XO-X 127 All the cells that are coupled to a particular row line are selected when the voltage on that line is in one state; and conversely, the same cells are deselected when the voltage on the same row line is in another state For example, one preferred embodiment of the invention utilizes Nchannel memory cells; and in that embodiment, the cells coupled to a particular row line are addressed by raising the voltage on that row line to + 12 volts, and the cells are deselected by lowering the same row line voltage to ground.

Each Hi-C cell 30 also has an input-output region 42 This region of the cell is coupled to one of several bit lines b O-b 127 or h O'b 127 ' The voltage on bit line pairs b O-b O', bl-bl', etc are generally the complement of each other The bit lines selectively couple to one of the sense amplifiers 16 and then to signal line 24 through transistors 31 Each column line couples to the gate of a selected one of transistors 31; and therefore, by increasing the voltage on one particular column line (in the case of N-channel transistors for example) line 26 will be interconnected to the corresponding bit line.

During a read operation, each of the bit lines is precharged to some voltage that is intermediate to a " 1 " or " O " level Then a selection voltage is applied to the addressed row line In response, all the cells that are coupled to that row line dump the charge they have stored as information onto their corresponding bit line The sense amplifiers sense this charge, and in response, generate a full " 1 " or " O " voltage level on the bit lines A selection voltage is then applied to one of the column lines; and this gates the " 1 " or " O " of the corresponding bit line onto signal line 24 This sequence is reversed for a write operation That is, I/O buffer 17 generates a voltage on signal lead 24 Then a selection voltage is applied to one column line; and this gates the " 1 " 70 or " O " voltage from lead 24 to the corresponding bit line Then a selection voltage is applied to one row line In response, a quantum of charge representing either a " 1 " or " O " is stored in the selected cell 75 Referring next to FIGURE 2 a circuit diagram of two of the Hi-C memory cells in the array of FIGURE 1 is illustrated In this figure, the labeling on the bit lines is shown as b O, bl; and the row line is shown 80 as XO Note however, that the circuit diagram for the other memory cells in array 11 is identical to this figure except for the labeling.

The circuit of FIGURE 2 is comprised 85 of an insulated gate field effect transistor 40, an MOS capacitor 50, and a PN junction depletion capacitor 55 Inputloutput region 42 of the cell is provided by the source of transistor 40 The drain 43, of transistor 40 90 couples to a node N; and node N couples to a plate 53 of capacitor 50, and to a plate 56 of capacitor 55 A fixed voltage V.

is applied to a second plate 51 of capacitor 50; while the second plate 57 of capacitor 55 95 is connected to the substrate bias voltage Vbb.

Row line XO couples to the transfer gates 41 of transistors 40 Therefore, by selectively raising or lowering the voltage on the row 100 line, transistors 40 turn on and turn off.

When transistor 40 is on, capacitors 50 and charge node N to the voltage level of the bit line; and when transistor 40 is off, the charge in capacitors 50 and 55 remains un 105 changed The quantity of charge in capacitors 50 and 55 (the voltage at node N) represents the information stored in the memory cells.

To understand the significance of the Hi-C 110 RAM cell concept it is important to emphasize that the charge in cell 30 is not only stored on MOS capacitor 50, but that it is also stored on depletion capacitor 55 In the past, depletion capacitor 55 has been 115 neglected because for conventional substrate dopings (e g 10 ions/cm 2) of MOS RAM cells, the depletion capacitance is approximately 10 times smaller than the MOS capacitance And in the past, nobody had 120 successfully found a way to utilize the depletion capacitance to increase the amount of charge that could be stored in the cell.

The depletion capacitance can be increased by increasing the substrate doping in the 125 region which forms capacitors 50 and 55.

For example a P-type implant could be added to a P-type substrate However, this increased substrate doping also causes the voltage swings which occur at node N to 130 1 591 429 be reduced And this, in turn, causes the charge capacity of the cell to actually be reduced This fact has previously been documented See for example an article by A F Tasch, Jr in the IEEE Journal of Solid-State Circuits for February 1976.

However, if a shallow implant (at or very near the Si O 2-Si interface) of conductivity type opposite to the substrate is also added, the flatband voltage in the storage region is shifted in the negative direction This then allows the potential of node N to maintain its full original swing while at the same time increasing the depletion capacitance As a result, the charge capacity of the cell may be increased by as much as 100 % This is an important aspect of the Hi-C cell.

Referring next to FIGURES 3 and 4, the detailed physical structure of one preferred embodiment of the Hi-C memory cells is illustrated In these figures, the actual size of the cell is greatly enlarged FIGURE 3 is a cross-sectional view, taken along line a-a in FIGURE 4 This cross-section cuts through one Hi-C memory cell, and exposes all the components of the cell Ions in the various doped regions are labeled in FIGURE 3 for an N-channel cell However, the structure could easily be modified to provide a P-channel cell as another embodiment Additionally, these ions will be referred' to as implants; however, other methods (e g diffusions) may be used to introduce the ions into the various regions.

The Hi-C memory cell array is formed by utilizing a P-type semiconductor substrate This substrate has a surface 72 near which several elements of each memory cell are formed The boundary of each cell area has a rectangular shape and is open on one end This boundary is defined by field oxide regions 78 a and 78 b, and the corresponding channel stop implant regions 71 a and 71 b An N + region 73 lies near surface 72 and is adjacent to the open end of the cell boundary Region 73 forms bit line bl and transistor source 42 Several bit lines selectively interconnect the cells, and their boundary is also formed by field oxide regions 78 a and 78 b, and channel stop regions 71 a and 71 b.

A storage region 74 fills most of the space within the cell boundary and is spaced apart from region 73 This storage region is formed by two ion implants 75 and 76 near surface 72 Region 74 forms capacitor 55, plate 53 of capacitor 50, and drain 43.

Implant 75 is of an N-type material and it lies relatively near surface 72 The other implant 76 of the pair is of a P-type material, and it lies beneath the N-type implant In the drain 43 area the P implant either coincides laterally with or lies.

laterally within the N-type implants This avoids potential barriers to charge flow between storage region 74 and bit line bl.

Further structural details of storage implant region 74 will be given following this overall description of FIGURES 3 and 4.

An MOS transfer channel or transfer re 70 gion 77 is formed in surface 72 between N+ region 73 and storage region 74 as a result of the substrate being a P-type material This transfer region is not implanted An insulating layer 78 overlies 75 substrate surface 72 In one embodiment, insulating layer 78 is formed of Si 02 and is about l OO 1 A thick Storage gate 51 overlies insulating layer 78 above storage region 74; and transfer gate 41 overlies insulating layer 80 78 above transfer region 77 and partially overlies storage gate 51 Gates 41 and 51 are comprised of a conductive material, such as a polysilicon or a metal for example; and they are about 3000 A-8000 A thick 85 FIGURE 4 is a top view of two Hi-C memory cells that are arranged in accordance with the circuit diagram of FIGURE 2, and the cross-sectional view of FIGURE 3 The various regions illustrated in 90 FIGURE 4 lie on one of three levels as previously described Components lying on the lowest layer are enclosed by lines 61.

These components include the bit lines, b O and bl, the transistor sources 42, the 95 transistor -drains 43, the transfer region 77 between the source and drain regions, and the storage region 74 with the double level implants The perimeter of these elements is defined by field oxide regions 78 A and 100

78 B; and channel stops 71 A and 71 B. The components lying on the second level are enclosed by lines 62 A and 62 B A thin insulating layer 78; of Sio 2 for example, separates the first and second levels The 105 area enclosed by lines 62 A forms storage gate 51 and storage line 52 Thus, in this configuration, storage gate 51 and storage line 52 are physically integrated into one area This area is then connected to a 110 fixed voltage source V Similarly, the area enclosed by line 62 B forms the transfer gates 41 of transistors 40.

Row line X lies on the third level, and it occupies the area enclosed by line 63 115 The second oxide layer 79 ( 6000-7000 A) separates the second and third levels Electrical connection is made between row line XO and gates 41 by a contact 45 This contact penetrates the oxide separating the 120 second and third layers.

Of particular importance in this invention are the structural details of storage region 74 There, the P-type implant (boron for example) is made to a depth of about 125 2000 A-10,OOA from surface 72; and the N-type implant (arsenic for example) is made to a depth of about 100-500 A Note that these implants actually have a Gaussian distribution in surface 72 and therefore 130 1 591429 these numbers define the depth at which the distribution peaks occur.

Boron typically is used as the deeper implant, and the implant operation is performed by an ion-implant machine This implant may be made into the bare silicon surface 72 before insulating layer 78 is grown Or alternatively, it can be made directly through insulating layer 78 after the layer is formed In this latter case, the ionimplant is made at approximately 130 Key.

The dose in the silicon typically ranges from 1-8 x 10 '2 ions/cm 2.

The shallow implant typically is arsenic or antimony Other elements such as phosphorus are also acceptable, but arsenic or antimony are typically used because they have a heavy mass and diffuse slowly.

Therefore, they remain at or very near surface 72 during subsequent fabrication steps which are required to form the cell and any associated on-chip circuitry.

Arsenic or antimony can be implanted directly into the bare surface 72 before insulating layer 78 is formed This process uses an implant energy of approximately 10 Key to 50 Key Alternatively, these implants can be made through insulating layer 78 after it is formed One way to do this is to use a very high implant energy As an example, approximately 300 Key may be required The high energy is required due to the heavy mass of the ions.

Alternatively, a conveniently lower implant energy can be used which will place most of the dopants within insulating layer 78.

The concentration of these dopants is chosen so that the desired amount will subsequently diffuse from insulating layer 78 into surface region 72 during the remaining steps of fabrication As an example of this approach, arsenic may be implanted into 1000 A of gate oxide at 105 Key The concentration is typically 1-8 x 101 ions / cm' The amount of arsenic which subsequently diffuses into surface 72 ranges from 1-6 x 10 '2 ions/cm 2.

Referring now to FIGURES 5 a-5 j a method for constructing the array 11 of the above described Hi-C memory cells is illustrated These figures illustrate crosssectional views of one cell taken at various steps in the construction process This one cell pattern is the basic pattern of the entirearray Therefore, the pattern need only be repeated to construct the entire array.

Referring now to FIGURES Sa-5 e, the initial steps of the construction process are illustrated The purpose of these initial steps is to form the perimeter of the cells (i.e, to define the cell area) and the perimeter of the interconnecting bit lines As a first step, a silicon dioxide layer 81 is formed on surface 72 of substrate 70 Layer 81 is approximately 1000 A thick It is formed by exposing the silicon substrate to an oxidizing atmosphere at approximately 10000 C Next a silicon nitride layer 82 is formed on top of layer 81 Layer 82 is approximately 1000 A thick; and it is formed 70 by exposing the substrate 70 to an atmosphere containing silane and ammonia.

Then a layer 83 of photoresist is deposited on top of the silicon nitride layer 82 The photoresist may be of a type called Kodak 75 Metal Etch resist as an example.

The next several steps form the field oxide regions 78 A and 78 B, and the corresponding channel'stops' 71 A and 71 B To this end, the photoresist is 'exposed to ultra 80 violet light through a mask having a pattern of the desired field oxide-channel stop pattern The photoresist is then developed leaving photoresist regions 84 as illustrated in FIGURE 5 b 85 The slice is next subjected to a selective etchant (wet chemical, plasma, or ion mill) which will remove the silicon nitride in the areas where the photoresist has been removed Thus, only areas 85 of the silicon 90 nitride remain after this etching step The result is illustrated in FIGURE 5 c Next, a P-type implant is made through the exposed oxide layer to form channel stop regions 71 A and 71 B This implant step may 95 be performed with boron ions at approximately 100 Key The dosage of these atoms is typically ( 0 1-1 0) x 1013 ions/cm 2.

Next, photoresist layer 83 is removed by an appropriate clean-up step and then field 100 oxide regions 78 A and 78 B are grown The latter is performed by exposing the slice to an oxidation operation The oxidation operation involves exposing the slice to steam at approximately 900-1000 C for 105 several hours During this operation, the nitride layer 85 masks the oxidation where it exists The oxide that is formed during this process is approximately 3000 A-10,OOOA thick And it penetrates the surface of the 110 silicon to a depth of approximately 15002500 A However, the original P+ regions 71 A and 71 B are only partially consumed, and the remainder diffuse ahead of the oxidation front The result of this operation is 115 illustrated in FIGURE 5 d.

Then the nitride layer 85 is removed by an etchant, such as phosphoric acid And next, oxide layer 81 is removed by another etchant, such as hydrogen fluoride This 120 completes the formation of the cells' perimeter The result is illustrated in FIGURE Se.

Next, the initial steps in forming storage region 74 are performed To this end the 125 entire area enclosed by field oxide 78 A and field oxide 78 B is implanted twice The two implants consist of a shallow ion implant and a deep ion implant 76 These implants are opposite in conductivity type 130 1 591429 to each other The implantation is made with an ion implant machine The Gaussian distribution peak of the deep implant occurs within 1500-10,000 A from surface 72 And the concentration level of the implanted deep ions is within 1-40 X '2 ions/cm 2 During implantation, portions of the deep ions straggle laterally from each cell area to the adjacent channel stop regions This results in a potential barrier around each cell And this potential barrier prevents leakage charge that is generated in the field oxide regions from being collected in the cells' storage regions Thus leakage current of the cell is reduced As an example of an acceptable P-type ion, boron may be used Shallow ion implant 75 has a Gaussian distribution peak which occurs within 500 A from surface 72 The concentration level of these ions is within 1-9 X 1012 ions/cm 2 As an example of an acceptable N-type ion, arsenic or antimony may be used These ions have a heavy mass, and as a result they are preferred because they do not diffuse rapidly in silicon at elevated temperatures, and do not penetrate deeply into silicon when implanted However other N-type dopant material, such as phosphorus, is also acceptable.

The next several steps form storage gate 51 First, gate oxide layer 78 is thermally grown over the entire surface of the slice.

This oxide layer is approximately 500l OOOA thick (Note that the above described shallow implant step may be performed through this oxide layer after it is formed, by using a higher implant energy) Next a polysilicon layer 86 is formed on top of oxide layer 78 Polysilicon layer 86 also covers the entire surface of the slice It is approximately 3000-5000 A thick Polysilicon layer 86 is then heavily doped by an N+ ion implant or diffusion in order to make it a highly conductive electrode Next, a layer of oxide 79 a may be thermally grown or deposited over polysilicon layer 86 This is an optical step; and it is performed only if oxide layer 79 is desired to be relatively thick between storage gate electrode 51 and transfer gate electrode 41 Then, a photoresist layer 87 is deposited on top of polysilicon layer 86 (or oxide layer 79 a if it is put down) This photoresist also covers the entire surface of the slice The result of these steps is illustrated in FIGURE 5 g.

The photoresist is then masked according to storage gate 51 Then, the masked slice is exposed to ultraviolet light, and the photoresist is developed Polysilicon layer 86 is then selectively etched, with the result that storage gate 51 is formed, as shown in FIGURE Sh.

The next several steps form transfer region 77 First, with photoresist 87 remaining over storage gate 51, an etch is made in region 88 Region 88 fills the space between field oxide 78 A and storage gate 51 as illustrated in FIGURE Si This etch removes the oxide and also removes approximately A-1 O,OOOA of the silicon in region 88 70 By etching the silicon, the shallow implant lying in region 88 is removed The oxide etch is made with a substance which will not attack the polysilicon of the storage gate 51 and thus the etch is self-aligned to 75 storage gate 51 and field oxide 78 A.

Next ions 89 are deeply implanted into region 88 These ions 89 have a conductivity type opposite to that of the previously described ions 76 Thus, ions 89 and ions 80 76 cancel each other within region 88 And the net result is the same as if little or no ion implant had been made In addition, due to the high energy required to perform this implant, the ions 89 straggle laterally 85 into the region lying slightly under storage gate 51 The result is that a small potential well is created at the interface of storage region 74 and transfer region 77 due to a slight excess of N-type ions in the straggle 90 region This is important because a potential well, as opposed to a potential barrier, will not reduce the charge capacity of storage region 74 The result of these steps is illustrated in FIGURE 5 i 95 Next transfer gate 41 and region 73 are formed as follows First, oxide layer 79 is formed over the entire surface of the slice.

Layer 79 is thermally grown and may be approximately 300-1000 A thick over region 100 88 It will, of course, be thicker over storage gate 51 if oxide layer 79 a was formed Next a polysilicon layer, which will be patterned to form transfer gate 41, is deposited over the entire surface on top of 105 oxide layer 79 The polysilicon is then covered with photoresist The photoresist is then etched to form transfer gate 41.

Then, the oxide layer 79 lying above region 73 is selectively etched Region 73 is then 110 implanted or diffused using an N-type ion to form bit line bl and transistor source 42.

This step also dopes the polysilicon comprising transfer gate 41, thereby making the transfer gate a highly conductive electrode 115 The result of these steps is shown in FIGURE 5 j.

Next an oxide layer is grown or deposited approximately 6000-7000 A thick over the entire surface This is performed at low 120 temperatures to avoid the diffusion of the previously implanted regions The oxide is then masked and etched to form an area for word line contact 45 Next, a conductor such as aluminum is deposited over the 125 entire oxide surface The aluminum is then covered with photoresist which is patterned and etched to form the word lines This essentially completes the manufacturing process However, it is understood that the 130 1 591 429 slice will also be coated with a protective layer, scribed, broken into individual chips, and mounted into packages according to conventional procedures in the industry.

A second method for constructing the array of Hi-C memory cells is a variation of the above described first method, and it consists of the following steps To begin, the boundary of each cell and the bit lines are formed by the same steps as described in conjunction with FIGURES 5 a-5 e Then, the deep implant 76 is made as described in conjunction with FIGURE Sf However, the shallow implant step as therein described is not performed Instead, the gate oxide layer 78 is grown after the deep implant steps are performed Next, the ions 75 are implanted into oxide layer 78 The concentration of these ions ranges from 1-8 x 1013 ions/cm 2 This is approximately times larger than the concentration of the previously described shallow implant that was made into substrate 70 All of the other steps that were described in conjunction with FIGURES 5 g-5 h to form storage electrode 51 are then performed This results in cells having a cross-section as illustrated in FIGURE 5 h, except that the shallow implant ions 75 are entirely contained in oxide layer 78 In order to confine ions 75 entirely to oxide layer 78, the deposit of polysilicon layer 86 and oxide layer 79 a is performed at low temperatures (< 7200 C).

Next oxide layer 78 is etched out of region 88 This, of course, also removes the shallow implant that was contained within oxide layer 78 of region 88 Then a high temperature step is performed which causes a portion of the shallow implant that is contained in the remaining oxide layer 78 to diffuse into the surface 72 of the underlying silicon 70 This forms storage region 74 Next, a deep implant of ions 89 is made as previously described in conjunction with FIGURE Si And then, all of the steps as described in conjunction with FIGURE Sj are performed, thereby completing the construction of the Hi-C cell.

A third method of forming an array of Hi-C memory cells is illustrated in FIGURES 6 a-6 j Here again, the figures are cross-sectional views taken through one cell of the array at various stages in the process The one cell cross-sections illustrate the basic pattern which is repeated for each cell in the array.

The first steps of this process form field oxide regions 78 A and 78 B and the corresponding channel stop regions 71 A and 71 B. These regions border the cell area of each cell and the interconnecting bit lines The process used to form these regions is the same as the process previously described in conjunction with FIGURES 5 a-5 e The result of these steps is shown in FIGURE 6 a.

Next, transfer gate 51 is formed as follows First, an oxide layer 78 is grown on the surface 72 of substrate 70 as illustrated in FIGURE 6 b This oxide layer 70 covers the entire surface of the substrate and is approximately 300 1000 A thick Then a polysilicon layer 91 is formed on the oxide layer 78 and heavily doped N+ by implantation or diffusion The polysilicon 75 is approximately 2000-5000 A thick Then, an insulating oxide layer 79 a is optionally grown or deposited as described in conjunction with FIGURE 5 g Then, photoresist 92 is deposited on top of the poly 80 silicon layer 91 (or oxide layer 79 a if it is put down) as illustrated in FIGURE 6 c.

The photoresist 92 is then exposed to ultraviolet light through a mask having the form of transfer gate 41 The polysilicon layer 91 85 is then selectively etched according to the mask thereby forming a transfer gate 41.

The result is illustrated in FIGURE 6 d.

Then storage region 74 is formed by the following steps A photoresist layer 93 is 90 deposited on the surface in a pattern which exposes only the area between field oxide regions 78 A and 78 B Then a shallow implant of N-type ions 75 is made into the exposed area As in the previous process, 95 the N-type ions may be arsenic, antimony or phosphorus Their concentration is approximately 1-9 x 102 ions/cm 2 And the depth of the Gaussian distribution peak is within 500 A from the surface This implant 100 self-aligns to transfer gate 41 because polysilicon transfer gate 41 masks the ions 75 from transfer region 77 The result of these steps is illustrated in FIGURE 6 e.

Next oxide layer 79 is grown This is a 105 relatively high temperature operation and takes place at approximately 850-1100 'C.

The thickness of the oxide is approximately 300-1 OOOA The higher temperature causes shallow implant 75 to diffuse laterally 110 slightly Thus, implant 75 extends slightly under the transfer gate 41 as illustrated in Figure 6 f.

Photoresist 94 is again deposited so as to expose the area between field oxide regions 115

78 A and 78 B And then, a deep implant of ions 76 is performed Again, transfer gate 41 acts as a self-aligning mask for the deep implant Boron ions may be used as the deep implant ion The Gaussian 120 distribution peak of the ions 76 is between 2000-10,OOOA And their concentration is approximately 1-40 x 1012 ions/cm 2.

FIGURE 6 g illustrates the result of this operation 125 After this deep implant step is performed, the chances are good that the deep implant ions lie inside of the shallow implant ions in the lateral direction under electrode 41.

That is, the deep implant ions do not pene 130 1 591429 trate under the electrode 41 as far as the shallow implant ions do This is important, because it means' that a potential barrier does not exist under transfer electrode 41.

if the deep implant ions extended:beyond ti ie shallow implant ions, a potential barrier would exist which would substantially reduce the charge capacity of the IE-C cell.

Conversely, the above process causes a potential well to exist And this well does not degrade the charge capacity of the Hi-C cell, because the potential well is always filled with charge carriers.

Next storage gate 51 is formed Storage gate 51 is comprised of a polysilicon layer which is etched using photoresist and a selective etchant as previously described in conjunction with the formation of transfer gate 41 The result of these, steps is shown in FIGURE 6 h.

The remaining steps form bit line bl and transistor source 42 This is performed by first etching the oxide layer 79 which lies between storage gate 51 and field oxide region 78 A FIGURE 6 i illustrates the result of this step Next, an N+ implant or diffusion is made into the etched region The concentration level of this N-type dopant is made sufficiently high to completely cancel the previous implants that were made into that area This also heavily dopes polysilicon gate 51 and makes it conductive.

FIGURE 6 j shows the result of this operation This essentially completes the manufacturing process Additional steps required to form an insulating layer and word line, to coat the structure with a protective covering, and to mount the circuit into packages are made in accordance with conventional industry practices.

A fourth method for constructing the array of Hi-C cells is a modification of the above described third method In this fourth method, all ihe steps as described in conjunction with FIGURES 6 a-6 d are performed Then, a shallow ion implant is made into oxide layer 78 The concentration of these ions range within ( 1-8) x 101 'ions/cm 2 Then, the slice is exposed to a high temperature atmosphere which causes a portion of the above implanted ions to diffuse from oxide layer 78 into the underlying substrate The resulting concentration of ions near the surface of the substrate ' ranges from ( 1-6) x 10 12 ions/cm 2 The high temperature atmosphere also causes the ions to diffuse laterally as previously described in conjunction with FIGURE 6 f.

Then, to complete the construction of the Hi-C cell array, all of the steps as described in conjunction with FIGURES 6 g-6 j are performed.

In the previous four methods,, deep implant 76 and shallow implant 75 were initially made throughout the entire memory cell area Subsequently these implants were shaped to form storage area 74 By comparison, in the next two methods, methods 5 and 6, the deep implant is initially made only in storage region 74 70 Method 5 will now be described in conjunction with FIGURES 7 a-7 e The initial steps of this method form the boundaries of the cell That is, field oxide regions 78 A and 78 B, in addition to'channel stop regions 75 71 A and 71 B, are formed To form these regions, the steps as previously described in conjunction with FIGURES Sa-5 e are repeated The result is shown in FIGURE 7 a 80 Next, the shallow implant ions 75 are implanted throughout the cell area The depth and concentration dosage of this implant is the same as previously described.

Then, the oxide layer 78 is formed on top 85 of the entire slice FIGURE 7 a also shows the result of these steps.

Then a photoresist layer 101 is deposited on top of oxide layer 78 Photoresist layer 101 is then patterned so as to expose storage 90 area 74 This patterning is performed by steps as previously described The photoresist 101 is shaped so as to extend slightly over storage region 74 in the area adjacent to 'transfer region 77 In other words, edge 95 102 of photoresist 101 lies slightly within storage region 74 Next, the deep implant of ions 76, into storage region 74, is made.

The result of these steps is shown in FIGURE 7 b 103 The next steps form storage gate 51.

First a layer of polysilicon is deposited on top of the entire slice Then it is doped N+ to make it conductive Next, a layer of oxide 79 a is optionally formed on top of the 105 photoresist layer Then a layer of photoresist is deposited on top of this oxide (or polysilicon if the optional step is eliminated).

The photoresist is then masked and selectively patterned leaving layer 103 above 110 storage region 74 The polysilicon (and oxide) is then etched, leaving storage gate 51 (and insulating layer 79 a) as illustrated in' FIGURE 7 c Edge 104 of the polysilicon is patterned such that all of the deep 115 implant ion 76 lies completely under storage gate 51 Thi's 'is illustrated in FIGURE 7 c.

The next steps form transfer region 77.

To accomplish this, an etch is made in 120 region 105 before removing resist layer 103.

Region 105 fills the space between edge 104 and field oxide region 78 A The above described position of edge 104 ensures that deep implant 76 will lie within shallow 125 implant 75 after this etch is made Thus no potential barriers,will exist in transfer region 77 The etching-in region 105 reinoves oxide layer 78, and)in addition, removes the shallow implant ions 75 in that region The 130 1 591 429 result of these steps is illustrated in FIGURE 7 d.

The remaining steps form bit line region 73 and transfer gate 41 The steps used to form these structures are identical to those described in conjunction with FIGURE 5 j.

The result of these steps is illustrated in FIGURE 7 e.

The remaining steps form bit line region 73 and transfer gate 41 The steps used to form these structures are identical to those described in conjunction with FIGURE Sj.

The result of these steps is illustrated in FIGURE 7 e.

The next method, method 6, is a variation of method 5 That is, in method 6, the deep implant ion 76 is only made in storage region 74, and the sallow implant 75 is made throughout the cell area However, the manner in which shallow implant 75 is made is different FIGURES 8 a-8 e illustrate method 6.

Referring to FIGURE 8 a, the initial steps of this process are illustrated Field oxide regions 78 A and 78 B and channel stop regions 71 A and 71 B are formed as previously described Then, an insulating layer 78 is formed on the surface of the substrate.

Next, the shallow implant ions 75 are deposited entirely within oxide layer 78 The concentration of this ion implant ranges from 1-8 x 101 'ions/cm 2 This is approximately a factor ten times larger than the concentration of the ions 75 that was made in conjunction with FIGURE 7 a The result of these steps is illustrated in FIGURE 8 a.

The next steps form deep ion implant 76 in storage region 74, and also form storage gate 51 These steps are similar to those previously described in conjunction with FIGURES 7 b and 7 c The only difference is that here the polysilicon deposition and overlying oxide formation of layer 79 a are performed at temperatures below 720 WC to ensure that ion implant 75 remains entirely in oxide layer 78 The result of these steps is illustrated in FIGURES 8 b and 8 c.

Next, transfer region 77 is formed To accomplish this, an etch is made in region 105 before resist layer 103 is removed Region fills the space between etch 104 and field oxide 78 A This etch removes oxide layer 78 in region 105 However, the etch does not remove any significant portion of the silicon in area 105 A silicon etch, of course, is not necessary because all of the shallow implant ions 75 lie within the oxide layer 78 FIGURE 8 d illustrates the result of these steps.

Then the slice is exposed to a high temperature atmosphere As a result, a portion of the shallow implant ions 75 lying within oxide layer 78 diffuse into the under 70 lying substrate Thus, storage region 74 having a shallow implant 75 and a deep implant 76 is formed FIGURE 8 e illustrates the result of this step Also illustrated in FIGURE 8 e are bit line 73 and transfer 75 gate 41 The formation of these elements and the associated word line are made by steps as previously described.

Referring now to FIGURES 9 and 10, two more methods (methods 7 and 8) for 80 constructing the Hi-C cell are illustrated.

These methods differ from the previously described methods in that shallow implant and deep implant 76 are made only in storage region 74 That is, neither of these 85 implants is made in the entire cell area as defined by field oxide regions 78 A and 78 B.

The first of these processes is illustrated in FIGURES 9 a-9 e To begin the cell boundaries as defined by field oxide regions 90

78 A and 78 B and corresponding channel stop regions 71 A and 71 B are formed by steps as previously described Then a layer of photoresist is deposited on top of the entire slice The photoresist is then selectively 95 patterned leaving region 111 and exposing the top of storage region 74 A shallow ion implant 75 is then made into the exposed area The dosage and implant depth is as previously described FIGURE 9 a illus 100 trates the result of these steps.

Next, a photoresist layer 113 is formed on surface 72 of substrate 70 so as to expose a window through which the deep implant of ions 76 is made The shape of resist layer 105 113 is the same as that for resist layer 111, except that the edge 114 extends slightly over storage region 74 In comparison, edge 112 of the previous photoresist mask defined the edge of storage region 74 Resist 110 layer 113 may be formed by removing resist layer 111 and subsequently forming an entirely new resist layer Alternatively resist layer 113 may be formed from resist layer 111 by heating the latter thereby causing 115 it to soften and move slightly in the lateral direction In either case the deep implant 76 is then made The above described relative positions of edges 112 and 114 ensure that no potential barriers will exist 120 in transfer region 77 This is because deep implant 76 lies within shallow implant 75 at the transfer region storage region interface The depth and concentration level of implant 76 is as previously described As a 125 result of these steps storage region 74 is formed as illustrated in FIGURE 9 b.

Next oxide layer 78 is formed over surface 72 of the entire slice This is illustrated in FIGURE 9 c Then storage gate 51 is formed 130 1 591429 over storage region 74 as illustrated in FIGURE 9 d The steps involved in forming storage gate 51 are the same as those previously described in conjunction with FIGURES 5 g and Sh FIGURE 9 d illustrates the result of these steps The remaining steps form bit line bl, transistor source 42, transfer gate 41 and the corresponding word line All of these' elements are formed by steps as previously described in conjunction with the FIGURE 5 j -The result of these steps is illustrated in FIGURE 9 e.

The next method, method 8 is a modification of the previously described method 7.

Portions of this method are illustrated in FIGURES l Oa-10 c.

As before, the first steps form field oxide regions 78 A and 78 B and the corresponding channel stop regions 71 A and 71 B However, the next step, is to form oxide layer 78 over surface 72 Then, a layer of photoresist 111 is formed on top of oxide layer 78 The pattern of this photoresist layer is the same as previously described in conjunction with FIGURE 9 a Then, a shallow implant of ions 75 is made into oxide 78 which is exposed by photoresist layer 111.

The concentration dosage of this implant is approximately 10 times larger than the concentration dosage of the shallow implant when made directly into substrate 70.

FIGURE l Oa illustrates the result of these steps.

Next, the photoresist layer 113 is formed as previously described in conjunction with FIGURE 9 b And then the deep implant of ions 76 is performed as previously described FIGURE l Ob illustrates the result Qf these steps.

The slice is then exposed to a high temperature atmosphere This causes a portion of the shallow implant lying in oxide layer 78 to diffuse out into the surface of the underlying substrate 70 As a result, storage region 74 is formed And near transfer region 77, the deep, implant ions lie entirely within storage region 74 This ensures that no potential barriers will exist in transfer region 77 The remaining steps which complete the cell structure are the same as those previously described in conjunction with FIGURES 9 d-9 e.

Referring now to FIGURES lla-lle, a process for constructing a second embodiment of the Hi-C cell is illustrated This embodiment is similar in many respects to' the previously described cell For example, as illustrated in FIGURE llb, this embodiment includes a storage region 121 which has a deep P-type ion layer 122 and a shallow N-type ion layer 123 Ion layers 122 and 123 have distribution peaks and dosages identical to those of the previously described deep ion layer 76 and shallow ion layer 75 respectively This Hi-C cell also includes an overlying storage gate 124, and a transfer gate 125, which are separately operable from each other However, the two Hi-C cell embodinients differ from each other, in that the second embodiment 70 includes an additional N+ type region 126 similar to the N+ region 73 Region 126 is adjacent to storage region 121 and is spaced apart from source-bit line region 73.

Also, transfer gate 125 does not overlie 75 storage gate 124, but instead only overlies the surface region between regions 126 and 72.

The electrical operation of the second embodiment is very similar to the electrical 80 operation of the first embodiment Storage region 121 and region 126 act like storage region 74; and the surface area under gate acts like transfer region 77 With these modifications, the surface potentials of the 85 storage region -and transfer region are the same for the two embodiments In addition, both embodiments have the same high charge capacity per unit area, and both have reduced leakage current This is be 90 cause storage' region 121 has the same con-struction as the previously described storage region 74.

FIGURE lla illustrates the initial steps for constructing this second embodiment of 95 the invention First, the cell area of each of the cells of array 11 are defined by forming channel stop regions 71 A and 71 B, and the corresponding field oxide regions 78 A and

78 B Next, a photoresist layer 127 is 100 selectively patterned on surface 72 of substrate 70 so as to expose storage region 121.

Storage region 121 occupies the area lying between edge 128 of photoresist 127, and field oxide region 78 B of each cell (just as 105 did the previously described storage region 74).

Next, a P-type ion 122, and an N-type ion 123, are implanted into each storage region 121 Ion implant 122 is at the same 110 depth, and has the same dosage, as the previously described deep ion implant 76.

That is, the Gaussian distribution peak of ions 122 occurs within 1500 A-10,OOOA from surface 72; and the dosage of ions 122 ranges 115 between'I-40 x 1 Q 2 ions/cm 2 Similarly, shallow ion layer 123 has a distribution peak and dosage identical to that of the previously described shallow ion layer 75 The result of these' implant steps is illustrated in 120 FIGURE llb.

The next steps form storage gate regions 51 and transfer gate regions 125 First, photoresist, layer 127 is removed Then, insulating layer 78 is formed on top of 125 surface 72 Next, a Dolysilicon layer is disposed on top of insulating layer 78 This polysilicon layer is then implanted to make it conductive, and then selectively masked and etched (using previously described steps) 130 11 ' 1 591429 to form storage gate 51 and transfer gate FIGURE lic illustrates the result of these steps.

Next, the N + type region 126 and the N+ region 73 are formed This is accomplished by etching that portion of insulating layer 78 which lies between storage gate 51 and transfer gate 125; and also by etching that portion of insulating layer 78 lying between field oxide 78 A and transfer gate 125.

Then, an N-type implant or diffusion which is very high in dosage (approximately 's-10 '6 ionsl/cm 2) is made, and this high dosage completely eliminates any potential barriers near surface 72 at the interface between regions 121 and 126 This is because the ions implanted or diffused into region 126 laterally straggle or diffuse slightly into storage region 121 And therefore, ion layer 122 lies laterally within ion layer 123 at the interface between regions 121 and 126 The result of these steps is illustrated in FIGURE l d.

The remaining steps complete the construction of the cell These steps include forming an insulating layer over the entire surface of the slice, etching this layer to form areas for world line contact 45, and patterning word lines on top of the insulating layer The result of these steps is illustrated in FIGURE 1 le Additional steps to coat the slice with a protective layer, to break the slice into individual chips, and to mount the chips into packages are subsequently performed in accordance with standard industry practice.

Various embodiments of the invention have now been described in detail And from this description, it will be apparent that several modifications of these embodiments are possible For example, the ions identified as N-type and P-type can all be reversed to P-type and N-type respectively.

Additionally, semiconductor substrates other than silicon can be used.

Claims

WHAT WE CLAIM IS: -

1 A method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone, comprising the steps of:

forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which define a cell area for each cell of said array, the cells being interconnected by zones comprising bit lines and formed subsequently adjacent one channel stop region; introducing ions of a first conductivity type throughout said cell areas, thereby forming a shallow ion layer throughout each cell area; introducing ions of a second conductivity type throughout said cell areas at a level lying below said shallow ion layers, thereby forming a deep ion layer throughout each cell area; disposing a first insulating layer on said first surface overlying said cell areas; forming a patterned layer of conductive 70 material on said insulating layer to define a storage gate region partially overlying each of said cell areas and spaced apart from said one channel stop region; removing from each of said cell areas, 75 the portions of said shallow ion layer lying between said storage gate regions and one channel stop region; introducing ions of said first conductivity type, throughout the portion of each cell 80 area lying between said storage gate regions and said one channel stop regions, at approximately the same depth and concentration as said deep ion layer lying therein; disposing a second insulating layer at least 85 on said storage gate regions; forming a patterned layer of conductive material on said second insulating layer to define a transfer gate region partially overlying and spaced from said storage gate 90 region in each of said cell areas; and introducing ions of said first conductivity type into each of said cell area between said transfer gate regions and said one channel stop regions so as to define said bit line 95 zones.

2 A method according to claim 1, wherein said ions of said first conductivity type which are introduced throughout the portion of each cell area lying between said 100 storage gate regions and said one channel stop regions at approximately the same depth and concentration as said deep ion layer lying therein are introduced by an ion implant operation after said storage gate 105 regions are formed and at an energy sufficient to produce lateral straggle under said storage gate regions.

3 A method according to either of claims 1 or 2, wherein said ions of said second con 110 ductivity type which are introduced throughout said cell areas in forming a deep ion layer throughout each cell area are introduced by an ion implantation at an energy level sufficient to produce straggle from said 115 cell areas into said channel stop regions.

4 A method according to any of claims 1 to 3, wherein said first insulating layer is disposed on said first surface overlying said cell areas, and subsequently said shallow 120 ion layer of each cell area is formed by implanting said ions of said first conductivity type into said insulating layer, and exposing said substrate to a high temperature atmosphere thereby diffusing said ions 125 of said first conductivity type from said first insulating layer into said underlying substrate.

A method according to any of claims 1 to 4, Wherein said field insulator regions 1 i 30 f 2 1 591429 are at least partially exposed:'while said shallow ion layer and said deep ion layer are being formed.

6 A method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone, comprising the steps of:

forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which define a cell area for each cell of said array, the cells being interconnected by zones comprising bit lines and formed subsequently adjacent one channel stop region; disposing a first insulating layer on said first surface overlying said cell areas; forming a patterned layer of conductive material on said first insulating layer to define transfer gate regions overlying a portion of each of said cell areas and spaced apart from said one channel stop region; introducing ions of a first conductivity type, throughout the portion of said cell areas not covered by said transfer gate regions, thereby forming a shallow ion layer in each of said cell areas; disposing 'a second insulating layer at least on said transfer gate regions; exposing said substrate to a high temperature atmosphere to diffuse said shallow ion layer laterally and partially under said transfer gate regions and subsequently; introducing ions of a second conductivity type throughout said portions of said cell areas not covered by said transfer gate regions, at a level lying below said shallow ion layers, thereby forming in each cell area a deep ion lying laterally within said shallow ion layer of that cell area; forming a patterned layer of conductive material on said second insulating layer to define a storage gate region partially overlying and spaced from said transfer 'gate region in each of said cell areas; and introducing ions of said' first conductivity type into each of said cell areas between said transfer gate regions and said one channel ston regions so as to define said bit :50 line zones.

7 A method according to claim 6, wherein said ions of said second conductivity type which are introduced to form said deep ion layer in each cell area are introduced by an ion implantation at an energy level sufficient to produce straggle-from said cell areas into said channel stop regions.

8 A method according to either of claims 6 or' 7, -wherein said shallow: ion layer of each cell area-is' formed by implanting ions of said first conductivity type directly into said' substrate after said transfer 'gate regions are formed.

9 A method according to' either of claims :" 65 6 or 7, wherein said shallow ion layer of each cell area is formed by implanting ions of said: first conductivity type through said first insulating layer after said transfer gate regions are formed.

-

10 A method according to claim 6 or 7, 70 wherein said " transfer gate' regions are formed, and subsequently said shallow ion layer of each cell area is formed by implanting said ions of said first conductivity type into said' first insulating layer, and 75 exposing said, substrate to a high temperature atmosphere thereby diffusing said ions of said first conductivity type from said first insulating layer into said underlying substrate 80

11 A method according to any of claims 6 to 10, wherein said transfer gate regions and portions of said 'field insulator regions are exposed while said shallow ion layer and said deep ion layer are being formed 85

12 A method according to any of claims 6 to 11, wherein said patterned layer of conductive material defining said transfer gate regions is formed by disposing an unpatterned layer of conductive material on 90 said first:insulting layer and selectively removing portions thereof.

13 A method according to any of claims 6 to 12, wherein said ions of said first conductivity type are introduced into each 95 of said cell areas between said transfer gate regions and said one channel stop regions in defining said bit line zones at a dosage which at least cancels said deep ion layers lying therein 100

14 A method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone,' comprising the steps of: 105 forming-in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions' which define a cell'area for each cell of said array, the cells "being interconnected by zones 110 comprising bit lines 'and formed subsequently adjacent one channel stop 'region; introducing ions of a first conductivity type, 'throughout said, cell areas, thereby forming a shallow ion layer throughout each 115 of said cell areas; disposing a first insulating layer on said first' surface overlying said cell areas; masking each of said cell areas so as to expose a storage region lying within each of 120 said cell areas and spaced apart from said one channel stop region; introducing ions, of a second conductivity type into each of said storage regions at a level lying-below said shallow ion layers to 125 form a deep ion layer in each of said cell areas;.

forming a patterned layer of conductive material on said first" insulating layer to define a storage gate region overlying each 130 1 591429 of said storage regions; removing the portion of said shallow ion layers lying between said storage gate regions and said one channel stop region; disposing a second insulating layer at least on said storage gate regions; forming a patterned layer of conductive material on said second insulating layer to define a transfer gate region partially overlying and spaced from said storage gate region in each of said cell areas; and introducing ions of said first conductivity type into each of said cell areas between said transfer gate regions and said one channel stop regions so as to define said bit line zones.

A method according to claim 14, wherein said shallow ion layer of each cell area is formed by implanting said ions of said first conductivity type throughout said first insulating layer, removing the portions of said first insulating layer lying between said storage gate regions and said channel stop regions, and exposing said substrate to a high temperature atmosphere to diffuse said ions of said first conductivity type from the remaining portions of said first insulating layer into said underlying substrate.

16 A method according to either of claim 14 or 15, wherein said ions of said second conductivity type forming said deep ion layer in each of said cell areas are introduced such that said deep ion layer lies laterally within said storage region.

17 A method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone, comprising the steps of:

forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which define a cell area for each cell of said array, the cells being interconnected by zones comprising bit lines and formed subsequently adjacent one channel stop region; masking each of said cell areas so as to expose a storage region lying therein and spaced apart from said one channel stop region; introducing ions of a first conductivity type throughout each of said storage regions thereby forming a shallow ion layer in each cell area; masking each of said cell areas so as to expose said storage region except in the area lying closest to said spaced apart one channel stop region; introducing ions of a second conductivity type throughout said partially exposed storage regions and at a level lying below said shallow ion layer lying therein to form a deep ion layer in each of said cell areas; disposing a first insulating layer on said first surface overlying said cell areas; forming a patterned layer of conductive material on said first insulating layer to define a storage gate region overlying said storage region of each of said cell areas; 70 disposing a second insulating layer at least on said storage gate regions; forming a patterned layer of conductive material on said second insulating layer to define a transfer gate region partially over 75 lying and spaced from said storage gate region in each of said cell areas; and introducing ions of said first conductivity type into each of said cell areas between said transfer gate regions and said one 80 channel stop regions so as to define said bit line zones.

18 A method according to claim 17, wherein the masking of each of said cell areas so as to expose said storage region 85 except in the area lying closest to said spaced apart one channel stop region is performed by heat softening the mask previously employed in masking each of the cell areas so as to expose a storage region 90 lying therein and spaced apart from said one channel stop region prior to the formation of the shallow ion layer in each cell area.

19 A method according to any of claims 95 1 to 5 and 14 to 18, wherein said patterned layer of conductive material defining said storage data regions is formed by disposing an unpatterned layer of conductive material on said first insulating layer and selectively 100 removing portions thereof.

A method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone, comprising 105 the steps of:

forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which define a cell of said array, the cells being inter 110 connected by zones comprising bit lines and formed subsequently adjacent one channel stop region; masking each of said cell areas so as to expose a storage region lying therein and 115 spaced apart from said one channel stop region; introducing ions of a first conductivity type throughout each of said storage regions, thereby forming a shallow ion layer 120 lying therein in each cell area; Introducing ions of a second conductivity type throughout said storage regions at a level below said shallow ion layer lying therein, thereby forming a deep ion layer in 125 each cell area; disposing a first insulating layer on said first surface overlying said cell areas; forming a patterned layer of conductive material on said first insulating layer to 130

forming in a first surface of a semiconductor substrate, channel stop regions and overlying field insulator regions which define a cell of said array, the cells being inter 110 connected by zones comprising bit lines and formed subsequently adjacent one channel stop region; masking each of said cell areas so as to expose a storage region lying therein and 115 spaced apart from said one channel stop region; introducing ions of a first conductivity type throughout each of said storage regions, thereby forming a shallow ion layer 120 lying therein in each cell area; Introducing ions of a second conductivity type throughout said storage regions at a level below said shallow ion layer lying therein, thereby forming a deep ion layer in 125 each cell area; disposing a first insulating layer on said first surface overlying said cell areas; forming a patterned layer of conductive material on said first insulating layer to 130 1 591 429 are at least partially exposed while said shallow ion'layer and said deep-ion layer are being formed 6 A method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS; capacitor sharing a ' common -semiconductor zone, comprising the steps of:

-forming in a first surface of a semiconductor substrate, channel stop regions-and overlying field'insulator:regions which'define a cell area for-each cell of said array, the cells being interconnected -by zones -comprising 'bit lines and formed subsequently adjacent one-channel stop region; disposing a first insulating layer on said first surface overlying said cell areas; forming a patterned layer,'of conductive material on said first insulating layer to define transfer 1-gate regions overlying a portion of-each of said cell areas and spaced apart from said one channel stop region; introducing ions: of a first 'conductivity type,' throughout the portion of said cell areas not -covered by said transfer gate regions, thereby forming a shallow ion layer in:each of said'cell areas; disposing a second insulating layer at least on said transfer gate regions; exposing said substrate to a high temperature 'atmosphere to diffuse said shallow ion layer laterally and partially under said transfer gate regions and subsequently; "introducing ions, of-a second conductivity type' throughout said portions of said cell areas not covered' by said transfer gate regions, at a level lying below said shallow ion layers,,thereby forming in each cell area a deep ion lying laterally within said shallow ion layer of that cell area;,-.

forming a patterned layer of conductive material on said second insulating layer to define a storage gate region partially overlying and: spaced -from> said transfer gate region in eachi:of said cell areas; and introducing ions of said first conductivity type into each of said cell areas between said transfer gate regions and said one channel stopregions so as to define said bit line zones:

7 A method' according to claim 6, wherein said ions of said second conductivity type' which are introduced to'form said deep ion layer in -each cell' area are introduced by an ion implantation' at an energy level sufficient to produce straggle from said cell areas into said channel stop regions.

8 A method according to either of claims 6 or 7, -wherein said shallow ion layer of each cell area is formed by implanting ions of said first conductivity type directly into said substrate after said transfer gate regions are formed : 9 A method according to either of claims 6 or 7, wherein said shallow ion layer of each cell area is formed by implanting ions of said first conductivity type through said first 'insulating layer after said transfer gate regions are formed ' A method according to claim 6 or 7, 70 wherein said -transfer gate regions are formed, and subsequently said shallow ion layer of -each cell area is formed:by implanting said ions of said first conductivity type into said first insulating layer, and 75 exposing said substrate to a high temperature atmosphere thereby diffusing said ions of -said first conductivity type from' said first insulating layer into said underlying substrate ' 80 11 A method according to any of claims 6 to 10, wherein said transfer gate regions and portions of said field insulator regions are exposed while' said shallow ion layer and said deep ion layer are being formed 85 12 A method according to any of claims 6 to 11, wherein said patterned layer of conductive material -defining said transfer gate regions is formed by disposing an unpatterned layer of conductive material on 90 said first insulting layer and selectively removing portions thereof ' ^ 13 A method according to any of claims 6 to 12, wherein said ions of said first conductivity type are introduced into each 95 of said cell areas between said transfer gate regions and said one channel stop regions in defining said bit line zones at a dosage which at least cancels said deep ion layers lying therein, 100 14 A method of constructing an array of high capacity memory cells, each comprising a MOSFET and a MOS capacitor sharing a common semiconductor zone, comprising the steps of: 105 forming in a first surface of a semiconductor substrate, channel ston regions and overlying field insulator regions which define a cell area for each cell of said array, the cells being interconnected by zones 110 comprising bit lines and formed subsequently adjacent one channel stop region; introducing ions of a first conductivity type, throughout said cell areas, thereby forming a shallow ion layer throughout each 115 of said cell areas; disposing a first insulating layer on said first surface overlying said cell areas; masking each 'of said cell areas so as to expose a storage region lying within each of 120 said cell areas and spaced apart from said one channel stop region;introducing ions of a second conductivity type into each of said storage regions at a level lying below said shallow ion layers to 125 form a deep ion layer in each of said cell areas; forming'a patterned layer of conductive material on 'said first insulating layer to define a storage gate region overlying each 130 1 591429 of said storage regions; removing the portion of said shallow ion layers lying between said storage gate regions and said one channel stop region; disposing a second insulating layer at least on said storage gate regions; forming a patterned layer of conductive material on said second insulating layer to define a transfer gate region partially overlying and spaced from said storage gate region in each of said cell areas; and introducing ions of said first conductivity type into each of said cell areas between said transfer gate regions and said one channel stop regions so as to define said bit line zones.