JPS6033312B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6033312B2
JPS6033312B2 JP1543479A JP1543479A JPS6033312B2 JP S6033312 B2 JPS6033312 B2 JP S6033312B2 JP 1543479 A JP1543479 A JP 1543479A JP 1543479 A JP1543479 A JP 1543479A JP S6033312 B2 JPS6033312 B2 JP S6033312B2
Authority
JP
Japan
Prior art keywords
plating layer
brazing material
nickel
phosphorus
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1543479A
Other languages
Japanese (ja)
Other versions
JPS55108757A (en
Inventor
博之 馬場
修 薄田
親男 竹林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP1543479A priority Critical patent/JPS6033312B2/en
Publication of JPS55108757A publication Critical patent/JPS55108757A/en
Publication of JPS6033312B2 publication Critical patent/JPS6033312B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PURPOSE:To improve, in semiconductor device having elements arranged on a lead frame, the bonding strength between the brazing material and semiconductor element, by disposing a nickel-plating layer and a phosphorus-containing plating layer on the portions of the lead frame where the elements are to be mounted. CONSTITUTION:A bright electro-plating layr 3b of nickel and a nickel plating layer 13b containing phosphorus are formed on the surface of a substrate 3a. A brazing material 16 is press-contacted against the plating layer 13b and is then molten. A semiconductor element 4 is mounted on the molten brazing material 16. Since the standard oxide-forming energy of phosphorus contained by the nickel-phsphorus alloy plating layer is lower than those of the brazing material and the lead frame, the nickel plating on the brazing material and lead frame are activated to provide a stronger bonding between the brazing material and the semiconductor element.

Description

【発明の詳細な説明】 この発明は半導体装置にか)り、特に半導体素子が配設
されるリードフレームにおける秦子配設台床部の改良構
造を備えた高出力用半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a high-output semiconductor device having an improved structure for a bottom portion of a lead frame on which a semiconductor element is disposed.

高出力用半導体装置の一例にリードフレームを用い樹脂
封止された第1図に斜視図示するものがある。
An example of a high-output semiconductor device is the one shown in a perspective view in FIG. 1 that uses a lead frame and is sealed with resin.

図において、la,lb,lcはいずれもリード、2は
樹脂封止体、3は放熱板を兼ねる素子酉己設台床部であ
る。次に上記蓑子配設台床部とこ)に配設される半導体
素子との関係を上面図によって第2図に示す。すなわち
、図において4は半導体素子でその1主面の電極にて素
子配設台床部3に鑑接され、さらにこの素子配設台床部
は1つのりードlbに接続される。なお、5a,5cは
ボンディングワイヤにて半導体素子の残る電極を夫々リ
ードla,lcに夫々導出するものである。上記半導体
素子4と素子配設台床部3との接続は一般に第3図に該
部の断面図によって示す如く、素子配設台床部はその基
村3aが銅または銅合金でなり、その表面に光沢ニッケ
ルめつき層3bが設けられ、この層にはんだの如きろう
材によって半導体素子が1電極にて接合される。図にお
ける6はろう層を示す。こ)に上記接合は機械による自
動組立により施されるが、光沢ニッケルめつきされたり
ードフレームの酸化や、ろう村の表面の酸化の問題があ
り、それを回避するには装置の複雑化や、不活性ガスあ
るいは還元性ガスの使用量が著るしく増加するなどの欠
点があった。しかも、前記方法ではろう村やりードフレ
ームのニッケルの酸化物を十分還元できないため、第3
図に示される如く半導体素子が傾斜したり、素子直下の
ろう材とIJードフレームのニッケルめつき層とのなじ
みが悪く、ボィド7,7′・・・が発生したりしてろう
材が均一に流れなく製品の信頼性も完全でなかった。こ
の発明は上記従来の欠点に対しこれを改良するために、
リードフレームの少くとも素子配設台床部に半導体素子
をろう接するためのニッケルめつき層およびろう材表面
の酸化を生ぜしめない構造を備えた半導体装置を提供す
る。
In the figure, la, lb, and lc are all leads, 2 is a resin sealing body, and 3 is an element mounting base portion that also serves as a heat sink. Next, FIG. 2 shows a top view of the relationship between the above-mentioned pedestal mounting base and the semiconductor element disposed thereon. That is, in the figure, reference numeral 4 denotes a semiconductor element, and an electrode on one main surface of the semiconductor element is in contact with the element mounting platform 3, and this element mounting platform is further connected to one lead lb. Note that 5a and 5c lead out the remaining electrodes of the semiconductor element to leads la and lc, respectively, using bonding wires. The connection between the semiconductor element 4 and the element mounting platform 3 is generally shown in FIG. 3, which is a cross-sectional view of the part. A bright nickel plating layer 3b is provided on the surface, and a semiconductor element is bonded to this layer at one electrode using a brazing material such as solder. 6 in the figure indicates a wax layer. (2) The above-mentioned joining is performed by automatic assembly using a machine, but there are problems with oxidation of the bright nickel-plated metal frame and oxidation of the surface of the wax. There were drawbacks such as a significant increase in the amount of inert gas or reducing gas used. Moreover, since the nickel oxide in the deaf frame cannot be sufficiently reduced by the above method, the third method is
As shown in the figure, the semiconductor element may be tilted, the brazing material directly under the element may not fit well with the nickel plating layer of the IJ card frame, and voids 7, 7', etc. may occur, causing the brazing material to become uniform. There was no flow and product reliability was not perfect. In order to improve the above-mentioned conventional drawbacks, this invention has the following points:
To provide a semiconductor device having a structure that does not cause oxidation of a nickel plating layer and a surface of a brazing material for soldering a semiconductor element to at least the element mounting base part of a lead frame.

この発明にかかる半導体装置は、銅または銅合金でなる
リードフレームにおける少くとも素子配設台床部に光沢
ニッケルめつき層とこれに積層したリン含有ニッケルめ
つき層を設け、このリン含有ニッケルめつき層に半導体
素子を鍋薮したことも特徴とする。
A semiconductor device according to the present invention is provided with a bright nickel plating layer and a phosphorus-containing nickel plating layer laminated thereon on at least the element mounting base of a lead frame made of copper or copper alloy, and the phosphorus-containing nickel plating layer is laminated thereon. Another feature is that the semiconductor element is placed in the base layer.

次にこの発明を一実施例の半導体装置につき従来との相
違点につき図面を参照して詳細に説明する。
Next, the present invention will be explained in detail with reference to the drawings regarding the differences from the conventional semiconductor device according to one embodiment.

第4図にリードフレームの一部の素子配設台床の一部表
面部を断面図示する。図において13は放熱板を兼ねる
素子配設台床部で、基板3aは銅または銅合金でなり、
その表面に光沢ニッケルめつき層3bが層厚3〆被着さ
れ、さらに積層してリンを含有するニッケルめつき層1
3bの電解ニッケルリン合金めつき層が層厚0.2山被
着されてなる。そして上記合金めつき層に鉛・錫等の如
きろう材16を圧接したのちこのろう材を溶融して半導
体素子4をマゥントする。上記ニッケルリン合金めつき
層に含有されるリンの酸化物生成の標準自由ェネルギ0
金属便覧」:日本金属学会編、(丸善))は(単位はい
ずれもKcal/molにて)2500にて約一130
30000にて約一118と通常半導体装置に使用さ
れるろう材のたとえば錫、鉛などや、リードフレームの
めつきのニッケルよりも小さい、すなわち、(単位はい
ずれもKcal/molにて)25qCにて 錫:約
一110, 鉛:約一100,ニッケル:約一106
30000にて 錫:約一106, 鉛:約一80
,ニッケル:約一95と非常に酸化されやすい。
FIG. 4 shows a cross-sectional view of a part of the surface of a part of the element mounting base of the lead frame. In the figure, reference numeral 13 denotes an element mounting base that also serves as a heat sink, and the substrate 3a is made of copper or copper alloy.
A bright nickel plating layer 3b with a thickness of 3 layers is deposited on the surface, and a nickel plating layer 1 containing phosphorus is further laminated.
An electrolytic nickel phosphorus alloy plating layer 3b is deposited to a thickness of 0.2 mounds. After a brazing material 16 such as lead or tin is pressure-welded to the alloy plating layer, the brazing material 16 is melted and the semiconductor element 4 is mounted. The standard free energy for the formation of oxides of phosphorus contained in the above nickel-phosphorus alloy plating layer is 0.
"Metal Handbook": Edited by the Japan Institute of Metals, (Maruzen)) is 2500 (all units are Kcal/mol), which is approximately 1130.
30,000 and about 118, which is smaller than the brazing filler metals normally used in semiconductor devices, such as tin and lead, and the nickel used in lead frame plating, that is, at 25qC (all units are in Kcal/mol). Tin: about 1110, Lead: about 1100, Nickel: about 1106
At 30,000 Tin: approx. 1106, Lead: approx. 180
, Nickel: Approximately 195%, very easily oxidized.

逆にいえば前託ろう材やめつきの酸化物に対する還元作
用を有しており、しかもこのリンの酸化物は半導体素子
マウント温度の35000程度の温度で昇華する(「化
学便覧基機編1」:日本化学会糠、(丸善))ので、半
導体素子のリードフレームへのマウント温度をそれ以上
にすることによってリンのろう材への他の影響(機械的
性質等)はほとんどなくなる。したがって、ろう材およ
びリードフレームのニッケルめつきは非常に美しい金属
光沢を有し活性化するため、リードフレームとろう材、
あるいはろう材と半導体素子とのなじみ、すなわち、接
着力が格段に向上することになる。また、このリンを含
むニッケルめつき層の層厚は光沢ニッケルめつきのボン
ディング性を失わない程度に必要であり、実験では数百
A〜数千Aの範囲であれば上記のリンの効果を満足しボ
ンディング性も良好であるという結果が得られている。
つぎに上記リンを含むニッケルめつき層の形成にはめつ
き液中に一例ととして10%含ませて好適したが、これ
に限られず、含有せしめることが有効である。なお、リ
ンを含むニッケルめつき層のみではろう材の酸化物を還
元する能力は充分に存するも、めつき層表面は無光沢で
あり、光沢ニッケルめつき層、あるいは「光沢ニッケル
めつき層」と「リンを含むニッケルめつき層」との積層
層に比し加熱時のめつき層露出面の変色が甚だしく、め
つき層厚を変えてもボンディング性は光沢めつき層に比
し非常に劣るため、組立作業歩蟹も悪く、製品の信頼性
も不完全になることが判明した。そこで、本願の「光沢
ニッケルめつき層」と「リンを含むニッケルめつき層」
との積層層によれば次に列挙する如き顕著な利点が認め
られる。
In other words, it has a reducing effect on the oxides of the soldering filler metal and the soldering material, and moreover, this oxide of phosphorus sublimates at a temperature of about 35,000 ℃, which is the semiconductor element mounting temperature (``Chemistry Handbook Basic Machine Edition 1'': (Maruzen)), the other effects of phosphorus on the brazing material (mechanical properties, etc.) are almost eliminated by raising the temperature at which the semiconductor element is mounted on the lead frame to a higher temperature. Therefore, the nickel plating on the brazing metal and lead frame has a very beautiful metallic luster and is activated.
Alternatively, the compatibility between the brazing material and the semiconductor element, that is, the adhesion strength is significantly improved. In addition, the thickness of the nickel plating layer containing phosphorus is necessary to the extent that the bonding properties of bright nickel plating are not lost, and in experiments, the above effect of phosphorus is satisfied within the range of several hundred amps to several thousand amps. The results showed that the bonding properties were also good.
Next, for forming the above-mentioned nickel plating layer containing phosphorus, it is preferable to include 10% of phosphorus in the plating solution as an example, but the present invention is not limited to this, and it is effective to include phosphorus in the plating solution. Although the phosphorous-containing nickel plating layer alone has sufficient ability to reduce the oxides of the brazing material, the surface of the plating layer is matte, and it is called a bright nickel plating layer or a "bright nickel plating layer." Compared to a laminated layer of ``nickel plated layer containing phosphorus'', the exposed surface of the plated layer discolors significantly when heated, and even if the thickness of the plated layer is changed, the bonding property is extremely poor compared to a glossy plated layer. It was found that due to the inferior quality, the assembly process was slow and the reliability of the product was also incomplete. Therefore, the "bright nickel plating layer" and "nickel plating layer containing phosphorus" of the present application
According to the laminated layer, the following remarkable advantages are recognized.

‘1} ろう材のりードフレーム面および半導体素子裏
面へのなじみが良好なるため、半導体素子裏面全体に安
定してしかも均一にろう材が流れる様になり、製品の信
頼性も大幅に向上した。一例の重要な信頼性試験の一つ
に熱疲労試験があり、その結果を従来のものに比較して
第5図および第6図に夫々示す。各図において縦軸に熱
抵抗値(Rth)を単位(℃/W)にて、横軸に熱疲労
試験サイクル数(Cyc.)を夫々示し、第5図は従来
の半導体装置につき0−サイクル(試験前)分布と10
000−サイクル分布を、第6図はこの発明の一実施例
の半導体装置につき第5図の表わし方に準じて示すもの
である。両図を比較して特に本発明にか)る一実施例の
半導体装置は熱疲労試験10000−サイクル後におけ
る熱抵抗値の著大化が消滅し安定している。‘21 自
動組立工程での作業マージンも拡がったため、光沢ニッ
ケルめつき層のみの場合に比し歩留は15〜20%向上
した。{3’ 従来半導体素子をIJ−ドフレームにマ
ウントする際、接着力を向上するためにスクラブ時間が
多く(0.5〜1秒程度)必要であったが、ろう材表面
およびリードフレーム表面が活性化しなじみが非常に良
好であるため、スクラブ時間を1/4〜1/甥星度に低
減でき、インデックスが大幅に向上した。
'1} Because the brazing material blends well with the frame surface and the backside of the semiconductor element, the brazing material flows stably and evenly over the entire backside of the semiconductor element, greatly improving product reliability. . One example of an important reliability test is a thermal fatigue test, the results of which are shown in FIGS. 5 and 6, respectively, in comparison with conventional tests. In each figure, the vertical axis shows the thermal resistance value (Rth) in units (℃/W), and the horizontal axis shows the number of thermal fatigue test cycles (Cyc.). (Before the exam) Distribution and 10
FIG. 6 shows the 000-cycle distribution for a semiconductor device according to an embodiment of the present invention in accordance with the representation shown in FIG. Comparing both figures, the semiconductor device according to one embodiment of the present invention is stable, with no significant increase in thermal resistance after 10,000 cycles of the thermal fatigue test. '21 Because the work margin in the automatic assembly process has been expanded, the yield has improved by 15 to 20% compared to the case of only a bright nickel plating layer. {3' Conventionally, when mounting a semiconductor device on an IJ-board frame, a long scrubbing time (approximately 0.5 to 1 second) was required to improve the adhesive strength, but the surface of the brazing material and lead frame Since it is activated and blends in very well, the scrubbing time can be reduced to 1/4 to 1/4 degrees, and the index has been significantly improved.

これにより、この工程の自動化ができるようになった。
‘4’不活性ガスまたは還元性ガスの使用量も非常に少
なくて済むようになり、自動組立機の構造も従来ほど注
意を払う必要がなくなった。
This has made it possible to automate this process.
'4' The amount of inert gas or reducing gas used is also very small, and the structure of automatic assembly machines does not require as much attention as before.

以上の如くなるこの発明は半導体基板に光沢電解ニッケ
ルめつき層を介して積層被着されたリンを含むニッケル
めつき層を備えるリードフレームを使用することにより
、はんだなどのろう材の酸化物を還元させてリードフレ
ーム、ろう材、半導体素子とのなじみを良好にせしめ、
半導体素子の配設側主面(裏面)全体に所望の如くろう
材が均一に流れる如くした。
The present invention as described above uses a lead frame equipped with a phosphorous-containing nickel plating layer laminated on a semiconductor substrate via a bright electrolytic nickel plating layer, thereby eliminating oxides of brazing materials such as solder. It is reduced to improve compatibility with lead frames, brazing filler metals, and semiconductor elements.
The brazing material was made to flow uniformly as desired over the entire main surface (back surface) on the side where the semiconductor element was disposed.

このため、さらには製品の信頼性をも完全ならしめた。
なお、上記素子配設部において、電解ニッケル・リン合
金めつきに代り、リンを数%含有する無電解ニッケルめ
つき層を設けてもよい。
This has further ensured the reliability of the product.
In addition, in the above-mentioned element arrangement part, an electroless nickel plating layer containing several percent of phosphorus may be provided instead of the electrolytic nickel-phosphorus alloy plating.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は半導体装置の斜視図、第2図は半導体装置マウ
ント部の上面図、第3図は第2図の一部の断面図、第4
図はこの発明の一実施例の半導体装置のマウント部の一
部の断面図、第5図は従来の、また第6図は本発明の一
実施例のいずれも半導体装置の熱疲労試験の結果を示す
分布図である。 なお、図中同一符号は同一または相当部分を夫々示すも
のとする。la〜lc・・・・・・半導体装置のリード
、2・・・・・・樹脂封止体、3,13・・・・・・放
熱板を兼ねる素子配設台床部,3a,13a・・・・・
・素子配設台床部の基材、3b・・・・・・光沢ニッケ
ルめつき層、13b・・・・・・リンを含有ニッケルめ
つき層、4・・・・・・半導体素子、6,16……ろう
層(ろう材)。 第1図 第2図 第3図 第4図 第5図 第6図
FIG. 1 is a perspective view of the semiconductor device, FIG. 2 is a top view of the semiconductor device mount, FIG. 3 is a cross-sectional view of a part of FIG. 2, and FIG.
The figure is a cross-sectional view of a part of the mounting part of a semiconductor device according to an embodiment of the present invention, FIG. 5 is a conventional one, and FIG. 6 is an embodiment of the present invention. FIG. Note that the same reference numerals in the figures indicate the same or corresponding parts, respectively. la to lc...Semiconductor device leads, 2...Resin sealing body, 3, 13...Element placement platform floor that also serves as a heat sink, 3a, 13a.・・・・・・
・Base material of element placement base floor, 3b... Bright nickel plating layer, 13b... Nickel plating layer containing phosphorus, 4... Semiconductor element, 6 , 16... Brazing layer (brazing material). Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims] 1 銅または銅合金でなるリードフレームにおける少く
とも素子配設台床部に光沢ニツケルめつき層とこれに積
層したリン含有ニツケル層を設け、このリン含有ニツケ
ルめつき層に半導体素子を鑞接したことを特徴とする半
導体装置。
1. A bright nickel plating layer and a phosphorus-containing nickel layer laminated thereon are provided on at least the element mounting base of a lead frame made of copper or copper alloy, and a semiconductor element is soldered to this phosphorus-containing nickel plating layer. A semiconductor device characterized by:
JP1543479A 1979-02-15 1979-02-15 semiconductor equipment Expired JPS6033312B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1543479A JPS6033312B2 (en) 1979-02-15 1979-02-15 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1543479A JPS6033312B2 (en) 1979-02-15 1979-02-15 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS55108757A JPS55108757A (en) 1980-08-21
JPS6033312B2 true JPS6033312B2 (en) 1985-08-02

Family

ID=11888684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1543479A Expired JPS6033312B2 (en) 1979-02-15 1979-02-15 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6033312B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
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JP2017208461A (en) * 2016-05-19 2017-11-24 Shプレシジョン株式会社 Lead frame and manufacturing method of lead frame

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JPS57145351A (en) * 1981-03-04 1982-09-08 Hitachi Cable Ltd Lead frame for semiconductor
JPS59149042A (en) * 1983-02-15 1984-08-25 Hitachi Cable Ltd Lead frame for semiconductor
JPH0620083B2 (en) * 1986-02-06 1994-03-16 富士電機株式会社 Method for manufacturing semiconductor device
JP2767821B2 (en) * 1988-07-25 1998-06-18 株式会社 神戸製鋼所 Lead frame for semiconductor device
US8637165B2 (en) * 2011-09-30 2014-01-28 Apple Inc. Connector with multi-layer Ni underplated contacts
US9004960B2 (en) 2012-08-10 2015-04-14 Apple Inc. Connector with gold-palladium plated contacts

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017208461A (en) * 2016-05-19 2017-11-24 Shプレシジョン株式会社 Lead frame and manufacturing method of lead frame

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