JP2000174191A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JP2000174191A
JP2000174191A JP10347141A JP34714198A JP2000174191A JP 2000174191 A JP2000174191 A JP 2000174191A JP 10347141 A JP10347141 A JP 10347141A JP 34714198 A JP34714198 A JP 34714198A JP 2000174191 A JP2000174191 A JP 2000174191A
Authority
JP
Japan
Prior art keywords
plating film
alloy
semiconductor device
content
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10347141A
Other languages
Japanese (ja)
Inventor
Hiroaki Okudaira
弘明 奥平
Kichiji Inaba
吉治 稲葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10347141A priority Critical patent/JP2000174191A/en
Publication of JP2000174191A publication Critical patent/JP2000174191A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a crack and a whisker on a tin alloy-plated film by forming a concentration gradient so as to increase a content of the alloy content in a thickness direction of the film in the case of tin-alloy plating external leads. SOLUTION: After a lead having a width of 3 mm, a length of 15 mm and a thickness of 0.15 mm is normally degreased and pickled, the lead is tin-bismuth alloy-plated by a plating solution containing an organic acid, an organic stannic acid (tin concentration of 55 g/l), an organic bismuthic acid (bismuth concentration of 0.8 g/1) and an additive of 30 ml/l. A current density when the plating is started is set to 20 A/dm2, and a lower layer (near a lead base material) plating film 7 of a bismuth content of 0.7 wt.% is formed. Then, the density is reduced to 5 A/dm2, and an intermediate layer plated film 9 (film thickness of 5 μm) continuously changing from the bismuth content of 0.7 wt.% to 2.3 wt.% is formed. Subsequently, the density is maintained at 5 A/dm2, and an upper layer (near a surface) plated film 8 (5 μm of a film thickness together with the film 7 is formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の外部
リードの表面に鉛を含まないスズ合金めっき膜を形成し
た半導体装置の改良及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device in which a lead-free tin alloy plating film is formed on the surface of external leads of the semiconductor device, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】ＩＣ、ＬＳＩなどの半導体素子は、いわ
ゆるパッケージング工程において、リードフレーム上に
固着された後、ワイヤボンデイングなどによりリードフ
レームと電気的に接続され、さらにモールド樹脂により
モールドされる。そして、基板などの外部回路とはんだ
等を用いて接続するために、モールド樹脂の外側に露出
したリード（外部リードと云う）には、主に鉛を１０〜
４０ｗｔ％含むスズー鉛合金、いわゆる鉛はんだめっき
が施され、その後リードはフレームから切断され、所定
の形状に曲げ成形される。このため、リードに対するめ
っきには、はんだ濡れ性、耐熱性、耐ウイスカ性、密着
性、折り曲げ性、耐食性等の特性が要求される。鉛はん
だめっきはこれらの要求特性を全て満足し、現行製品に
広く使用されている。2. Description of the Related Art In a so-called packaging process, a semiconductor element such as an IC or an LSI is fixed on a lead frame, is electrically connected to the lead frame by wire bonding, and is molded with a molding resin. In order to connect to an external circuit such as a substrate using solder or the like, lead (external lead) exposed to the outside of the mold resin is mainly made of lead.
A tin-lead alloy containing 40 wt%, so-called lead solder plating, is applied, and then the lead is cut from the frame and bent into a predetermined shape. For this reason, plating on the leads is required to have properties such as solder wettability, heat resistance, whisker resistance, adhesion, bending properties, and corrosion resistance. Lead solder plating satisfies all of these required characteristics and is widely used in current products.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、近年の
環境問題の中で鉛による環境汚染が大きな問題となって
いる。鉛はんだに関しては、家電製品、自動車部品など
の電機部品の接合材料として広く使用されており、これ
らが廃棄物としてシュレッダーダスト化され屋外に廃棄
されたとき、酸性雨等の酸性雰囲気に曝されると、はん
だ中の鉛が溶出して、地下水を汚染することが問題とな
ってきている。そこで、鉛を含まないいわゆる鉛フリー
はんだの開発が進められ、Ｓｎ−Ａｇ−Ｂｉ系、Ｓｎ−
Ｚｎ−Ｂｉ系等の鉛フリーはんだが開発されている。However, among the recent environmental problems, environmental pollution due to lead has become a major problem. Lead solder is widely used as a bonding material for electrical parts such as home appliances and automobile parts, and when exposed to shredder dust as waste, is exposed to acidic atmospheres such as acid rain. This leads to a problem that lead in the solder is eluted and contaminates the groundwater. Therefore, the development of lead-free solder, which does not contain lead, has been promoted, and Sn-Ag-Bi-based, Sn-
Lead-free solders such as Zn-Bi have been developed.

【０００４】さらに、鉛フリーはんだに対応する鉛フリ
ーはんだめっきの開発も進められ、めっき膜材料として
はパラジウム、スズ−亜鉛合金（例えば特開平４−２１
２４４３号公報）、スズ−銀合金、スズ−ビスマス合金
などが挙げられている。[0004] Further, development of lead-free solder plating corresponding to lead-free solder has been advanced, and palladium, tin-zinc alloy (for example, Japanese Patent Application Laid-Open No.
2443), a tin-silver alloy, a tin-bismuth alloy, and the like.

【０００５】しかし、これらの合金めっき膜はいずれも
大きな欠点がある。例えばパラジウムは、耐食性の点で
リード材の主流である鉄−ニッケル合金である４２アロ
イには適用できない。スズ−亜鉛合金は酸化されやすく
濡れ性が劣り、ウィスカも発生しやすい。ウィスカが発
生すると間隔の狭いリード間で電気的な短絡を生じる。
スズ−銀合金は加熱により表面が青く変色して濡れ性が
低下する。However, all of these alloy plating films have a major drawback. For example, palladium cannot be applied to a 42 alloy which is an iron-nickel alloy which is a mainstream lead material in terms of corrosion resistance. Tin-zinc alloys are easily oxidized, have poor wettability, and are liable to generate whiskers. When whiskers occur, an electrical short circuit occurs between closely spaced leads.
The surface of the tin-silver alloy turns blue due to heating, and the wettability decreases.

【０００６】また、スズ−ビスマス合金は硬く、脆いた
め上記の半導体素子の成形工程においてリードを曲げた
ときにめっき膜にクラックが生じる。そのため、リード
を折り曲げた後に加熱工程を通すとリード表面が酸化さ
れ、濡れ性が低下する。また、耐食性も低下する。この
ようにいずれのスズ合金も大きな欠点があるため、従来
のスズ−鉛合金の代替めっき膜として用いることはでき
ない。[0006] Further, since the tin-bismuth alloy is hard and brittle, cracks occur in the plating film when the lead is bent in the above-described semiconductor element forming step. Therefore, if the heating step is performed after bending the lead, the lead surface is oxidized, and the wettability is reduced. Also, the corrosion resistance is reduced. As described above, any of the tin alloys has a major drawback, and thus cannot be used as a plating film alternative to the conventional tin-lead alloy.

【０００７】また、東芝技術公開集ＶＯＬ．１５−６
２、発行番号９７−０６４７、第６１頁および第６２頁
（発行日：１９９７−９−２９）には、リード母材部分
に下地めっき部分としてスズめっきまたはスズ合金めっ
きを施し、表面めっき部分にスズベースで２元以上の合
金めっき（例えばＳｎＡｇ、ＳｎＺｎ、ＳｎＢｉなど）
を施すことが記載されている。しかしながら、クラック
やウイスカの発生を無くすことについては、考慮されて
いない。Further, Toshiba Technical Publication Vol. 15-6
2. On the issue number 97-0647, pages 61 and 62 (issue date: 1997-9-29), tin plating or tin alloy plating is applied to the lead base material portion as a base plating portion, and the surface plating portion is provided. Tin-based alloy plating of two or more elements (eg, SnAg, SnZn, SnBi, etc.)
Is described. However, no consideration is given to eliminating generation of cracks and whiskers.

【０００８】本発明の目的は、上記従来技術の課題を解
決すべく、鉛フリーはんだめっきを用いて、クラックの
発生を防止して濡れ性の低下が無く、しかも耐ウイスカ
性、耐食性などに優れた曲げ成形されたリードを有する
信頼性の高い半導体装置を実現して、基板に濡れ性を低
下させることなく高信頼度ではんだ接続実装できるよう
にした半導体装置およびその製造方法と実装構造体とを
提供することにある。An object of the present invention is to solve the above-mentioned problems of the prior art by using a lead-free solder plating to prevent the occurrence of cracks so that there is no decrease in wettability and to be excellent in whisker resistance and corrosion resistance. Semiconductor device having a highly reliable semiconductor device having bent and formed leads, and capable of being soldered and mounted with high reliability without deteriorating wettability on a substrate, a method of manufacturing the same, and a mounting structure. Is to provide.

【０００９】[0009]

【課題を解決するための手段】本発明者等は、スズ合金
めっき膜中の合金成分について膜厚方向の含有率、膜厚
等について種々検討したところ、従来の技術では予想も
着かない新しい知見が得られ、この知見に基づいて本発
明をするに至った。すなわち、合金成分を例えばビスマ
スまたは銀とした場合、従来はこれらの合金成分をスズ
合金めっき膜中において可能な限り均一に分散させよう
と努力してきた。しかし、前述の通りの問題が発生し
た。Means for Solving the Problems The present inventors conducted various studies on the content, thickness, etc. of the alloy components in the tin alloy plating film in the thickness direction, and found that new knowledge that could not be expected with the conventional technology was obtained. Was obtained, and the present invention was accomplished based on this finding. That is, when the alloy component is, for example, bismuth or silver, conventionally, an effort has been made to disperse these alloy components as uniformly as possible in the tin alloy plating film. However, the problem described above has occurred.

【００１０】ところが、本発明では半導体装置の外部リ
ードにスズ合金をめっきする際に、めっき膜の厚さ方向
に合金成分含有率が増加するようにスズ合金めっき膜を
形成する。つまり、リード表面にスズ合金めっき膜を形
成する際に、めっき膜の膜厚方向に例えばＢｉやＡｇ等
の鉛を含まない合金成分に濃度勾配を設けることによ
り、従来技術の問題点を解消させることができたもので
ある。However, in the present invention, when a tin alloy is plated on an external lead of a semiconductor device, the tin alloy plating film is formed so that the alloy component content increases in the thickness direction of the plating film. That is, when a tin alloy plating film is formed on the lead surface, the problem of the prior art is solved by providing a concentration gradient in a lead-free alloy component such as Bi or Ag in the thickness direction of the plating film. It was something that could be done.

【００１１】すなわち、上記目的を達成するために、本
発明は、曲げ成形された外部リードを有する半導体装置
において、前記リード表面に、めっき膜厚方向に合金成
分含有率が増加するように、スズ合金めっき膜中の合金
成分に膜厚方向の濃度勾配を設けたことを特徴とする。That is, in order to achieve the above object, the present invention relates to a semiconductor device having a bent external lead, wherein tin is formed on the surface of the lead such that the alloy component content increases in the plating film thickness direction. It is characterized in that a concentration gradient in the thickness direction is provided for the alloy component in the alloy plating film.

【００１２】上記スズ合金めっき膜中の合金成分に膜厚
方向の濃度勾配を設けるに際して、先ず実用的に好まし
い合金成分としては、例えばビスマス、銀、亜鉛、イン
ジウム及びアンチモンの少なくとも１種が挙げられ、か
つ膜厚方向の好ましい濃度勾配は、めっき膜の下層の合
金成分の含有率を１ｗｔ％以下とし、上層の含有率を１
ｗｔ％以上とすることである。When providing a concentration gradient in the thickness direction of the alloy component in the tin alloy plating film, at least one of bismuth, silver, zinc, indium and antimony may be mentioned as a practically preferable alloy component. The preferred concentration gradient in the film thickness direction is such that the content of the alloy component in the lower layer of the plating film is 1 wt% or less and the content of the upper layer is 1 wt%.
wt% or more.

【００１３】極端な場合、下層の合金成分の含有率を１
ｗｔ％以下とし、上層を避けられない不純物を除き合金
成分のみの１００ｗｔ％としてもよい。In an extreme case, the content of the alloy component in the lower layer is set to 1
wt% or less, and 100 wt% of the alloy component alone except for impurities that cannot avoid the upper layer.

【００１４】また、スズ合金めっき膜の厚さを１０μｍ
とした場合、めっき膜の表面近傍の合金成分含有率が１
ｗｔ％以上である部分の膜厚が１μｍ以上であり、リー
ド基材近傍の合金成分含有率が１ｗｔ％以下の部分の膜
厚が２μｍ以上であることが望ましい。Further, the thickness of the tin alloy plating film is 10 μm.
, The alloy component content near the surface of the plating film is 1
It is desirable that the thickness of the portion where the content is not less than 1 wt% is 1 μm or more, and the thickness of the portion where the alloy component content is 1 wt% or less near the lead base material is 2 μm or more.

【００１５】また、本発明は、前記半導体装置におい
て、スズ合金めっき膜におけるクラックおよびウイスカ
の発生を防止すること目的とするするものであり、その
ためには特に、リード基材近傍のめっき膜において例え
ばビスマス含有率を１ｗｔ％以下にすることによってク
ラックの発生を防止し、表面近傍のめっき膜においてビ
スマス含有率を１ｗｔ％以上にすることによってウイス
カの発生を防止することができる。Another object of the present invention is to prevent the occurrence of cracks and whiskers in a tin alloy plating film in the semiconductor device. Cracking can be prevented by setting the bismuth content to 1 wt% or less, and whisker formation can be prevented by setting the bismuth content to 1 wt% or more in the plating film near the surface.

【００１６】また、本発明においては、外部リード基材
の表面に下地膜として１〜１０μｍ膜厚の銅めっきを施
すことが望ましい。Further, in the present invention, it is desirable to apply copper plating having a thickness of 1 to 10 μm as a base film on the surface of the external lead base material.

【００１７】また、本発明は、上記のように外部リード
基材の表面に、めっき膜厚方向に合金成分含有率が増加
するように形成したスズ合金めっき膜を有する曲げ成形
された複数のリードを備えた半導体装置を、前記複数の
リードを所定の配線基板上の電極にはんだ接続したこと
を特徴とする半導体装置の実装構造体をも含むものであ
る。The present invention also provides a plurality of bent leads having a tin alloy plating film formed on the surface of the external lead base material such that the alloy component content increases in the plating film thickness direction. And a mounting structure of the semiconductor device, wherein the plurality of leads are soldered to electrodes on a predetermined wiring board.

【００１８】以上説明したように、前記構成によれば、
樹脂封止後の外部リード成型時の折り曲げによるクラッ
クの発生に伴う濡れ性の低下がなく、かつウイスカの発
生もなく、耐食性などに優れた半導体装置及びその実装
構造体を製造することが可能となった。As described above, according to the above configuration,
It is possible to manufacture a semiconductor device excellent in corrosion resistance and the like and a mounting structure thereof without a decrease in wettability due to the occurrence of cracks due to bending during molding of an external lead after resin sealing, and no whisker. became.

【００１９】[0019]

【発明の実施の形態】本発明に係る半導体装置およびそ
の実装構造体の実施の形態について以下、図を用いて説
明する。図１は、本発明に係る樹脂封止された半導体装
置の断面図を示しており、実施の形態の全体を示す概略
構成図である。半導体装置は、半導体素子と熱膨張率が
合わせられた鉄−ニッケル合金である４２アロイまたは
その表面に１〜１０μｍの厚さの銅めっきが施されたリ
ードフレーム（リード基材）２上にＩＣ、ＬＳＩなどの
半導体素子１を固定した後、半導体素子１の不図示の電
極をワイヤボンデイング３などによりリードフレームと
電気的に接続詞、モールド樹脂４により樹脂封止されて
製造される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a mounting structure thereof according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a resin-sealed semiconductor device according to the present invention, and is a schematic configuration diagram showing an entire embodiment. The semiconductor device is composed of a 42 alloy, which is an iron-nickel alloy having a coefficient of thermal expansion matched with that of the semiconductor element, or a lead frame (lead base) 2 having a surface plated with copper having a thickness of 1 to 10 μm. After fixing the semiconductor element 1 such as an LSI, an electrode (not shown) of the semiconductor element 1 is electrically connected to a lead frame by a wire bonding 3 or the like, and is resin-sealed with a mold resin 4 to manufacture the semiconductor element 1.

【００２０】そして、モールド樹脂４の外側に露出した
リードフレーム（リード基材）２に対して、脱脂、酸洗
処理したのち、有機酸、有機酸スズ、有機酸ビスマスま
たは有機酸銀および添加剤からなるめっき液を用いて、
図２に断面を示すように、リード表面に、めっき膜厚の
表面方向に向かって合金成分含有率が増加するようにス
ズ合金めっき膜を形成する。その後、リード５はフレー
ムから切断され、所定形状に折り曲げ成形される。The lead frame (lead substrate) 2 exposed outside the mold resin 4 is degreased and pickled, and then treated with an organic acid, an organic tin, an organic bismuth or an organic silver, and an additive. Using a plating solution consisting of
As shown in the cross section in FIG. 2, a tin alloy plating film is formed on the lead surface such that the alloy component content increases toward the surface direction of the plating film thickness. After that, the lead 5 is cut from the frame and bent into a predetermined shape.

【００２１】以上により、本発明に係る半導体装置が完
成されたことになる。このように完成された半導体装置
のリード（外部リード）５は、不図示の配線基板などの
外部回路に設けられた電極と鉛フリーはんだ等を用いて
はんだ接続（はんだ接合）されて実装されることにな
る。Thus, the semiconductor device according to the present invention is completed. The leads (external leads) 5 of the semiconductor device completed in this manner are mounted by soldering (solder bonding) to electrodes provided on an external circuit such as a wiring board (not shown) using lead-free solder or the like. Will be.

【００２２】図２には、一例としてリード基材６の表面
に、クラックの発生しにくいビスマスまたは銀含有率の
低い（１ｗｔ％以下）スズ−ビスマスまたは銀合金めっ
き膜７（下層）を表面近傍に、それよりビスマスまたは
銀含有率が高く（１ｗｔ％以上）、ウイスカが発生しな
いスズ−ビスマスまたは銀合金めっき膜８（上層）をリ
ード基材近傍に、それらの間に中間層９を形成した構造
を示す。この中間層９は合金成分であるビスマスまたは
銀の含有率が、下層と上層との中間にあり、その含有率
は上層方向に連続的に増加するように濃度勾配を設けて
もよいし、中間の一定含有率としてもよい。FIG. 2 shows, as an example, a tin-bismuth or silver alloy plating film 7 (lower layer) having a low content of bismuth or silver (less than 1 wt%) in which cracks are less likely to be generated on the surface of the lead substrate 6 near the surface. Then, a tin-bismuth or silver alloy plating film 8 (upper layer) having a higher bismuth or silver content (1 wt% or more) and free from whiskers was formed near the lead substrate, and an intermediate layer 9 was formed between them. The structure is shown. In the intermediate layer 9, the content of bismuth or silver, which is an alloy component, is between the lower layer and the upper layer, and the content may be provided with a concentration gradient such that the content continuously increases in the upper layer direction. May be constant.

【００２３】リード基材近傍のめっき膜７（下層）とし
て、ビスマスまたは銀含有率が１ｗｔ％以下のスズ−ビ
スマスまたはスズ−銀合金からなることにより、リード
成型時の折り曲げ（規格は曲げ半径がリード基材の厚さ
と同じ０．１５ｍｍ、現実には曲げ半径が０．２５ｍｍ
程度である）によるクラックの発生が防止されて、濡れ
性の低下をなくすことができ、表面近傍のめっき膜８
（上層）として、ビスマスまたは銀含有率が１ｗｔ％以
上のスズ−ビスマスまたはスズ−銀合金からなることに
より、ウイスカが発生しないため、間隔の狭いリードで
もウイスカ発生によるリード間の電気的短絡を防止し、
しかもリード成型時の折り曲げによるクラックの発生を
防止して、濡れ性の低下をなくすことができ、さらに優
れた耐食性を有する鉛フリーはんだめっきを施すことが
できる。Since the plating film 7 (lower layer) near the lead substrate is made of tin-bismuth or a tin-silver alloy having a bismuth or silver content of 1% by weight or less, bending at the time of forming the lead (the bending radius is a standard). 0.15mm, the same as the thickness of the lead base material, the bending radius is actually 0.25mm
), The occurrence of cracks is prevented, and a decrease in wettability can be prevented.
As the (upper layer) is made of tin-bismuth or a tin-silver alloy having a bismuth or silver content of 1 wt% or more, whiskers are not generated, so that even short leads are prevented from short-circuiting between leads due to whisker formation. And
Moreover, it is possible to prevent the occurrence of cracks due to bending at the time of lead molding, to prevent a decrease in wettability, and to apply lead-free solder plating having more excellent corrosion resistance.

【００２４】即ち、リード基材近傍のめっき膜７（下
層）上に、一定量（１ｗｔ％）以上のビスマスまたは銀
を含有するめっき膜８（上層）を形成すれば、ビスマス
および銀はウイスカを防止する作用があるため、基材近
傍のめっき膜７によるウイスカの発生を防止することが
できる。That is, if a plating film 8 (upper layer) containing a certain amount (1 wt%) or more of bismuth or silver is formed on the plating film 7 (lower layer) in the vicinity of the lead substrate, the bismuth and silver become whiskers. Since it has an effect of preventing, it is possible to prevent the generation of whiskers due to the plating film 7 near the base material.

【００２５】また、リードの折り曲げ時に表面近傍のめ
っき膜８にクラックが発生しても、表面近傍のめっき膜
８または中間層９で留まり、基材近傍のめっき膜７には
達しない。そのためリードを折り曲げた後に加熱工程を
通してもリードの表面が酸化されて、濡れ性が低下する
ことはない。また、クラックがリード基材６の表面に達
しないため耐食性が低下することもない。Further, even if a crack occurs in the plating film 8 near the surface when the lead is bent, the crack remains in the plating film 8 or the intermediate layer 9 near the surface and does not reach the plating film 7 near the base material. Therefore, even when the lead is bent and the heating step is performed, the surface of the lead is not oxidized and the wettability is not reduced. Further, since the crack does not reach the surface of the lead base material 6, the corrosion resistance does not decrease.

【００２６】リードフレームの基材は、鉄−ニッケル合
金である４２アロイでも４２アロイに銅めっきを施した
ものでも銅合金でも特に制限するものではない。The base material of the lead frame is not particularly limited to a 42 alloy, which is an iron-nickel alloy, a 42 alloy plated with copper, or a copper alloy.

【００２７】めっき膜中のビスマス含有率とめっき処理
時の電流密度との間には、めっき液中のビスマス濃度が
一定のとき、図３に示すように電流密度が小さいときほ
どビスマス含有率は大きく、電流密度が大きいときほど
ビスマス含有率は小さくなる関係がある。従って、リー
ド基材にスズ−ビスマス合金めっきを行うとき、めっき
初期の電流密度を大きくし、めっき終期の電流密度を小
さくすれば、基材近傍にビスマス含有率が低く、表面近
傍にビスマス含有率が高いめっき膜を同一のめっき液中
で形成することができる。Between the bismuth content in the plating film and the current density during the plating process, when the bismuth concentration in the plating solution is constant, as shown in FIG. The larger the current density, the smaller the bismuth content. Therefore, when performing tin-bismuth alloy plating on a lead substrate, if the current density at the beginning of plating is increased and the current density at the end of plating is reduced, the bismuth content near the substrate is low, and the bismuth content near the surface is low. Can be formed in the same plating solution.

【００２８】即ち、図３を例にとれば、初期に電流密度
２０Ａ／ｄｍ2でめっきを行い、終期に電流密度５Ａ／
ｄｍ2でめっきを行えば、リード基材近傍（下層）にビ
スマス含有率０．７ｗｔ％のめっき膜が形成され、表面
近傍（上層）にビスマス含有率２．３ｗｔ％のメッキ膜
がが形成できる。それぞれのめっき時間は、リード基材
近傍のビスマス含有率０．７ｗｔ％のめっき膜厚が２μ
ｍ以上、表面近傍のビスマス含有率２．３ｗｔ％のめっ
き膜厚が１μｍ以上になるように設定すればよい。That is, taking FIG. 3 as an example, plating is performed at a current density of 20 A / dm 2 at the initial stage, and at a current density of 5 A / dm 2 at the end stage.
If plating is performed at dm 2 , a plating film with a bismuth content of 0.7 wt% can be formed near the lead substrate (lower layer), and a plating film with a bismuth content of 2.3 wt% can be formed near the surface (upper layer). . Each plating time is 2 μm in the plating film thickness of 0.7 wt% bismuth near the lead substrate.
m or more and the plating film thickness of the bismuth content of 2.3 wt% near the surface may be set to 1 μm or more.

【００２９】また、それらの中間のめっき膜のビスマス
含有率は、電流密度を連続的に減少させて、０．７ｗｔ
％から２．３ｗｔ％へと連続的に変化させても、電流密
度を２０Ａ／ｄｍ2から５Ａ／ｄｍ2へと段階的に変化さ
せて１層または２層以上の多層構造にしても差し支えな
い。以上ビスマスについて記したが銀その他の合金成分
である亜鉛、インジウム及びアンチモン等についても同
様である。Further, the bismuth content of the intermediate plating film is set to 0.7 wt% by continuously reducing the current density.
% To 2.3 wt%, the current density may be changed stepwise from 20 A / dm 2 to 5 A / dm 2 to form a single layer or a multilayer structure of two or more layers. . As described above, bismuth is described, but the same applies to silver and other alloy components such as zinc, indium and antimony.

【００３０】また、本発明においては、上記電流密度に
基づくスズ合金めっき方法の他に以下に説明する方法に
よっても形成することができる。スズ−ビスマスめっ
き、スズ―銀めっきの例を代表して説明すると、スズ−
ビスマス、スズ―銀めっきにおいては、スズに比べてビ
スマスおよび銀の電位が高いため、めっき液中にスズま
たはスズ含有率の高いスズ合金を浸漬するとスズが溶出
してビスマスまたは銀が析出するいわゆる置換反応が生
じる。この置換反応を利用すると上記の例と同様に同一
のめっき液中で、ビスマスまたは銀含有率の異なるめっ
き膜を形成することができる。In the present invention, in addition to the above-described tin alloy plating method based on the current density, it can be formed by a method described below. As an example of tin-bismuth plating and tin-silver plating,
In bismuth and tin-silver plating, the potential of bismuth and silver is higher than that of tin, so when tin or a tin alloy with a high tin content is immersed in the plating solution, tin elutes and bismuth or silver precipitates. A substitution reaction occurs. By utilizing this substitution reaction, plating films having different bismuth or silver contents can be formed in the same plating solution as in the above-described example.

【００３１】即ち、図４に示すように、電気メッキ時の
めっき電流波形にパルスを用いると、パルスの通電時間
ｔにおいてはスズ―ビスマス合金めっき膜が析出し、通
電休止時間ｓではビスマス置換反応膜が析出する。これ
をパルス波形によって繰り返すことにより、図５の断面
図に示すようにリード基材６上にスズ―ビスマス合金め
っき膜（通電時間に析出）１０とビスマス置換反応膜
（通電休止時間に析出）１１との層状のめっき膜が得ら
れる。That is, as shown in FIG. 4, when a pulse is used for the plating current waveform at the time of electroplating, a tin-bismuth alloy plating film is deposited during the energization time t of the pulse, and the bismuth substitution reaction is performed during the energization suspension time s. A film is deposited. By repeating this with a pulse waveform, as shown in the cross-sectional view of FIG. 5, a tin-bismuth alloy plating film (deposited during energization time) 10 and a bismuth substitution reaction film (deposited during energization suspension time) 11 on lead substrate 6 Is obtained.

【００３２】このとき、通電時間ｔに比べて休止時間ｓ
を短くすれば、ビスマス置換反応膜１１は薄くなりビス
マス含有率の小さいめっき膜が得られ、休止時間ｓを長
くすれば、ビスマス置換反応膜１１は厚くなってビスマ
ス含有率がより大きいめっき膜が得られる。従って、同
一のめっき液において、めっき初期においては休止時間
ｓを短く、めっき終期には休止時間ｓを長くすればリー
ド基材近傍（下層）にはビスマス含有率の小さいめっき
膜が形成され、表面近傍（上層）にはビスマス含有率の
高いめっき膜が形成される。At this time, the pause time s is compared with the energization time t.
If the length is shortened, the bismuth substitution reaction film 11 becomes thin and a plating film having a small bismuth content can be obtained. If the pause time s is lengthened, the bismuth substitution reaction film 11 becomes thick and a plating film having a large bismuth content is obtained. can get. Therefore, in the same plating solution, if the pause time s is short at the beginning of plating and the pause time s is long at the end of plating, a plating film with a low bismuth content is formed near the lead substrate (lower layer), In the vicinity (upper layer), a plating film having a high bismuth content is formed.

【００３３】上記の電流密度を変化させる方法とパルス
電流の休止時間を用いる方法とを組み合わせると、さら
にビスマス含有率の差の大きいめっき膜を形成すること
ができる。即ち、めっき初期には電流密度を大きく、か
つ休止時間を短くし、めっき終期には電流密度を小さ
く、かつ休止時間を長くすることにより、リード基材近
傍（下層）にはビスマス含有率の小さいめっき膜が形成
され、表面近傍（上層）にはビスマス含有率のより大き
なめっき膜が形成される。By combining the above-described method of changing the current density with the method of using the pause time of the pulse current, it is possible to form a plating film having a larger difference in bismuth content. That is, by increasing the current density and shortening the pause time at the beginning of plating, and decreasing the current density and increasing the pause time at the end of plating, the bismuth content near the lead substrate (lower layer) is low. A plating film is formed, and a plating film having a higher bismuth content is formed near the surface (upper layer).

【００３４】[0034]

【実施例】次に、本発明に係る鉛フリースズ合金はんだ
めっき膜構造の実施例について具体的に説明する。Next, an embodiment of a lead-free tin alloy solder plating film structure according to the present invention will be described in detail.

【００３５】〈実施例１〉４２アロイを基材とする幅３
ｍｍ、長さ１５ｍｍ、厚さ０．１５ｍｍのリードを１０
本連ねたテストサンプルを通常の方法で脱脂、酸洗処理
した後、有機酸、有機酸スズ（スズ濃度５５ｇ／ｌ）、
有機酸ビスマス（ビスマス濃度０．８ｇ／ｌ）および添
加剤３０ｍｌ／ｌからなるめっき液を用いてスズ―ビス
マス合金めっきを行った。Example 1 Width 3 made of 42 alloy
mm, length 15mm, thickness 0.15mm lead 10
After degreasing and pickling treatment of the series of test samples in a usual manner, an organic acid, an organic tin (a tin concentration of 55 g / l),
Tin-bismuth alloy plating was performed using a plating solution comprising an organic acid bismuth (bismuth concentration 0.8 g / l) and an additive 30 ml / l.

【００３６】めっき膜のビスマス含有率と電流密度の関
係は図３に示したとおりである。めっき開始時の電流密
度を２０Ａ／ｄｍ2に設定してビスマス含有率０．７ｗ
ｔ％の下層（リード基材近傍）めっき膜を形成し、つい
で電流密度を連続的に５Ａ／ｄｍ2まで減少してビスマ
ス含有率０．７ｗｔ％から２．３ｗｔ％に連続的に変化
する中間層めっき膜を形成し、その後引き続き電流密度
を５Ａ／ｄｍ2に維持してビスマス含有率２．３ｗｔ％
の上層（表面近傍）めっき膜を形成した。The relationship between the bismuth content of the plating film and the current density is as shown in FIG. The current density at the start of plating was set to 20 A / dm 2 and the bismuth content 0.7 w
forming a lower plating film (near the lead base material) of t%, and then continuously decreasing the current density to 5 A / dm 2 to continuously change the bismuth content from 0.7 wt% to 2.3 wt%. After forming a layer plating film, the current density is maintained at 5 A / dm 2 and the bismuth content is 2.3 wt%.
The upper (near the surface) plating film was formed.

【００３７】めっき膜厚は中間層を５μｍとし、上層と
下層とを合わせて５μｍ、全体で１０μｍとなるように
形成し、表１に示す試料Ｎｏ．１〜６の組合せとした。
めっきの終了したサンプルを１本ずつのリードに切り離
し、以下の評価を行った。The thickness of the plating layer was 5 μm for the intermediate layer, the upper layer and the lower layer were formed so as to be 5 μm in total, and 10 μm in total. 1 to 6 were used.
The sample after plating was cut into individual leads, and the following evaluation was performed.

【００３８】曲げ半径０．１５ｍｍおよび０．２５ｍｍ
の曲げ治具を用いて９０°曲げ試験を行い、曲げ部のク
ラックの発生状況を顕微鏡で観察した。ついでそのサン
プルを１５０℃で１６８時間加熱し、ディップ法により
濡れ性を評価した。また、温度８５℃、湿度８５％の環
境に３３６時間放置した後のウィスカの発生状況を顕微
鏡で観察した。その結果は表１に示すとおりである。Bending radii of 0.15 mm and 0.25 mm
A 90 ° bending test was performed using the bending jig described above, and the occurrence of cracks in the bent portion was observed with a microscope. Then, the sample was heated at 150 ° C. for 168 hours, and the wettability was evaluated by a dip method. The occurrence of whiskers after being left in an environment at a temperature of 85 ° C. and a humidity of 85% for 336 hours was observed with a microscope. The results are as shown in Table 1.

【００３９】[0039]

【表１】 [Table 1]

【００４０】表１に示すとおり、曲げ半径０．１５ｍｍ
のときは上層（表面近傍）のビスマス含有率２．３％の
めっき膜厚が０．５μｍとき（試料Ｎｏ．１）は、クラ
ックの発生はないがウィスカが発生（×印で表示）し、
また、下層（リード基材近傍）のビスマス含有率０．７
％のめっき膜厚が１μｍ以下のとき（試料Ｎｏ．５〜
６）は、ウィスカの発生はないがクラック発生（×印で
表示）による濡れ性の低下（×印で表示）がみられた。As shown in Table 1, the bending radius is 0.15 mm
In the case of (2), when the plating film thickness of the upper layer (near the surface) with a bismuth content of 2.3% is 0.5 μm (sample No. 1), no cracks are generated but whiskers are generated (indicated by x)
Further, the bismuth content of the lower layer (near the lead substrate) is 0.7%.
% When the plating film thickness is 1 μm or less (Sample Nos. 5 to 5).
In No. 6), no whisker was generated, but a decrease in wettability (indicated by x) due to the occurrence of cracks (indicated by x) was observed.

【００４１】従って、クラック及びウィスカの少なくと
も一方の発生を防止するには上層のビスマス含有率２．
３％のめっき膜厚は１μｍ以上あればよく、下層のビス
マス含有率０．７％のめっき膜厚は２μｍ以上あればよ
い。Therefore, in order to prevent the generation of at least one of cracks and whiskers, the bismuth content of the upper layer should be less than 2.
The plating film thickness of 3% may be 1 μm or more, and the plating film thickness of the lower layer having a bismuth content of 0.7% may be 2 μm or more.

【００４２】曲げ半径０．２５ｍｍのときは、下層のビ
スマス含有率０．７％のめっき膜厚が１μｍのときクラ
ックの発生は有るものの濡れ性は良好であることから、
めっき膜厚は上層が１μｍ以上、下層が１μｍ以上であ
る。When the bending radius is 0.25 mm, when the plating thickness of the lower layer is 0.7 μm with a bismuth content of 0.7% and the thickness is 1 μm, cracks occur but the wettability is good.
The plating thickness is 1 μm or more for the upper layer and 1 μm or more for the lower layer.

【００４３】また、更に好ましくクラックもウィスカも
発生させないためには、試料Ｎｏ．２〜４にみられるよ
うに、上層が１〜３μｍ、下層が２〜４μｍであった。In order to prevent the generation of cracks and whiskers, it is more preferable that the sample No. As can be seen in 2-4, the upper layer was 1-3 μm and the lower layer was 2-4 μm.

【００４４】〈実施例２〉実施例１と同様に、４２アロ
イを素材とするテストサンプルに次のようにしてめっき
を行い、評価した。めっき開始時の電流密度を２０Ａ／
ｄｍ2に設定してビスマス含有率０．７ｗｔ％の下層
（リード基材近傍）めっき膜を形成し、ついで電流密度
を１２Ａ／ｄｍ2に設定してビスマス含有率１．２ｗｔ
％の第１中間層を形成し、さらに電流密度を７Ａ／ｄｍ
2に設定してビスマス含有率１．８ｗｔ％の第２中間層
を形成した。その後、電流密度を５Ａ／ｄｍ2に下げて
ビスマス含有率２．３ｗｔ％の上層（表面近傍）めっき
膜を形成した。めっき膜厚は第１及び第２中間層をそれ
ぞれ５μｍとし、上層と下層を合わせて５μｍとし、全
体の膜厚を１５μｍとなるよう表２に示す組合せとし
た。Example 2 In the same manner as in Example 1, a test sample using 42 alloy as a raw material was plated and evaluated as follows. The current density at the start of plating is 20 A /
dm 2 , a lower plating film (in the vicinity of the lead substrate) of a bismuth content of 0.7 wt% was formed, and the current density was set to 12 A / dm 2 to obtain a bismuth content of 1.2 wt%.
% Of the first intermediate layer, and the current density is further increased to 7 A / dm.
Set 2 to form a second intermediate layer of bismuth rate 1.8 wt% to. Thereafter, the current density was reduced to 5 A / dm 2 to form an upper (near the surface) plating film having a bismuth content of 2.3 wt%. The plating film thickness was set to 5 μm for each of the first and second intermediate layers, and the total thickness of the upper layer and the lower layer was set to 5 μm.

【００４５】[0045]

【表２】 [Table 2]

【００４６】表２に示すとおり曲げ半径０．１５ｍｍの
ときは上層のめっき膜厚０．５μｍとき（試料Ｎｏ．
１）は、クラックの発生はないがウィスカが発生（×印
で表示）し、また、下層めっき膜厚１μｍ以下（試料Ｎ
ｏ．５〜６）では、ウィスカの発生はないがクラック発
生（×印で表示）による濡れ性の低下（×印で表示）が
みられた。As shown in Table 2, when the bending radius is 0.15 mm, the plating thickness of the upper layer is 0.5 μm (sample No.
In 1), no cracks were generated, but whiskers were generated (indicated by crosses), and the lower plating film thickness was 1 μm or less (sample N
o. In Nos. 5 and 6), no whisker was generated, but a decrease in wettability (indicated by x) due to cracks (indicated by x) was observed.

【００４７】従って、クラック及びウィスカの少なくと
も一方の発生を防止するには、この場合も上層のビスマ
ス含有率０．７％のめっき膜は１μｍ以上あればよく、
下層のビスマス含有率２．３％のめっき膜は２μｍあれ
ばよい。曲げ半径０．２５ｍｍのときは、上層のめっき
膜は４μｍのときクラックの発生は有るものの濡れ性は
良好であることから、好ましいめっき膜厚は上層が１μ
ｍ以上、下層が１μｍ以上である。本実施例では中間層
を２層としたが、１層でも２層以上でも差し支えはな
い。また、更に好ましくクラックもウィスカも発生させ
ないためには、試料Ｎｏ．２〜４にみられるように、上
層が１〜３μｍ、下層が２〜４μｍであった。Therefore, in order to prevent the generation of at least one of cracks and whiskers, it is sufficient that the upper plating film having a bismuth content of 0.7% is 1 μm or more.
The lower plating film having a bismuth content of 2.3% may have a thickness of 2 μm. When the bending radius is 0.25 mm, when the upper plating film is 4 μm, although cracks are generated but the wettability is good, the preferable plating film thickness is 1 μm.
m or more, and the lower layer is 1 μm or more. In this embodiment, the number of the intermediate layers is two. However, the number of the intermediate layers may be one or two or more. In order to prevent cracks and whiskers from occurring, it is more preferable that the sample No. As can be seen in 2-4, the upper layer was 1-3 μm and the lower layer was 2-4 μm.

【００４８】〈実施例３〉実施例１と同様に、４２アロ
イを素材とするテストサンプルに次のようにしてめっき
を行い、評価した。めっき開始時の電流密度を２０Ａ／
ｄｍ2に設定してビスマス含有率０．７ｗｔ％の下層
（リード近傍）めっき膜を形成し、ついで電流密度を５
Ａ／ｄｍ2に下げてビスマス含有率２．３ｗｔ％の上層
（表面近傍）めっき膜を形成した。ここでは中間層は設
けていない。めっき膜厚は上層と下層を合わせて１０μ
ｍとなるよう表３に示す組合せとした。Example 3 In the same manner as in Example 1, a test sample using 42 alloy as a raw material was plated and evaluated as follows. The current density at the start of plating is 20 A /
dm 2 to form a lower layer (near the lead) plating film with a bismuth content of 0.7 wt%, and then set the current density to 5%.
A / dm 2 was reduced to form an upper layer (near the surface) plating film having a bismuth content of 2.3 wt%. Here, no intermediate layer is provided. The plating thickness is 10μ for the upper and lower layers.
The combinations shown in Table 3 were used to obtain m.

【００４９】[0049]

【表３】 [Table 3]

【００５０】表３に示すとおり曲げ半径０．１５ｍｍの
とき上層のめっき膜厚０．５μｍのとき（試料Ｎｏ．
１）は、クラックの発生はないがウィスカが発生し、ま
た、下層めっき膜厚１μｍ以下（試料Ｎｏ．５〜６）で
は、ウィスカの発生はないがクラック発生（×印で表
示）による濡れ性の低下（×印で表示）がみられた。従
って、クラック及びウィスカの少なくとも一方の発生を
防止するには、この場合も上層のビスマス含有率０．７
％のめっき膜は１μｍ以上あればよく、下層のビスマス
含有率２．３％のめっき膜は２μｍあればよい。曲げ半
径０．２５ｍｍのときは、上層のめっき膜は４μｍのと
きクラックの発生は有るものの濡れ性は良好であること
から、好ましいめっき膜厚は上層が１μｍ以上、下層が
１μｍ以上である。また、更に好ましくクラックもウィ
スカも発生させないためには、試料Ｎｏ．２〜４にみら
れるように、上層が１〜８μｍ、下層が２〜９μｍであ
った。As shown in Table 3, when the bending radius was 0.15 mm and the plating thickness of the upper layer was 0.5 μm (Sample No.
In 1), no cracks were generated but whiskers were generated, and when the lower plating film thickness was 1 μm or less (samples Nos. 5 to 6), no whisker was generated but wettability due to cracks (indicated by x) (Indicated by x) was observed. Therefore, in order to prevent the generation of at least one of cracks and whiskers, the bismuth content of the upper layer is also set to 0.7 in this case.
% Of the plating film may be 1 μm or more, and the plating film of the lower layer having a bismuth content of 2.3% may be 2 μm. When the bending radius is 0.25 mm, the upper plating film is 4 μm, although cracks are generated, but the wettability is good. Therefore, the preferred plating film thickness is 1 μm or more for the upper layer and 1 μm or more for the lower layer. In order to prevent cracks and whiskers from occurring, it is more preferable that the sample No. As seen in FIGS. 2 to 4, the upper layer was 1 to 8 μm, and the lower layer was 2 to 9 μm.

【００５１】〈実施例４〉実施例１と同様に、４２アロ
イを素材とするテストサンプルに次のようにしてめっき
を行い、評価した。めっき開始時の電流密度を２０Ａ／
ｄｍ2に設定してビスマス含有率０．５％の下層（リー
ド基材近傍）めっき膜を形成し、ついで電流密度を連続
的に減少してビスマス含有率０．５ｗｔ％から、表４の
上層めっき膜のビスマス含有率に対応するように０．８
〜４ｗｔ％へ連続的に変化する中間層めっき膜を形成
し、その後、中間層末期の電流密度を維持しながら試料
Ｎｏ．１〜５に表示したビスマス含有率の異なる上層
（表面近傍）めっき膜を形成した。めっき膜厚は中間層
を５μｍとし、上層を２μｍ、下層を３μｍとした。<Example 4> In the same manner as in Example 1, a test sample using 42 alloy as a material was plated and evaluated as follows. The current density at the start of plating is 20 A /
dm 2 , a lower layer (near the lead base material) plating film of 0.5% bismuth content was formed, and then the current density was continuously reduced to reduce the bismuth content from 0.5 wt% to the upper layer of Table 4. 0.8 to correspond to the bismuth content of the plating film
The intermediate layer plating film continuously changing to about 4 wt% is formed, and then, while maintaining the current density at the final stage of the intermediate layer, the sample No. Upper-layer (near the surface) plating films having different bismuth contents indicated by 1 to 5 were formed. The plating thickness was 5 μm for the intermediate layer, 2 μm for the upper layer, and 3 μm for the lower layer.

【００５２】[0052]

【表４】 [Table 4]

【００５３】表４に示すとおり上層めっき膜のビスマス
含有率０．８％（試料Ｎｏ．１）では、クラックの発生
はないがウィスカが発生した（×印で表示）。また、ビ
スマス含有率４％においてもクラックの発生による濡れ
性の低下はみられなかった。従って、上層めっき膜のビ
スマス含有率は１ｗｔ％以上であればよい。曲げ半径
０．２５ｍｍのときも同様の結果であった。なお、本実
施例ではめっき膜厚が下層３μｍ、上層２μｍの例を示
したが、上記の実施例１〜３で示しためっき膜厚範囲で
も同様の結果が得られた。As shown in Table 4, when the bismuth content of the upper plating film was 0.8% (sample No. 1), no cracks were generated, but whiskers were generated (indicated by x). Also, even at a bismuth content of 4%, no decrease in wettability due to cracks was observed. Therefore, the bismuth content of the upper plating film may be 1 wt% or more. Similar results were obtained when the bending radius was 0.25 mm. In this example, the example in which the plating film thickness was 3 μm for the lower layer and 2 μm for the upper layer was shown, but similar results were obtained in the plating film thickness ranges shown in Examples 1 to 3 above.

【００５４】〈実施例５〉実施例１と同様に、４２アロ
イを素材とするテストサンプルに次のようにしてめっき
を行い、評価した。めっき開始時の電流密度を変えてビ
スマス含有率の異なる下層（リード基材近傍）めっき膜
を形成し、ついで電流密度を連続的に減少してビスマス
含有率０．５〜１．５ｗｔ％から２．３ｗｔ％に連続的
に変化する中間層めっき膜を形成し、その後、電流密度
を５Ａ／ｄｍ2に設定してビスマス含有率２．３％の上
層（表面近傍）めっき膜を形成した。めっき膜厚は中間
層を５μｍとし、上層を２μｍ、下層を３μｍとした。
その結果は表５に示すとおりである。<Example 5> In the same manner as in Example 1, a test sample using 42 alloy as a material was plated and evaluated as follows. By changing the current density at the start of plating, a lower layer (near the lead base material) plating film having a different bismuth content is formed, and then the current density is continuously reduced to reduce the bismuth content from 0.5 to 1.5 wt% to 2%. An intermediate layer plating film continuously changing to 0.3 wt% was formed, and thereafter, an upper layer (near the surface) plating film with a bismuth content of 2.3% was formed at a current density of 5 A / dm 2 . The plating thickness was 5 μm for the intermediate layer, 2 μm for the upper layer, and 3 μm for the lower layer.
The results are as shown in Table 5.

【００５５】[0055]

【表５】 [Table 5]

【００５６】表５に示すとおり曲げ半径０．１５ｍｍの
とき、下層めっき膜のビスマス含有率１．２ｗｔ％以上
でクラックの発生による濡れ性の低下がみられた。従っ
て、下層めっき膜のビスマス含有率は１ｗｔ％以下であ
ればよい。曲げ半径０．２５ｍｍのときは、ビスマス含
有率１．２％まで濡れ性は良好であることから、ビスマ
ス含有率は１．２ｗｔ％以下であればよい。なお、本実
施例ではめっき膜厚が下層３μｍ、上層２μｍの例を示
したが、上記の実施例１〜４で示した好ましいめっき膜
厚範囲でも同様の結果が得られた。As shown in Table 5, when the bending radius was 0.15 mm, when the bismuth content of the lower plating film was 1.2 wt% or more, a decrease in wettability due to cracks was observed. Therefore, the bismuth content of the lower plating film may be 1 wt% or less. When the bending radius is 0.25 mm, since the wettability is good up to a bismuth content of 1.2%, the bismuth content may be 1.2 wt% or less. In this embodiment, the example in which the plating film thickness is 3 μm for the lower layer and 2 μm for the upper layer is shown, but similar results were obtained in the preferred plating film thickness ranges shown in the above Examples 1 to 4.

【００５７】〈実施例６〉実施例１と同様に、４２アロ
イを素材とするテストサンプルに次のようにしてめっき
を行い、評価した。めっき電流にパルス電流を使用し、
通電時間を０．９秒、休止時間を０．１秒とし、電流密
度を２０Ａ／ｄｍ2に設定してビスマス含有率０．８ｗ
ｔ％の下層（リード基材近傍）めっき膜を形成した。つ
いで通電時間と休止時間の比を連続的に変化させて、ビ
スマス含有率が０．８ｗｔ％から１．７ｗｔ％に連続的
に変化する中間層めっき膜を形成した。その後、通電時
間を０．２秒、休止時間を０．８秒としてビスマス含有
率１．７ｗｔ％の上層（表面近傍）めっき膜を形成し
た。電流密度は２０Ａ／ｄｍ2である。めっき膜厚は中
間層を５μｍとし、上層と下層を合わせて５μｍとなる
よう表６に示す組合せとした。<Example 6> In the same manner as in Example 1, a test sample using 42 alloy as a material was plated and evaluated as follows. Using pulse current for plating current,
The energizing time was 0.9 seconds, the rest time was 0.1 seconds, the current density was set to 20 A / dm 2 , and the bismuth content was 0.8 w.
A plating film of a lower layer (near the lead base material) of t% was formed. Next, the ratio of the energizing time to the pause time was continuously changed to form an intermediate plating film in which the bismuth content continuously changed from 0.8 wt% to 1.7 wt%. Thereafter, an upper layer (near the surface) plating film having a bismuth content of 1.7 wt% was formed with a conduction time of 0.2 seconds and a pause time of 0.8 seconds. The current density is 20 A / dm 2 . The plating film thickness was set to 5 μm for the intermediate layer, and the combinations shown in Table 6 were set so that the total thickness of the upper layer and the lower layer was 5 μm.

【００５８】[0058]

【表６】 [Table 6]

【００５９】表６に示すとおり曲げ半径０．１５ｍｍの
とき上層のめっき膜厚が０．５μｍのとき（試料Ｎｏ．
１）は、クラックの発生はないがウィスカが発生した
（×印で表示）。また、下層のめっき膜厚が１μｍ以下
（試料Ｎｏ．５〜６）では、ウィスカの発生はないがク
ラック発生（×印で表示）による濡れ性の低下（×印で
表示）がみられた。従って、クラック及びウィスカの少
なくとも一方の発生を防止するには、上層のめっき膜厚
は１μｍ以上あればよく、下層のめっき膜厚は２μｍ以
上あればよい。曲げ半径０．２５ｍｍのときは、下層の
めっき膜厚が１μｍのときクラックの発生は有るものの
濡れ性は良好であることから、めっき膜厚は上層が１μ
ｍ以上、下層が１μｍ以上あればよい。また、更に好ま
しくクラックもウィスカも発生させないためには、試料
Ｎｏ．２〜４にみられるように、上層が１〜３μｍ、下
層が２〜４μｍであった。As shown in Table 6, when the bending radius was 0.15 mm and the plating thickness of the upper layer was 0.5 μm (Sample No.
In 1), no crack was generated but whiskers were generated (indicated by crosses). When the thickness of the lower plating layer was 1 μm or less (samples Nos. 5 to 6), no whisker was generated, but a decrease in wettability (denoted by x) due to cracks (denoted by x) was observed. Therefore, in order to prevent the occurrence of at least one of cracks and whiskers, the upper plating film thickness needs to be 1 μm or more, and the lower plating film thickness needs to be 2 μm or more. When the bending radius is 0.25 mm, when the plating thickness of the lower layer is 1 μm, although cracks are generated but the wettability is good, the plating thickness of the upper layer is 1 μm.
m or more, and the lower layer may be 1 μm or more. In order to prevent cracks and whiskers from occurring, it is more preferable that the sample No. As can be seen in 2-4, the upper layer was 1-3 μm and the lower layer was 2-4 μm.

【００６０】〈実施例７〉実施例１と同様に、４２アロ
イを素材とするテストサンプルに次のようにしてめっき
を行い、評価した。めっき液にはビスマス濃度０．５ｇ
／ｌのめっき液を用い、めっき電流にパルス電流を使用
した。通電時間を０．９秒、休止時間を０．１秒とし、
電流密度を２０Ａ／ｄｍ2に設定してビスマス含有率
０．６ｗｔ％の下層（リード基材近傍）めっき膜を形成
した。Example 7 In the same manner as in Example 1, a test sample using 42 alloy as a raw material was plated and evaluated as follows. Bismuth concentration 0.5g in plating solution
/ 1 plating solution, and a pulse current was used as a plating current. The energization time is 0.9 seconds, the pause time is 0.1 seconds,
The current density was set to 20 A / dm 2 to form a lower plating film (in the vicinity of the lead substrate) of a bismuth content of 0.6 wt%.

【００６１】ついで電流密度を２０Ａ／ｄｍ2から５Ａ
／ｄｍ2に連続的に変化させると共に、通電時間と休止
時間の比を連続的に変化させて、ビスマス含有率が０．
６ｗｔ％から２．８ｗｔ％に連続的に変化する中間層め
っき膜を形成した。Then, the current density was increased from 20 A / dm 2 to 5 A.
/ Dm 2 and the ratio between the energizing time and the rest time is continuously changed so that the bismuth content is 0.1%.
An intermediate plating film continuously changing from 6 wt% to 2.8 wt% was formed.

【００６２】その後、通電時間を０．２秒、休止時間を
０．８秒とし、電流密度を５Ａ／ｄｍ2に下げ、ビスマ
ス含有率２．８ｗｔ％の上層（表面近傍）めっき膜を形
成した。めっき膜厚は中間層が５μｍ、上層と下層を合
わせて５μｍとなるよう表７に示す組合せとした。Thereafter, the energizing time was set to 0.2 seconds, the rest time was set to 0.8 seconds, the current density was reduced to 5 A / dm 2, and an upper (near the surface) plating film having a bismuth content of 2.8 wt% was formed. . The plating film thickness was set as shown in Table 7 so that the thickness of the intermediate layer was 5 μm, and the total thickness of the upper layer and the lower layer was 5 μm.

【００６３】[0063]

【表７】 [Table 7]

【００６４】表７に示すとおり曲げ半径０．１５ｍｍの
とき上層のめっき膜厚が０．５μｍとき（試料Ｎｏ．
１）は、クラックは発生しないがウィスカが発生し、ま
た、下層のめっき膜厚が１μｍ以下のとき（試料Ｎｏ．
５〜６）は、ウィスカは発生しないがクラック発生によ
る濡れ性の低下がみられた。従って、クラック及びウィ
スカの少なくとも一方の発生を防止するには、上層のめ
っき膜厚は１μｍ以上あればよく、下層のめっき膜厚は
２μｍ以上あればよい。As shown in Table 7, when the bending radius is 0.15 mm, the plating thickness of the upper layer is 0.5 μm (sample No.
In No. 1), when cracks did not occur but whiskers did occur, and when the thickness of the underlying plating film was 1 μm or less (Sample No. 1).
In Nos. 5 and 6, no whiskers were generated, but a decrease in wettability due to cracks was observed. Therefore, in order to prevent the occurrence of at least one of cracks and whiskers, the upper plating film thickness needs to be 1 μm or more, and the lower plating film thickness needs to be 2 μm or more.

【００６５】曲げ半径０．２５ｍｍのときは、下層のめ
っき膜厚が１μｍのときクラックの発生は有るものの濡
れ性は良好であることから、めっき膜厚は上層が１μｍ
以上、下層が１μｍ以上あればよい。また、更に好まし
くクラックもウィスカも発生させないためには、試料Ｎ
ｏ．２〜４にみられるように、上層が１〜３μｍ、下層
が２〜４μｍであった。When the bending radius is 0.25 mm, cracks are generated when the plating thickness of the lower layer is 1 μm, but the wettability is good, so that the plating thickness of the upper layer is 1 μm.
As described above, the lower layer only needs to be 1 μm or more. In order to further preferably prevent cracks and whiskers from occurring, the sample N
o. As can be seen in 2-4, the upper layer was 1-3 μm and the lower layer was 2-4 μm.

【００６６】実施例１〜７で示しためっき膜厚範囲では
いずれも耐食性も良好であった。さらに、ここでは４２
アロイリードの例について示したが、銅めっきをした４
２アロイリード、銅合金リードについても同様の結果が
得られた。In each of the plating film thickness ranges shown in Examples 1 to 7, the corrosion resistance was good. Further, here, 42
The example of alloy lead is shown, but copper plated 4
Similar results were obtained with 2 alloy leads and copper alloy leads.

【００６７】実施例１〜７では上層、下層のめっき膜と
もにビスマス含有率が一定の場合を記したが、上層のビ
スマス含有率は１％以上の範囲で、また、下層のビスマ
ス含有率は１ｗｔ％以下の範囲で変動させても差し支え
ない。本発明において重要なことはビスマスのような合
金成分含有率が、下層よりも上層の方で大きくなってい
ることである。In Examples 1 to 7, the case where the bismuth content of the upper and lower plating films is constant is described. However, the bismuth content of the upper layer is 1% or more, and the bismuth content of the lower layer is 1 wt. % May be varied. What is important in the present invention is that the content of an alloy component such as bismuth is higher in the upper layer than in the lower layer.

【００６８】また、上記実施例ではスズ−ビスマス合金
めっき膜を代表例として示したが、その他、合金成分が
銀、亜鉛、インジウム及びアンチモン等のスズ合金めっ
き膜についても同様の結果が得られた。In the above embodiment, a tin-bismuth alloy plating film is shown as a representative example. However, similar results were obtained for tin alloy plating films containing silver, zinc, indium, and antimony as alloy components. .

【００６９】[0069]

【発明の効果】以上詳述したように、本発明により所期
の目的を達成することができた。すなわち、半導体装置
の外部リードへのスズ合金めっき膜の形成において、リ
ード基材近傍（下層）のビスマスに代表される合金成分
含有率の小さいめっき膜および表面近傍（上層）のビス
マス含有率の大きいめっき膜およびそれらの間のビスマ
ス含有率を連続的または断続的に有する中間層めっき膜
とからなる構造とすることにより、リードの成型時の折
り曲げによるクラックの発生に伴う濡れ性の低下がな
く、かつ、ウィスカの発生もなく、耐食性など信頼性に
優れた半導体装置を製造することが可能となった。As described in detail above, the intended object has been achieved by the present invention. That is, in forming a tin alloy plating film on an external lead of a semiconductor device, a plating film having a small alloy component content represented by bismuth near the lead substrate (lower layer) and a large bismuth content near the surface (upper layer) are large. By having a structure consisting of a plating film and an intermediate plating film having a bismuth content between them continuously or intermittently, there is no decrease in wettability due to the occurrence of cracks due to bending during molding of the lead, In addition, a semiconductor device having excellent reliability such as corrosion resistance without whiskers can be manufactured.

【００７０】さらに、本発明によれば同一のめっき液中
で上記の下層、中間層、上層からなる３層のめっき全て
を行うことが可能であり、めっき槽、めっき液の節減が
可能となり、めっきコストの低減が図れる。Further, according to the present invention, it is possible to perform all of the above three layers of the lower layer, the intermediate layer, and the upper layer in the same plating solution, thereby saving the plating bath and the plating solution. Plating cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係る半導体装置の一実施例の形態を示
す断面図。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

【図２】本発明に係るリードの一実施例の形態を示す断
面図。FIG. 2 is a sectional view showing an embodiment of a lead according to the present invention.

【図３】本発明に係るめっき膜のビスマス含有率と電流
密度の関係を示す図。FIG. 3 is a view showing the relationship between the bismuth content of the plating film according to the present invention and the current density.

【図４】めっき電流としてのパルス波形の一実施例を示
す図。FIG. 4 is a diagram showing an example of a pulse waveform as a plating current.

【図５】パルス電流を用いたとき形成されるめっき膜構
成の一実施例を示す図。FIG. 5 is a diagram showing one embodiment of a plating film configuration formed when a pulse current is used.

【符号の説明】[Explanation of symbols]

1…半導体素子、 ２…リードフレーム、 ３…ボンデイングワイヤ、 ４…モールド樹脂、 ５…モールド樹脂の外側に露出したリード（外部リー
ド）、 ６…リード基材、 ７…ビスマス含有率の小さいめっき膜（下層）、 ８…ビスマス含有率の大きいめっき膜（上層）、 ９…中間層、 １０…パルスの通電時間に析出したスズ―ビスマス合金
めっき膜、 １１…パルスの休止時間に置換析出したビスマス膜。1 ... Semiconductor element, 2 ... Lead frame, 3 ... Bonding wire, 4 ... Mold resin, 5 ... Lead (external lead) exposed outside the mold resin, 6 ... Lead base material, 7 ... Plating film with small bismuth content (Lower layer), 8: plating film with high bismuth content (upper layer), 9: Intermediate layer, 10: Tin-bismuth alloy plating film deposited during pulse energization time, 11: Bismuth film deposited by substitution during pulse pause time .

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】リードに電気的に接続された半導体素子が
樹脂封止され、外部に露出したリード表面にスズ合金め
っき膜が形成されかつ曲げ成形された半導体装置におい
て、前記スズ合金めっき膜が、めっき膜厚方向に合金成
分の含有率が増加するように濃度勾配を有していること
を特徴とする半導体装置。1. A semiconductor device in which a semiconductor element electrically connected to a lead is resin-sealed, and a tin alloy plating film is formed on a surface of the lead exposed to the outside and is bent and formed. A semiconductor device having a concentration gradient such that the content of an alloy component increases in a plating film thickness direction. 【請求項２】前記スズ合金めっき膜は、めっき膜厚方向
に合金成分の含有率が連続的に増加するように濃度勾配
を有していることを特徴とする請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the tin alloy plating film has a concentration gradient such that the content of the alloy component continuously increases in the plating film thickness direction. 【請求項３】前記スズ合金めっき膜は、めっき膜厚方向
に合金成分の含有率が段階的に増加するように濃度勾配
を有していることを特徴とする請求項１記載の半導体装
置。3. The semiconductor device according to claim 1, wherein the tin alloy plating film has a concentration gradient such that the content of the alloy component increases stepwise in the plating film thickness direction. 【請求項４】リード表面に形成したスズ合金めっき膜
は、合金成分としてビスマス、銀、亜鉛、インジウム及
びアンチモンの少なくとも１種を含み、かつ前記合金成
分の含有率が１ｗｔ％以下の下層の上に、含有率が１ｗ
ｔ％以上の上層とを有していることを特徴とする請求項
１乃至３のいずれか一つに記載の半導体装置。4. A tin alloy plating film formed on a lead surface contains at least one of bismuth, silver, zinc, indium and antimony as an alloy component, and the content of the alloy component is 1 wt% or less. And the content rate is 1w
4. The semiconductor device according to claim 1, wherein the semiconductor device has an upper layer of at least t%. 【請求項５】前記スズ合金めっき膜の合金含有率が１ｗ
ｔ％以上の上層の膜厚が1μｍ以上であり、合金含有率
が１ｗｔ％未満の下層の膜厚が２μｍ以上であることを
特徴とする請求項４記載の半導体装置。5. The tin alloy plating film has an alloy content of 1 watt.
5. The semiconductor device according to claim 4, wherein the thickness of the upper layer of t% or more is 1 μm or more, and the thickness of the lower layer having an alloy content of less than 1 wt% is 2 μm or more. 【請求項６】前記リード表面には、スズ合金めっき膜の
下地として１〜１０μｍ膜厚の銅めっきが施されている
ことを特徴とする請求項１乃至５のいずれか一つに記載
の半導体装置。6. The semiconductor according to claim 1, wherein the lead surface is plated with copper having a thickness of 1 to 10 μm as a base of a tin alloy plating film. apparatus. 【請求項７】リードフレームに半導体素子を電気的に接
続し、樹脂封止した半導体装置の外部リードにスズ合金
めっき膜を形成し、リードをリードフレームから切断し
所定の形状に曲げて成形するパッケージ工程を有する半
導体装置の製造方法において、前記外部リードにスズ合
金めっき膜を形成するに際し、めっき膜の厚さ方向に合
金成分含有率が増加するようにスズ合金めっき膜中に合
金成分の濃度勾配を形成する工程を有していることを特
徴とする半導体装置の製造方法。7. A semiconductor element is electrically connected to a lead frame, a tin alloy plating film is formed on an external lead of a resin-sealed semiconductor device, and the lead is cut from the lead frame and bent into a predetermined shape. In the method of manufacturing a semiconductor device having a package step, when forming the tin alloy plating film on the external lead, the concentration of the alloy component in the tin alloy plating film is increased so that the alloy component content increases in the thickness direction of the plating film. A method for manufacturing a semiconductor device, comprising a step of forming a gradient. 【請求項８】リードフレームに半導体素子を電気的に接
続し、樹脂封止した半導体装置の外部リードにスズ合金
めっき膜を形成し、リードをリードフレームから切断し
所定の形状に曲げて成形するパッケージング工程を有す
る半導体装置の製造方法において、前記外部リードにス
ズ合金めっき膜を形成するに際し、めっき膜の厚さ方向
に合金成分含有率が連続的に増加するようにスズ合金め
っき膜中に合金成分の濃度勾配を形成する工程を有して
いることを特徴とする半導体装置の製造方法。8. A semiconductor device is electrically connected to a lead frame, a tin alloy plating film is formed on an external lead of the resin-sealed semiconductor device, and the lead is cut from the lead frame and bent into a predetermined shape. In the method for manufacturing a semiconductor device having a packaging step, when forming a tin alloy plating film on the external lead, the tin alloy plating film is so formed that the alloy component content continuously increases in the thickness direction of the plating film. A method for manufacturing a semiconductor device, comprising a step of forming a concentration gradient of an alloy component. 【請求項９】前記スズ合金めっき膜を形成する工程を、
電気めっき工程で構成し前記合金成分含有率を電流密度
に基づいて変化せしめ、めっき初期は所定の高電流密度
で目的とする低い合金成分含有率とし、次いで膜厚の増
加と共に順次電流密度を低下させて高い合金成分含有率
とする工程としたことを特徴とする請求項８記載の半導
体装置の製造方法。9. The step of forming the tin alloy plating film,
In the electroplating process, the content of the alloy component is changed based on the current density.In the initial plating, the desired low alloy component content is obtained at a predetermined high current density, and then the current density is sequentially reduced as the film thickness increases. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the step of increasing the alloy component content is performed. 【請求項１０】前記スズ合金めっき膜を形成する工程
を、電気めっき工程で構成し、めっき電流波形にパルス
波形を用いてパルスの通電時間ｔにおいて所定の合金成
分含有率のスズ合金めっき膜を析出させ、次いでパルス
休止時間ｓでスズを含まない合金成分のみを析出させ、
これらパルスの通電時間ｔと休止時間ｓとを周期的に繰
り返すことにより多層構造のめっき膜を形成する工程と
したことを特徴とする請求項８記載の半導体装置の製造
方法。10. The step of forming the tin alloy plating film comprises an electroplating step, and using a pulse waveform as a plating current waveform, forming a tin alloy plating film having a predetermined alloy component content at a pulse conduction time t. Precipitation, and then, after a pulse pause time s, only tin-free alloy components are precipitated,
9. The method for manufacturing a semiconductor device according to claim 8, wherein a step of forming a plating film having a multilayer structure by periodically repeating the energizing time t and the pause time s of the pulse is provided. 【請求項１１】前記スズ合金めっき膜を形成する工程
を、前記合金成分含有率を電流密度に基づいて変化せし
める第１の工程と、めっき電流波形にパルス波形を用い
てパルスの通電時間ｔにおいて所定の合金成分含有率の
スズ合金めっき膜を析出させ、次いでパルス休止時間ｓ
でスズを含まない合金成分のみを析出させる第２の工程
とからなる電気めっき工程で構成し、めっき初期には電
流密度を大きく、かつパルスの通電時間ｔを短くして目
的とする低い合金成分含有率とし、めっき終末期には電
流密度を小さく、かつパルスの通電時間ｔを長くするこ
とにより高い合金成分含有率とする形成工程としたこと
を特徴とする請求項８記載の半導体装置の製造方法。11. A method for forming a tin alloy plating film, comprising: a first step of changing the alloy component content based on a current density; and a pulse energizing time t using a pulse waveform as a plating current waveform. A tin alloy plating film having a predetermined alloy component content is deposited, and then a pulse pause time s
And a second step of precipitating only an alloy component not containing tin by using an electroplating process. In the initial stage of plating, the current density is high and the pulse energization time t is shortened to obtain the desired low alloy component. 9. The manufacturing method of a semiconductor device according to claim 8, wherein in the final stage of plating, the current density is low and the pulse energization time t is lengthened to increase the alloy component content. Method. 【請求項１２】請求項１乃至４のいずれか一つに記載さ
れた半導体装置の外部リードを所定の配線基板上の電極
にはんだ接続したことを特徴とする半導体装置の実装構
造体。12. A mounting structure for a semiconductor device, wherein external leads of the semiconductor device according to claim 1 are connected to electrodes on a predetermined wiring board by soldering.
JP10347141A 1998-12-07 1998-12-07 Semiconductor device and its manufacture Pending JP2000174191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10347141A JP2000174191A (en) 1998-12-07 1998-12-07 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JP2000174191A true JP2000174191A (en) 2000-06-23

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ID=18388196

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JP2007154260A (en) * 2005-12-05 2007-06-21 Sumitomo Metal Mining Co Ltd Method of depositing lead-free plating film
US7235309B2 (en) 2002-12-16 2007-06-26 Nec Electronics Corporation Electronic device having external terminals with lead-free metal thin film formed on the surface thereof
WO2008082004A1 (en) * 2007-01-04 2008-07-10 Toyota Jidosha Kabushiki Kaisha Plating member and process for producing the plating member
US7501694B2 (en) 2004-09-28 2009-03-10 Fujitsu Microelectronics Limited Semiconductor device using multi-layer unleaded metal plating, and method of manufacturing the same
JP2010245217A (en) * 2009-04-03 2010-10-28 Kenichi Fuse Method of mounting semiconductor ic
KR100998036B1 (en) 2003-06-27 2010-12-03 삼성테크윈 주식회사 Pre-plated lead frame for semiconductor package and pre-plating method thereof
CN101908515A (en) * 2009-06-08 2010-12-08 瑞萨电子株式会社 Semiconductor device and preparation method thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235309B2 (en) 2002-12-16 2007-06-26 Nec Electronics Corporation Electronic device having external terminals with lead-free metal thin film formed on the surface thereof
KR100998036B1 (en) 2003-06-27 2010-12-03 삼성테크윈 주식회사 Pre-plated lead frame for semiconductor package and pre-plating method thereof
US7501694B2 (en) 2004-09-28 2009-03-10 Fujitsu Microelectronics Limited Semiconductor device using multi-layer unleaded metal plating, and method of manufacturing the same
JP2007154260A (en) * 2005-12-05 2007-06-21 Sumitomo Metal Mining Co Ltd Method of depositing lead-free plating film
JP4654895B2 (en) * 2005-12-05 2011-03-23 住友金属鉱山株式会社 Formation method of lead-free plating film
WO2008082004A1 (en) * 2007-01-04 2008-07-10 Toyota Jidosha Kabushiki Kaisha Plating member and process for producing the plating member
JP2008166645A (en) * 2007-01-04 2008-07-17 Toyota Motor Corp Plating member, and its manufacturing method
US8021761B2 (en) 2007-01-04 2011-09-20 Toyota Jidosha Kabushiki Kaisha Plating member
JP2010245217A (en) * 2009-04-03 2010-10-28 Kenichi Fuse Method of mounting semiconductor ic
CN101908515A (en) * 2009-06-08 2010-12-08 瑞萨电子株式会社 Semiconductor device and preparation method thereof
JP2010283303A (en) * 2009-06-08 2010-12-16 Renesas Electronics Corp Semiconductor device and method of manufacturing the same

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