KR950008697B1 - Tab tape - Google Patents
Tab tape Download PDFInfo
- Publication number
- KR950008697B1 KR950008697B1 KR1019910012686A KR910012686A KR950008697B1 KR 950008697 B1 KR950008697 B1 KR 950008697B1 KR 1019910012686 A KR1019910012686 A KR 1019910012686A KR 910012686 A KR910012686 A KR 910012686A KR 950008697 B1 KR950008697 B1 KR 950008697B1
- Authority
- KR
- South Korea
- Prior art keywords
- tin
- film
- plated film
- plating film
- plating
- Prior art date
Links
- 238000007747 plating Methods 0.000 claims description 49
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 28
- 229910000679 solder Inorganic materials 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 5
- 239000011889 copper foil Substances 0.000 description 15
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 14
- 229910000531 Co alloy Inorganic materials 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 229910052709 silver Inorganic materials 0.000 description 9
- 239000004332 silver Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 7
- 229910052697 platinum Inorganic materials 0.000 description 7
- 229910052703 rhodium Inorganic materials 0.000 description 7
- 239000010948 rhodium Substances 0.000 description 7
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 7
- 229910017052 cobalt Inorganic materials 0.000 description 6
- 239000010941 cobalt Substances 0.000 description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 4
- 229910000990 Ni alloy Inorganic materials 0.000 description 3
- QXZUUHYBWMWJHK-UHFFFAOYSA-N [Co].[Ni] Chemical compound [Co].[Ni] QXZUUHYBWMWJHK-UHFFFAOYSA-N 0.000 description 3
- KVCNTPMIAMJSNS-UHFFFAOYSA-N [Co][Ni][Sn] Chemical compound [Co][Ni][Sn] KVCNTPMIAMJSNS-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 238000005275 alloying Methods 0.000 description 3
- WDHWFGNRFMPTQS-UHFFFAOYSA-N cobalt tin Chemical compound [Co].[Sn] WDHWFGNRFMPTQS-UHFFFAOYSA-N 0.000 description 3
- CLDVQCMGOSGNIW-UHFFFAOYSA-N nickel tin Chemical compound [Ni].[Sn] CLDVQCMGOSGNIW-UHFFFAOYSA-N 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000010970 precious metal Substances 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- GSJBKPNSLRKRNR-UHFFFAOYSA-N $l^{2}-stannanylidenetin Chemical compound [Sn].[Sn] GSJBKPNSLRKRNR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- -1 paradium Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Other Surface Treatments For Metallic Materials (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
내용 없음.No content.
Description
제1도는 TAB 테이프의 단면 설명도.1 is a cross-sectional explanatory diagram of a TAB tape.
제2도 및 제3도는 접속회로 패턴의 단면도.2 and 3 are cross-sectional views of the connection circuit pattern.
본 발명은 TAB (Tape Automated Bonding) 테이프에 관한 것이다.The present invention relates to a Tape Automated Bonding (TAB) tape.
TAB 테이프는 반도체 소자와 외부접속용 리드등의 외부도체회로를 전기적으로 접속하는 것이며 동박을 사용하여 미세한 패턴으로 형성할수 있으므로 와이어를 사용하여 접속하는 것 보다도 다수핀의 접속이 가능하다.TAB tapes are used to electrically connect semiconductor elements and external conductor circuits such as external connection leads, and can be formed in fine patterns using copper foil. Therefore, many pins can be connected than wires.
TAB 테이프의 인너리드와 반도체소자와의 접합은 반도체소자에 형성한 금등의 범프(bump)와의 사이에서 금-주석 공정합금에 의한 경우가 많고 그 때문에 TAB 테이프는 동박으로 형성된 리드패턴위에 주석 도금피막을 형성한 것이 사용된다.The bonding between the inner lead of the TAB tape and the semiconductor element is often performed by a gold-tin process alloy between a bump of gold or the like formed in the semiconductor element. Therefore, the TAB tape is a tin plated film on a lead pattern formed of copper foil. What formed is used.
또 TAB 테이프의 외부접속용 아우터리드와 외부도체회로와의 사이는 통상 주석 도금피막을 이용하여 납땜에 의해서 접합되어 있다.In addition, between an outer connection for an external connection of a TAB tape and an external conductor circuit is usually joined by soldering using a tin plating film.
그러나 상기의 TAB 테이프에는 다움과 같은 문제점이 있다.However, the above TAB tape has a problem such as ness.
즉 반도체소자와 TAB 테이프의 인너리드를 금-주석 공정합금에 의해서 접합할때에는 400℃∼500℃의 고온의 본딩조건이 필요하게 된다. 이 인너리드에 가해지는 열은 바로 TAB 테이프의 아우터리드에 전해져 아우터리드가 가열되고 이 때문에 아우터리드소재의 동이주석도금피막중으로 확산된다는 문제가 생긴다. 동이주석도금피막중으로 확산되면 결과적으로 주석도금을 행하지 않은 것과 같아지고 아우터리드와 외부도체회로와의 납땜성이 저해된다는 문제가 생긴다.That is, when the inner lead of the semiconductor element and the TAB tape are joined by the gold-tin process alloy, high temperature bonding conditions of 400 ° C to 500 ° C are required. The heat applied to this inner lead is immediately transmitted to the outer layer of the TAB tape, and the outer layer heats up, which causes a problem of diffusion into the copper tin-plated coating of the outer material. Diffusion into the copper tin plated film results in a problem that tin plating is not performed as a result and that solderability between the outer and the external conductor circuit is impaired.
또 일시적으로 아우터리드와 외부도체회로와의 접합이 행해져도 원래 동은 주석중으로 확산되기 쉬운 성질을 갖기 때문에 경시적으로 동의주석도금피막중으로의 확산이 생기므로 납땜강도는 점차 열화되어 박리가 생긴다는 본질적인 결함이 있다.In addition, even when the outer conductor and the external conductor circuit are temporarily bonded, the original copper tends to diffuse into the tin, and thus the diffusion into the tin-tin coating over time causes the solder strength to gradually deteriorate and peel off. There is an inherent flaw.
주석도금피막을 두껍게 하면 상기의 문제점은 어느정도 해소시킬 수 있으나 두껍게 하면 반도체소자와 인너리드와의 금-주석공정합금에 의한 접합시에 주석분이 남아 이 여분의 주석분이 유출되어 인너리드간을 단락시킬 우려가 있다. 이 때문에 주석도금피막의 두께는 0.5μm 정도로 극히 얇은 것이 현상이다.Thickening the tin-plated film can solve the above problems to some extent, but thickening the tin remains during joining of the semiconductor element and the inner lead by the gold-tin eutectic alloy, and this excess tin powder leaks out and shorts the inner lead. There is concern. For this reason, the thickness of the tin-plated film is extremely thin, about 0.5 μm.
또 한편 인너리드를 반도체소자에 접합시킬 때에는 본딩툴에 의해서 인너리드를 외측에서 눌러 반도체소자에 압착시키기 때문에 용융된 주석등이 본딩툴에 부착하고 이 때문에 빈번하게 본딩툴의 청소를 해야하고 심한 경우에는 본딩이 불가능하게 된다는 문제점도 있다.On the other hand, when the inner lead is bonded to the semiconductor element, the inner lead is pressed from the outside by the bonding tool and pressed to the semiconductor element, so that molten tin is attached to the bonding tool, and thus, the bonding tool needs to be cleaned frequently. There is also a problem that bonding becomes impossible.
본 발명은 상기의 문제점을 해소하기 위하여 행해진 것으로 그 목적은 동의주석도금 피막중으로의 확산을 방지하여 외부접속용 아우터리드와 외부도체회로와의 납땜성이 양호해지고 또 본딩툴로의 주석등의 부착이 방지될 수 있는 TAB 테이프를 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its purpose is to prevent diffusion into copper tin-plated coatings, thereby improving solderability of the outer connection outer conductor and the external conductor circuit, and attaching tin to bonding tools. It is to provide a TAB tape that can be prevented.
상기 목적을 위한 본 발명에 의한 TAB 테이프에서는 동 또는 동합금에 의해서 접속용 회로패턴이 형성되고 인너리드 및 아우터리드 위에 주석도금피막 또는 땜납도금피막이 형성되어 있는 TAB 테이프에 있어서, 적어도 아우터리드위에 주석도금피막 또는 땜납도금피막의 하지로서 니켈, 코발트, 금, 은, 백금, 파라듐, 로듐에서 선택된 금속에 의한 도금피막이 형성되어 있는 것을 특징으로 한다. 또 동 또는 동합금에 의해서 접속용 회로패턴이 형성되고 인너리드 및 아우터리드위에 주석도금피막 또는 땜납도금피막이 형성되어 있는 TAB 테이프에 있어서, 적어도 아우터리드위에 주석도금피막 또는 땜납도금피막의 하지로서 니켈, 코발트, 주석-니켈합금, 주석-코발트합금, 니켈-코발트합금, 주석-니켈-코발트합금 중에서 선택된 금속에 의한 제1도금피막과, 이 제1도금피막위에 형성되는 금, 은, 백금, 팔라듐, 로듐중에서 선택된 금속에 의한 제2도금피막이 형성되어 있는 것을 특징으로 한다.In the TAB tape according to the present invention for the above purpose, in a TAB tape in which a circuit pattern for connection is formed by copper or copper alloy, and a tin plating film or a solder plating film is formed on the inner lead and the outer lead, the tin plating on at least the outer lead. As the base of the coating or the solder plating film, a plating film made of a metal selected from nickel, cobalt, gold, silver, platinum, palladium and rhodium is formed. In the TAB tape, in which a circuit pattern for connection is formed by copper or copper alloy and a tin plated film or a solder plated film is formed on the inner lead and the outer lead, at least the outer layer of the tin plated or solder plated film is nickel, A first plating film made of a metal selected from cobalt, tin-nickel alloys, tin-cobalt alloys, nickel-cobalt alloys, and tin-nickel-cobalt alloys, and gold, silver, platinum, palladium, A second plating film made of a metal selected from rhodium is formed.
인너리드에 형성하는 주석도금피막 또는 땜납도금피막은 반도체 소자와 접합되는 쪽의 한쪽면에만 형성하는 것이 좋다.The tin-plated film or the solder-plated film formed on the inner lead is preferably formed only on one side of the side joined to the semiconductor element.
제1도는 TAB 테이프의 단면도를 나타내고 폴리이미드등의 내열성을 갖는 지지필름(10)위에 형성되어 있는 동박을 에칭하여 접속회로패턴이 형성되어 있다. 12는 그 인너리드, 13은 아우터리드이다. 또 동박은 동체 또는 동함금재로 되어 있다.FIG. 1 shows a cross-sectional view of a TAB tape, and a connection circuit pattern is formed by etching copper foil formed on a support film 10 having heat resistance such as polyimide. 12 is the inner lead, and 13 is the outer lead. The copper foil is made of a fuselage or a copper alloy material.
본 발명은 제1태양에 의한 TAB 테이프에서는 접속회로패턴의 동박위에 제2도에 나타낸 바와같이 도금피막(14)을 거쳐서 주석도금피막(16)을 형성한다.In the TAB tape according to the first aspect of the present invention, the tin-plated film 16 is formed on the copper foil of the connection circuit pattern via the plating film 14 as shown in FIG.
이 도금피막(14)은 반도체소자와 인너리드와의 접합시에 가해지는 400℃∼500℃ 의 고온 조건하에서도 상층의 주석도금피막(16)과 합금화하기 어려운 금속 또는 합금화에 의해서 납땜성을 저하시키지 않는 금속피막중에서 선택한다. 이와같은 금속피막은 금, 은, 백금, 팔라듐, 로듐의 귀금속피막 및 니켈, 코발트피막이다.The plating film 14 is deteriorated in solderability by metals or alloying that are difficult to alloy with the upper tin plating film 16 even under high temperature conditions of 400 ° C to 500 ° C applied at the time of joining the semiconductor element and the inner lead. Choose from metal coatings that do not. Such metal films are gold, silver, platinum, palladium, and noble metal films of rhodium, and nickel and cobalt films.
이와같은 도금피막(14)을 직접 동박위에 형성한 경우에 충분한 두께가 아닌 경우에는 동이 역시 도금피막(14)중에 확산된다.If such a plated film 14 is not formed to a sufficient thickness when directly formed on the copper foil, copper is also diffused in the plated film 14.
따라서 상기의 고온하에서도 동이 상층의 주석도금피막(16)으로 확산되지 않을 정도의 충분한 두께를 갖도록 한다.Therefore, even under the above-mentioned high temperature, copper may have a sufficient thickness such that copper does not diffuse into the upper tin-plated film 16.
주석도금피막(16)의 하지로서의 상기 도금피막(14)은 적어도 아우터리드에 형성하면 좋다. 또 인너리드측의 주석도금피막(16)은 반도체소자와 접합되는 쪽의 하나의 면에만 형성하는 것이 좋다.The plated film 14 as the base of the tin plated film 16 may be formed at least on the outer. In addition, the tin-plated film 16 on the inner lead side may be formed only on one surface of the side to be bonded to the semiconductor element.
본 발명의 제2태양에 의한 TAB 테이프에서는 접속회로패턴의 동박위에 제3도에 나타낸 바와 같이 제1도금피막(18), 제2도금피막(20)을 거쳐서 전해도금에 의한 주석도금피막(22)을 형성한다.In the TAB tape according to the second aspect of the present invention, as shown in FIG. 3 on the copper foil of the connection circuit pattern, the tin plating film 22 by electroplating through the first plating film 18 and the second plating film 20. ).
제1도금피막(18)은 반도체소자와 인너리드(12)와의 접합시에 가해지는 400℃μ500℃의 고온하에서도 소재인 동이 제1도금피막(18)중에 확산되기 어려운 금속피막으로 한다. 이와같은 제1도금피막(18)은, 니켈, 코발트, 주석-니켈합금, 주석-코발트합금, 니켈-코발트합금 및 주석-니켈-코발트합금의 도금피막중에서 선택한다.The first plated film 18 is a metal film that is hard to diffuse in the first plated film 18 of copper even under a high temperature of 400 ° C. to 500 ° C. applied at the time of bonding the semiconductor element and the inner lead 12. The first plating film 18 is selected from nickel, cobalt, tin-nickel alloy, tin-cobalt alloy, nickel-cobalt alloy, and tin-nickel-cobalt alloy.
상기 제1도금피막(18)과 주석도금피막(22)의 합금화를 방지하기 위하여 제1도금피막(18)과 주석도금피막(22)와의 사이에 제2도금피막(20)을 개재시킨다. 이 제2도금피막(20)은 상기의 고온조건하에서도 하층의 제1도금피막(18), 상층의 주석도금피막(20)의 각각과 합금화되지 않는 금속피막 또는 합금화에 의해서 납땜성을 저하시키지 않는 금속피막중에서 선택한다. 이와같은 금속피막은 금, 은, 백금, 팔라듐, 로듐의 귀금속피막이다.In order to prevent alloying of the first plating film 18 and the tin plating film 22, a second plating film 20 is interposed between the first plating film 18 and the tin plating film 22. The second plating film 20 does not deteriorate the solderability by a metal film or alloying which is not alloyed with each of the lower first plating film 18 and the upper tin plating film 20 even under the above high temperature conditions. Choose from metal coatings. Such metal coatings are precious metal coatings of gold, silver, platinum, palladium and rhodium.
주석도금피막(22)의 하지로서의 상기 제1도금피막(18) 및 제2도금피막(20)은 적어도 아우터리드에 형성하면 된다. 또 인너리드측의 주석도금피막(22)은 반도체소자와 접합되는 쪽의 하나의 면에만 형성하면 좋다.The first plating film 18 and the second plating film 20 serving as the base of the tin plating film 22 may be formed at least on the outer layer. In addition, the tin-plated film 22 on the inner lead side may be formed only on one surface of the side to be joined to the semiconductor element.
주석도금피막(16 및 22)은 종래와 같이 동박위에 직접 도금하는 경우에는 무전해도금에 의해서 형성할 수 있으나, 상기와 같이 하지가 귀금속피막일 경우에는 무전해도금으로는 형성할 수 없으므로 전해도금에 의해서 형성한다.The tin plating films 16 and 22 can be formed by electroless plating when directly plating on copper foil as in the prior art. However, when the base is a precious metal film as described above, electroless plating can not be formed. Form by.
또 주석도금피막(16 및 22) 대신에 땜납도금피막을 형성해도 좋다. 이 경우에도 소재인 동의 땜납도금피막으로의 확산의 방지와 양호한 납땜성을 얻을 수 있다.Instead of the tin plating films 16 and 22, a solder plating film may be formed. Also in this case, it is possible to prevent diffusion into the copper solder coating film, which is a raw material, and to obtain good solderability.
각층의 도금두께는 특별히 한정되는 것은 아니지만 제2도의 도금피막(14)은 0.1μm∼3.0μm, 제3도의 제1도금피막(18)은 0.1μm∼1.5μm, 제2도금피막(20)은 0.01μm∼1.01 정도가 양호하다. 또 주석도금피막(16, 22) 또는 땜납도금피막은 반도체소자 부착시의 유출을 방지하기 위하여 1μm 이하로 하는 것이 바람직하다.Although the plating thickness of each layer is not specifically limited, the plating film 14 of FIG. 2 is 0.1 micrometer-3.0 micrometers, the 1st plating film 18 of FIG. 3 is 0.1 micrometer-1.5 micrometers, and the 2nd plating film 20 0.01 micrometer-about 1.01 are favorable. In addition, the tin plating films 16 and 22 or the solder plating films are preferably 1 μm or less in order to prevent leakage when the semiconductor elements are attached.
이하에 구체적인 실시예를 나타냈다.Specific examples are shown below.
[실시예1]Example 1
동박위에 직접 주석도금피막을 0.5μm 형성한 비교예 1과 동박위에 중간도금피막으로서 은도금피막을 1.0μm 형성하고 그위에 주석도금피막을 0.5μm 형성한 실시예 1의 각각의 TAB 테이프를 220℃에서 1시간 가한 후에 250℃의 땜납중에 침지했다.Each of the TAB tapes of Comparative Example 1 in which the tin plated film was formed on the copper foil by 0.5 μm and 1.0 μm of the silver plated film as the intermediate plated film on the copper foil and 0.5 μm of the tin plated film thereon were formed at 220 ° C. It was immersed in 250 degreeC solder after adding for 1 hour.
그때의 납땜성을 솔더체커로 비교한 데이타를 표 1에 나타냈다.Table 1 shows the data comparing the solderability at that time with the solder checker.
또 적시는 응력은 7초후의 값을 사용했다.In addition, the wet stress used the value after 7 second.
[표 1]TABLE 1
표1에서 명백한 바와 같이 비교예 1에 비해서 실시예 1쪽이 양호한 납땜성이 얻어진다.As apparent from Table 1, Example 1 has better solderability than Comparative Example 1.
실시예 1에서 은도금피막 대신에 니켈, 코발트, 금, 백금 또는 로듐의 각 도금피막을 형성한 경우에도 상기와 같은 양호한 결과를 얻었다.Even in the case where each plated film of nickel, cobalt, gold, platinum or rhodium was formed in place of the silver plated film in Example 1, good results as described above were obtained.
[실시예 2]Example 2
동박위에 직접 주석도금피막을 0.5μm 형성한 비교예 2와 동박위에 제1도금피막으로서 니켈도금피막을 0.5μm 형성하고 그위에 제2도금피막으로서 팔라듐도금피막을 0.1μm 형성하고 또 그위에 주석도금피막을 0.5μm 형성한 실시예 2의 각각의 TAB 테이프를 500℃에서 2초간 가열한 후에 250℃의 땜납중에 침지시켰다. 그때의 납땜성을 실시예 1과 같이 솔더체커로 비교한 데이타를 표 2에 나타냈다.0.5 μm of tin plated film was formed directly on copper foil and 0.5 μm of nickel plated film was formed on copper foil, and 0.1 μm of palladium plated film was formed on the copper foil. Each TAB tape of Example 2 having a 0.5 μm coat formed thereon was heated at 500 ° C. for 2 seconds and then immersed in 250 ° C. solder. Table 2 shows the data comparing the solderability at that time with the solder checker as in Example 1.
[표 2]TABLE 2
표 2에서 명백한 바와같이 비교예 2에 비해서 실시예 2쪽이 납땜성이 양호하였다.As apparent from Table 2, the solderability of Example 2 was better than that of Comparative Example 2.
실시예 2에서 제1도금피막을 코발트도금피막으로 하고 제2도금피막을 금, 은, 백금, 또는 로듐의 각 도금피막으로 하여도 상기와 같은 양호한 결과를 얻었다.In Example 2, even when the first plated film was used as the cobalt plated film and the second plated film was each plated film of gold, silver, platinum, or rhodium, good results as described above were obtained.
[실시예 3]Example 3
동박위에 직접 주석도금피막을 0.5μm 형성한 비교예 3과 동박위에 제1도금피막으로서 주석-니켈합금 피막을 0.5μm 형성하고 그위에 제2도금피막으로서 금도금피막을 0.1μm 형성하고 또 그위에 주석도금피막을 0.5μm 형성한 실시예 3의 각각의 TAB 테이프를 220℃에서 1시간 가열한 후에 250℃의 땜납중에 침지시켰다. 그때의 납땜성을 실시예 1과 같이 솔더체커로 비교한 데이타를 표 3에 나타냈다.0.5 μm of tin-coated film directly on copper foil and 0.5 μm of tin-nickel alloy film as first plating film on copper foil, and 0.1 μm of gold-plated film on second copper film. Each TAB tape of Example 3, in which 0.5 µm of the plated film was formed, was heated at 220 ° C for 1 hour and then immersed in 250 ° C solder. Table 3 shows the data comparing the solderability at that time with the solder checker as in Example 1.
[표 3]TABLE 3
표 3에서 명백한 바와같이 비교예 3에 비해서 실시예 3쪽이 양호한 납땜성이 얻어져 있다.As apparent from Table 3, Example 3 has better solderability than Comparative Example 3.
또 실시예 3에서 제1도금피막을 주석-코발트합금, 니켈-코발트합금, 주석-니켈-코발트합금의 각 도금피막으로 한 경우 및 제2도금피막을 은, 백금, 파라듐, 로듐으로 한 경우도 양호한 납땜성을 얻을 수 있었다.In Example 3, when the first plating film is a plating film of tin-cobalt alloy, nickel-cobalt alloy, tin-nickel-cobalt alloy, and the second plating film is silver, platinum, paradium, and rhodium, Also good solderability was obtained.
또 상기 각 실시예에서 주석도금피막 대신에 땜납도금피막으로 하여도 양호한 납땜성을 얻을 수 있었다.In each of the above examples, good solderability was obtained even if the solder plating film was used instead of the tin plating film.
또 상기 각 실시예에서 인너리드에 은도금피막을 반도체소자와 접합되는 쪽의 하나의 면에만 형성하고 본딩툴쪽면에는 형성하지 않은 결과 본딩툴에 주석 또는 금-주석이 부착하지 않고 양호하게 인너리드의 본딩이 행해졌다.In each of the above embodiments, the silver plated film is formed on the inner lead only on one side of the side to be bonded to the semiconductor element, but not on the side of the bonding tool. Thus, tin or gold-tin does not adhere to the bonding tool. Bonding was done.
이상 본 발명에 대해서 실시예를 들어 설명하였으나 본 발명은 이들 실시예에 한정되는 것은 아니고 발명의 정신을 일탈하지 않는 범위내에서 많은 개변을 할 수 있는 것은 물론이다.Although the present invention has been described with reference to examples, the present invention is not limited to these examples, and of course, many modifications can be made without departing from the spirit of the invention.
이상과 같이 본 발명에 의하면 동 또는 동합금으로 된 접속용 회로패턴과 주석도금피막 또는 땜납도금피막 사이에 상기한 도금피막을 개재시킴으로써 400℃∼500℃ 정도의 고온조건이 가해져도 양호한 납땜성이 얻어진다.As described above, according to the present invention, good solderability is obtained by interposing the above-described plating film between the circuit pattern for connection made of copper or copper alloy and the tin plating film or the solder plating film. Lose.
또 인너리드에 반도체소자와 접합되는 쪽의하나의 면에만 주석도금피막 또는 땜납도금피막을 형성함으로써 본딩툴에 이들 금속이 부착되지 않아 인너리드의 본딩이 양호하게 행해지는 것이다.In addition, since the tin-plated film or the solder-plated film is formed on only one surface of the inner lead bonded to the semiconductor element, these metals do not adhere to the bonding tool, and the inner lead is bonded well.
Claims (2)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2-200183 | 1990-07-27 | ||
| JP90-200183 | 1990-07-27 | ||
| JP20018390A JP2892455B2 (en) | 1989-12-18 | 1990-07-27 | TAB tape |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920002318A KR920002318A (en) | 1992-02-28 |
| KR950008697B1 true KR950008697B1 (en) | 1995-08-04 |
Family
ID=16420179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910012686A KR950008697B1 (en) | 1990-07-27 | 1991-07-24 | Tab tape |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950008697B1 (en) |
-
1991
- 1991-07-24 KR KR1019910012686A patent/KR950008697B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR920002318A (en) | 1992-02-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5384204A (en) | Tape automated bonding in semiconductor technique | |
| KR100237940B1 (en) | A semiconductor device, a method for manufacturing thereof, and a lead made of copper | |
| JP3201957B2 (en) | Metal bump, method for manufacturing metal bump, connection structure | |
| CA2118758C (en) | Lead frame for integrated circuits | |
| JPS61196564A (en) | Film carrier integrated circuit and manufacture thereof | |
| JPS61142750A (en) | Insulating substrate | |
| USH498H (en) | Electronic component including soldered electrical leads | |
| US5061552A (en) | Multi-layer ceramic substrate assembly and a process for manufacturing same | |
| JP2000077593A (en) | Lead frame for semiconductor | |
| JPH1022434A (en) | Lead frame for integrated circuit and manufacture thereof | |
| JP2002289653A (en) | Semiconductor device tape carrier and its manufacturing method | |
| JPH1093004A (en) | Electronic component and manufacture thereof | |
| KR950008697B1 (en) | Tab tape | |
| JPH01257356A (en) | Lead frame for semiconductor | |
| EP0468787A2 (en) | Tape automated bonding in semiconductor technique | |
| JP2892455B2 (en) | TAB tape | |
| JPH0146228B2 (en) | ||
| JP2858197B2 (en) | Lead frame for semiconductor device | |
| JP2000174191A (en) | Semiconductor device and its manufacture | |
| US4765528A (en) | Plating process for an electronic part | |
| JPH05206620A (en) | Metallic base circuit board | |
| JP2627509B2 (en) | Electronic component having conductive layer | |
| JPH0398210A (en) | Complex metal plating wire | |
| WO2001076335A1 (en) | Mounting structure of electronic device and method of mounting electronic device | |
| JPH1084065A (en) | Conductive material for electronic component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050722 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |