JPS61142750A - Insulating substrate - Google Patents

Insulating substrate

Info

Publication number
JPS61142750A
JPS61142750A JP60261166A JP26116685A JPS61142750A JP S61142750 A JPS61142750 A JP S61142750A JP 60261166 A JP60261166 A JP 60261166A JP 26116685 A JP26116685 A JP 26116685A JP S61142750 A JPS61142750 A JP S61142750A
Authority
JP
Japan
Prior art keywords
solder
semiconductor chip
metal film
substrate
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60261166A
Other languages
Japanese (ja)
Inventor
Toru Kawanobe
川野辺　徹
Keiji Miyamoto
宮本　圭二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60261166A priority Critical patent/JPS61142750A/en
Publication of JPS61142750A publication Critical patent/JPS61142750A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain highly reliable bonding, whose strength is not deteriorated even if the bonded part is made to remain in a high temperature environment, by providing a first metal film, which is not substantially reacted with solder at a soldering temperature or less, at an electrode connecting part, and providing a second metal film, which is formed on the first metal film and readily becomes wet with the solder. CONSTITUTION:A ceramic wiring substrate 11 is manufactured by a wet method. For example, the material of an insulating film 19, which covers a part of a tungsten wiring 18 other than a bonding part, is alumina, which is the same material as that of the substrate. After the ceramic substrate is sintered, nickel plating 20 and gold plating 21 are provided in the opening part of the insulating film 19. A semiconductor chip 17, to which a solder electrode 16 is attached, is prepared. The amount of the solder 16 is controlled as required. Then, the semiconductor chip 17 is aligned to the specified positions, where the metal films 20 and 21 are formed. Thereafter, the chip is heated to a temperature higher than the melting point of the solder, and the solder is made to reflow. Thus the semiconductor chip 17 is bonded to the specified position.

Description

【発明の詳細な説明】 本発明ははんだ電極付半導体素子（以下半導体チップと
称す）が実装される絶縁基板に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulating substrate on which a semiconductor element with solder electrodes (hereinafter referred to as a semiconductor chip) is mounted.

はんだ電極付半導体チップの実装法ではＩＢＭ社の開発
した方法（特公昭４８−１６５４号）が最も一般的であ
る。この方法は、半導体チップのはんだ電極とはんだリ
フローボンディングするため、絶縁基板の電極接続部に
あらかじめはんだペデスタルの一部を形成しておくと同
時にはんだペデスタルの一部をはんだにぬれない材料で
おおっておくことを特徴とする。The most common method for mounting semiconductor chips with solder electrodes is the method developed by IBM (Japanese Patent Publication No. 48-1654). In this method, in order to perform solder reflow bonding with the solder electrodes of the semiconductor chip, a part of the solder pedestal is formed in advance at the electrode connection part of the insulating substrate, and at the same time, part of the solder pedestal is covered with a material that cannot be wetted by solder. It is characterized by keeping it.

上記ＩＢＭのはんだ接続法はＣＣＢ　（Ｃｏｎｔｒｏｌ
−１ｅｄ　Ｃｏ１１ａｐｓｅ　Ｂｏｎｄｉｎｇ）法とよ
ばれており、実際には第１図（ａ）に示したようにセラ
ミック基板１１上に印刷法によりＡｇ−Ｐｄ導体配線１
２を形成し、接合部１８を除きガラス膜１４をかぶせる
。この後さらにはんだ槽に浸漬してはんだペデスタル１
５を形成する。そして第１図（ｂ）に示すようにはんだ
電極１６が付いている半導体チップ１７を上記ペデスタ
ル１５上に位置合せし、はんだの融点以上に加熱しはん
だをリフローさせ接続している。The above IBM solder connection method is CCB (Control
This is called the -1ed Co11apse Bonding) method, and in reality, as shown in FIG.
2 is formed, and the glass film 14 is covered except for the joint portion 18. After this, the solder pedestal 1 is further immersed in the solder bath.
form 5. Then, as shown in FIG. 1(b), the semiconductor chip 17 with the solder electrode 16 attached thereto is aligned on the pedestal 15, and the solder is reflowed and connected by heating to a temperature above the melting point of the solder.

この方法の問題点はＡｇ−Ｐｄ導体中の特にＡｇがはん
だ中に拡散し、Ａｇ−Ｐｄ層がどんどん減少するいわゆ
る”くわれ”現象のためにはんだリフロー条件が不適当
の場合や、高温に長く置かれた場合に、接合部の強度が
劣化し、ひどい場合には破断することである。The problem with this method is that the solder reflow conditions are inappropriate due to the so-called "depression" phenomenon in which the Ag in the Ag-Pd conductor is diffused into the solder and the Ag-Pd layer is gradually reduced, or when the solder is exposed to high temperatures. If left for a long time, the strength of the joint will deteriorate, and in severe cases, it will break.

本発明の目的は上記従来方法の問題をなくし、高温でも
接合強度が劣化しないようにされた電極接続部を有する
絶縁基板を提供することである。An object of the present invention is to eliminate the problems of the above-mentioned conventional method and to provide an insulating substrate having an electrode connection portion that prevents the bonding strength from deteriorating even at high temperatures.

本発明は、半導体素子のはんだ電極を接続するための電
極接続部を有する絶縁基板であって、上記電極接続部は
はんだ付温度以下では実質的にはんだと反応しない第１
の金属膜及びその上に形成されたはんだとぬれやすい第
２の金属膜を有することを特徴とする。The present invention provides an insulating substrate having an electrode connection portion for connecting a solder electrode of a semiconductor element, wherein the electrode connection portion is a first insulating substrate that does not substantially react with solder below a soldering temperature.
The second metal film is formed on the second metal film and is easily wetted with solder.

以下第２図（ａ）、（ｂ）により本発明の絶縁基板を用
いた半導体接続法の一実施例について詳細に説明する。An embodiment of the semiconductor connection method using an insulating substrate according to the present invention will be described in detail below with reference to FIGS. 2(a) and 2(b).

まず第２図（ａ）に示すようにセラミック配線基板１１
を湿式法により製造する。即ち１８はタングステン配線
であり、このボンディング部以外を覆う絶縁膜１９は基
板と同材質のアルミナである。First, as shown in FIG. 2(a), a ceramic wiring board 11
is produced by a wet method. That is, 18 is a tungsten wiring, and the insulating film 19 covering the area other than the bonding portion is made of alumina, which is the same material as the substrate.

セラミック基板焼結機絶縁膜１９の開孔部に化学めっき
法により約２μｍのニッケルめっき２０、約２μｍの金
めっき２１をほどこす、上記タングステン１８、ニッケ
ル２０、金２１を総称して導体配線と称す、そしてはん
だ電極１６が付いた半導体チップ１７を用意する。上記
はんだ１６の量は必要に応じてコントロールする。Approximately 2 μm nickel plating 20 and approximately 2 μm gold plating 21 are applied to the openings of the ceramic substrate sintering machine insulating film 19 by chemical plating, and the tungsten 18, nickel 20, and gold 21 are collectively referred to as conductor wiring. A semiconductor chip 17 having a solder electrode 16 attached thereto is prepared. The amount of the solder 16 is controlled as necessary.

次に同図（ｂ）に示すように半導体チップ１７を金属膜
２０．２１が形成された所定位置に位置合せし、その後
はんだの融点以上の温度に加熱しはんだをリフローさせ
て上記半導体チップ１７を所定位置に接合する。Next, as shown in FIG. 2B, the semiconductor chip 17 is aligned at a predetermined position where the metal film 20.21 is formed, and then the semiconductor chip 17 is heated to a temperature higher than the melting point of the solder to reflow the solder. Join them in place.

以上説明した本発明の絶縁基板によれば、基板例のタン
グステン、及びこれの表面をおおうニッケル膜ははんだ
とほとんど反応しないので、高温に放置しても接合部の
強度は劣化せず信頼性の高い接合が得られる。又、ニッ
ケルめっき上にほどこした金めつきはニッケルめっき膜
の酸化を防ぎ。According to the insulating substrate of the present invention described above, the tungsten of the substrate example and the nickel film covering the surface of the substrate hardly react with solder, so even if left at high temperatures, the strength of the joint does not deteriorate and reliability is maintained. High bonding can be obtained. In addition, the gold plating applied on the nickel plating prevents the nickel plating film from oxidizing.

はんだとのぬれ性をよくするものであるため従来法で必
要としたはんだペデスタルは不要となる゛。Since it improves wettability with solder, the solder pedestal required in the conventional method is no longer necessary.

なお実施例ではタングステンを用いたが、タングステン
合金、モリブデン合金等でもよい、又、上記タングステ
ン上にめっきするニッケルの代りにはんだとの反応性が
それほど大きくない（はんだ付温度以下では実質的には
んだと反応しない）金属１例えば銅、鉄、コバルト、及
びニッケルを含むこれらの合金でもよい。又金めっきの
かわりに、はんだ付性のよい錫、鉛、はんだ銀等でもよ
い、又、セラミック基板を乾式法で製造しても良い。Although tungsten was used in the examples, tungsten alloys, molybdenum alloys, etc. may also be used.Also, instead of nickel plated on the tungsten, the reactivity with solder is not so great (substantially no solder metals 1 (which do not react with metals), such as copper, iron, cobalt, and alloys thereof, including nickel. Moreover, instead of gold plating, tin, lead, solder silver, etc. with good solderability may be used, and the ceramic substrate may be manufactured by a dry method.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）は従来の絶縁基板を用いたはんだ
電極を有する半導体チップの接続法を示す断面図、第２
図（ａ）、（ｂ）は本発明による絶縁基板を用いたはん
だ電極を有する半導体チップの接続法を示す断面図であ
る。 １１・・・セラミック基板、１２・・・Ａｇ−Ｐｄ導体
配線、１８・・・接合部、１４・・・ガラスダム、１５
・・・はんだペデスタル、１６・・・半導体チップ側は
んだ電極、１７・・・半導体チップ、１８・・・タング
ステン配線、１９・・・アルミナオーバーコート、２０
・・・ニッケルめっき層、２１・・・金めつき層・− 第　　１　　図 第　　２　　図1(a) and 1(b) are cross-sectional views showing a conventional method for connecting semiconductor chips with solder electrodes using an insulating substrate;
Figures (a) and (b) are cross-sectional views showing a method of connecting a semiconductor chip having solder electrodes using an insulating substrate according to the present invention. DESCRIPTION OF SYMBOLS 11...Ceramic board, 12...Ag-Pd conductor wiring, 18...Joint part, 14...Glass dam, 15
... Solder pedestal, 16... Semiconductor chip side solder electrode, 17... Semiconductor chip, 18... Tungsten wiring, 19... Alumina overcoat, 20
...Nickel plating layer, 21...Gold plating layer-- Fig. 1 Fig. 2

Claims (1)

【特許請求の範囲】[Claims] １、半導体素子のはんだ電極を接続するための電極接続
部を有する絶縁基板であって、上記電極接続部ははんだ
付温度以下では実質的にはんだと反応しない第１の金属
膜及びその上に形成されたはんだとぬれやすい第２の金
属膜を有することを特徴とする絶縁基板。1. An insulating substrate having an electrode connection portion for connecting a solder electrode of a semiconductor element, wherein the electrode connection portion is formed on a first metal film that does not substantially react with solder below the soldering temperature; An insulating substrate characterized by having a second metal film that is easily wetted with solder.
JP60261166A 1985-11-22 1985-11-22 Insulating substrate Pending JPS61142750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60261166A JPS61142750A (en) 1985-11-22 1985-11-22 Insulating substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60261166A JPS61142750A (en) 1985-11-22 1985-11-22 Insulating substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP15855278A Division JPS5586130A (en) 1978-12-25 1978-12-25 Connection of semiconductor element

Publications (1)

Publication Number Publication Date
JPS61142750A true JPS61142750A (en) 1986-06-30

Family

ID=17358033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60261166A Pending JPS61142750A (en) 1985-11-22 1985-11-22 Insulating substrate

Country Status (1)

Country Link
JP (1) JPS61142750A (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111279A (en) * 1989-08-28 1992-05-05 Lsi Logic Corp. Apparatus for isolation of flux materials in "flip-chip" manufacturing
US5168346A (en) * 1989-08-28 1992-12-01 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5249098A (en) * 1991-08-22 1993-09-28 Lsi Logic Corporation Semiconductor device package with solder bump electrical connections on an external surface of the package
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5311060A (en) * 1989-12-19 1994-05-10 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5329423A (en) * 1993-04-13 1994-07-12 Scholz Kenneth D Compressive bump-and-socket interconnection scheme for integrated circuits
US5363277A (en) * 1991-12-20 1994-11-08 Rohm Co., Ltd. Structure and method for mounting semiconductor device
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US6839479B2 (en) 2002-05-29 2005-01-04 Silicon Light Machines Corporation Optical switch
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50107463A (en) * 1974-01-30 1975-08-23
JPS5198991A (en) * 1975-02-26 1976-08-31
JPS5586130A (en) * 1978-12-25 1980-06-28 Hitachi Ltd Connection of semiconductor element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50107463A (en) * 1974-01-30 1975-08-23
JPS5198991A (en) * 1975-02-26 1976-08-31
JPS5586130A (en) * 1978-12-25 1980-06-28 Hitachi Ltd Connection of semiconductor element

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347162A (en) * 1989-08-28 1994-09-13 Lsi Logic Corporation Preformed planar structures employing embedded conductors
US5168346A (en) * 1989-08-28 1992-12-01 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5111279A (en) * 1989-08-28 1992-05-05 Lsi Logic Corp. Apparatus for isolation of flux materials in "flip-chip" manufacturing
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5410805A (en) * 1989-08-28 1995-05-02 Lsi Logic Corporation Method and apparatus for isolation of flux materials in "flip-chip" manufacturing
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5311060A (en) * 1989-12-19 1994-05-10 Lsi Logic Corporation Heat sink for semiconductor device assembly
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5249098A (en) * 1991-08-22 1993-09-28 Lsi Logic Corporation Semiconductor device package with solder bump electrical connections on an external surface of the package
US5363277A (en) * 1991-12-20 1994-11-08 Rohm Co., Ltd. Structure and method for mounting semiconductor device
US5434750A (en) * 1992-02-07 1995-07-18 Lsi Logic Corporation Partially-molded, PCB chip carrier package for certain non-square die shapes
US5329423A (en) * 1993-04-13 1994-07-12 Scholz Kenneth D Compressive bump-and-socket interconnection scheme for integrated circuits
US5438477A (en) * 1993-08-12 1995-08-01 Lsi Logic Corporation Die-attach technique for flip-chip style mounting of semiconductor dies
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6452260B1 (en) 1997-09-02 2002-09-17 Silicon Light Machines Electrical interface to integrated circuit device having high density I/O count
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US6839479B2 (en) 2002-05-29 2005-01-04 Silicon Light Machines Corporation Optical switch
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same

Similar Documents

Publication Publication Date Title
JPS61142750A (en) Insulating substrate
US4005454A (en) Semiconductor device having a solderable contacting coating on its opposite surfaces
US4727633A (en) Method of securing metallic members together
JP3201957B2 (en) Metal bump, method for manufacturing metal bump, connection structure
US4268585A (en) Soldering to a gold member
EP0380289B1 (en) A process of manufacturing a multi-layer ceramic substrate assembly
USRE27934E (en) Circuit structure
JPH081770B2 (en) Electrical contact structure
JP3339384B2 (en) Solder material, printed wiring board and method of manufacturing the same
JP3024506B2 (en) Connection method between Si chip and package
JP3359521B2 (en) Method for manufacturing semiconductor device
JPH10144850A (en) Connecting pin and mounting method of substrate
JP2000164785A (en) Pin, manufacture of the pin, and wiring board equipped with the pin
JPS643333B2 (en)
JP3279846B2 (en) Method for manufacturing semiconductor device
JPS6344991Y2 (en)
KR950008697B1 (en) Tab tape
JP2886945B2 (en) Wiring board
JPH0341475Y2 (en)
JPH05218269A (en) Semiconductor device
JPH0736429B2 (en) Method for manufacturing ceramic wiring board
JP2968969B2 (en) Wiring board
JPH08153727A (en) Connection member, electronic component assembled body using it and its manufacture
JPS61141156A (en) Semiconductor element
JPH0613434A (en) Film carrier for semiconductor device