JPS61141156A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS61141156A
JPS61141156A JP59262798A JP26279884A JPS61141156A JP S61141156 A JPS61141156 A JP S61141156A JP 59262798 A JP59262798 A JP 59262798A JP 26279884 A JP26279884 A JP 26279884A JP S61141156 A JPS61141156 A JP S61141156A
Authority
JP
Japan
Prior art keywords
solder
copper
tin
semiconductor element
contained
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59262798A
Other languages
Japanese (ja)
Inventor
Shinobu Taima
当間　忍
Kiichiro Kubo
毅一郎 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Consumer Electronics Co Ltd
Japan Display Inc
Original Assignee
Hitachi Device Engineering Co Ltd
Hitachi Ltd
Hitachi Consumer Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Device Engineering Co Ltd, Hitachi Ltd, Hitachi Consumer Electronics Co Ltd filed Critical Hitachi Device Engineering Co Ltd
Priority to JP59262798A priority Critical patent/JPS61141156A/en
Publication of JPS61141156A publication Critical patent/JPS61141156A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Abstract

PURPOSE:To suppress the diffusion of copper into solder when copper is connected to a wiring by a method wherein copper-contained solder is used for a solder bump. CONSTITUTION:A plurality of solder bumps 2 are provided on the semiconductor element 1 consisting of a semiconductor chip. At this point, each solder bump 2 consists of copper-contained solder. The copper-contained solder is same as the generally known material which is used for prevention of fusing away of the tip of a soldering iron made of copper, and the quantity of tin is relatively reduced by adding copper of 0.1-10% (desirably 0.5-2%) or thereabout of tin. In this case, after lead and tin of the desired ratio is coated in advance on the under-solder electrode 3 formed on the terminal of the semiconductor element 1 by performing plating, vapor-deposition and other method, and copper is coated until the prescribed ratio is obtained by performing plating, vapor- deposition and other method. Subsequently, the solder bump 2 consisting of copper-contained solder is formed by fusing said metal layer.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体素子、特に、ＣＣＢ方式により実装され
るはんだバンプ付半導体素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device with solder bumps mounted by a CCB method.

〔発明の背景〕[Background of the invention]

現在半導体素子の基板への実装方式のひとつとしてＣＣ
Ｂ　（Ｃｏｎｔｒｏｌｌｅｄ　Ｃｏｌ　１ａｐｓｅ　Ｂ
ｏｎｄｉｎｇ　）方式が広く用いられている。この方式
は、ワイヤレスボンディングの一櫨で、半導体チップ上
に形成したはんだ端子（パンツ）と基板上に形成したけ
んだ端子とを機械的かつ電気的に接合する技術であるが
、一般ｌこ基板側はセラミックであり、ＣＣＤ用の電極
として黄金）Ｉ４（金、銀、パラジウム、白金等）のペ
ーストを厚膜印刷して用いている（「ＬｓＩ技術」電子
通信学会刊行、昭和５４年　　−３月２０日）。CC is currently one of the methods for mounting semiconductor devices on substrates.
B (Controlled Col 1apse B
onding) method is widely used. This method is a form of wireless bonding, and is a technology that mechanically and electrically joins solder terminals (pants) formed on a semiconductor chip and solder terminals formed on a substrate. The sides are made of ceramic and are used as electrodes for CCDs by printing a thick film of gold I4 (gold, silver, palladium, platinum, etc.) paste ("LsI technology" published by the Institute of Electronics and Communication Engineers, 1978-3). 20th of the month).

しかしながら、貴金属の使用はその製造コストを上昇さ
せるため、貴金属の代りに鋼薄膜を用いてコストを低減
させることが考えられる。However, since the use of precious metals increases the manufacturing cost, it may be possible to reduce costs by using a steel thin film instead of the precious metals.

ところが、このようｌこ銅配線を用い、その上着こチッ
プをはんだ付した場合、はんだ中のスズが銅と合金をつ
くって接合するが、この合金層が時間とともに厚くなり
、銅配線の厚さ方向に成長するいわゆるはんだ喰われ現
象が生じ、ついｌこは破壊、すなわち接続不良ｌこ至る
という問題がある。このような合金層の成長は、使用ま
たは保管時の温度および時間等−こよって影響を受け、
特ｊこはんだ何時および６０〜８０℃以上の高温時にお
いては発生しやすい。However, when using this kind of copper wiring and soldering the outer chip, the tin in the solder forms an alloy with the copper and joins, but this alloy layer thickens over time and the thickness of the copper wiring increases. There is a problem in that a so-called solder eating phenomenon occurs in which the solder grows in the horizontal direction, and eventually leads to destruction, that is, a poor connection. The growth of such an alloy layer is influenced by temperature and time during use or storage, etc.
This is particularly likely to occur during soldering and at high temperatures of 60 to 80°C or higher.

そこで、このような不良の発生を防ぐために、従来は銅
配線の厚さを例えば２〜３μｍ以上と十分厚くシ、はん
だ喰われｌこよる破壊に至るまでの時間をその製品の規
定寿命より長くする方法を用いていた。Therefore, in order to prevent the occurrence of such defects, conventionally the thickness of the copper wiring was made sufficiently thick, for example, 2 to 3 μm or more, so that the time required for the copper wiring to be eaten by the solder and cause damage was longer than the specified life of the product. The method was used.

しかしながら、この方法は鋼薄膜の作成に長時間を要す
るとともに材料の使用量もかさみ、コスト高につながる
。However, this method requires a long time to create the steel thin film and also requires a large amount of material, leading to high costs.

〔発明の目的〕[Purpose of the invention]

本発明はこのような事情に鑑みてなされたもので、その
目的は、銅配線上に接続したときに銅のはんだ中への拡
散を抑制することが可能なＣＣＢ接続用半導体素子を提
供することにある。The present invention has been made in view of the above circumstances, and its purpose is to provide a semiconductor element for CCB connection that can suppress diffusion of copper into solder when connected to copper wiring. It is in.

〔発明の概要〕[Summary of the invention]

このような目的を達成するために、本発明は、はんだバ
ンプに銅入はんだを用いたものである。In order to achieve such an object, the present invention uses copper-containing solder for the solder bumps.

〔発明の実施例〕[Embodiments of the invention]

第１図は本発明の一実施例を示す斜視図で、半導体チッ
プからなる半導体素子１に、複数のはんだバンプ２が設
けである。FIG. 1 is a perspective view showing an embodiment of the present invention, in which a plurality of solder bumps 2 are provided on a semiconductor element 1 made of a semiconductor chip.

ここで、各はんだバンプ２は屑入はんだからなる。銅入
はんだは、銅製はんだコテ先の溶失防止用として知られ
ているものと同様で、銅をスズの０．１〜１０％（望ま
しくは０．５〜２％）程度添加することｌこより相対的
にスズの量を減少させたものである。Here, each solder bump 2 is made of scrap solder. Copper-containing solder is similar to that known for preventing copper soldering iron tips from melting away, and copper is added to the tin by about 0.1 to 10% (preferably 0.5 to 2%). The amount of tin is relatively reduced.

本実施例では、第２図に示すように、予め半導体素子１
の端子上に形成したはんだ下電極３上にメッキまたは蒸
着その他の方法により鉛およびスズを所望の比で被着さ
せた後、同じくメッキまたは蒸着その他の方法により銅
を所定の比となるように被着し、その後、この金属層を
融触することによって銅入はんだからなるはんだバング
２を形成した。In this embodiment, as shown in FIG.
After depositing lead and tin in a desired ratio on the solder lower electrode 3 formed on the terminal by plating, vapor deposition, or other method, copper is deposited in a predetermined ratio by plating, vapor deposition, or other method. The metal layer was then melted to form a solder bang 2 made of copper-containing solder.

このはんだバンプ付半導体素子をセラミック基板上に形
成した銅配線上ｌこ位置決めし、加熱することによって
融着するが、上記鋼入はんだを用いたことにより、はん
だ付は性そのものは損わすに、合金層の成長を通常のは
んだバンプを用いた場合の１／１０から１／１００に抑
圧することができた。This semiconductor element with solder bumps is positioned on the copper wiring formed on the ceramic substrate and fused by heating, but since the above-mentioned steel-filled solder is used, the solderability itself is impaired. The growth of the alloy layer could be suppressed to 1/10 to 1/100 of that when using normal solder bumps.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、銅入はんだバン
プを用いたことｌこより、基板側に銅配線を用いしかも
銅のはんだ中への拡散を有効に抑圧することができるた
め、銅配線の厚さを例えば０．５〜２μｍと薄くシ、か
つ長寿命化をはかることができ、コストを低減すること
ができる利点を有する。As explained above, according to the present invention, by using copper-containing solder bumps, copper wiring can be used on the board side and diffusion of copper into the solder can be effectively suppressed. It has the advantage that the thickness can be reduced to, for example, 0.5 to 2 μm, and the service life can be extended and costs can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す斜視図、第２図ははん
だバンプを示す側面図である。 １・・・・半導体素子、２・・嗜・はんだバンプ、３・
・・・はんだ下電極。FIG. 1 is a perspective view showing an embodiment of the present invention, and FIG. 2 is a side view showing a solder bump. 1. Semiconductor element, 2. Solder bump, 3.
...Solder bottom electrode.

Claims (1)

【特許請求の範囲】[Claims] 　はんだバンプ付半導体素子において、バンプを構成す
るはんだとして銅入はんだを用いたことを特徴とする半
導体素子。A semiconductor element with solder bumps, characterized in that a copper-containing solder is used as solder constituting the bumps.
JP59262798A 1984-12-14 1984-12-14 Semiconductor element Pending JPS61141156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59262798A JPS61141156A (en) 1984-12-14 1984-12-14 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59262798A JPS61141156A (en) 1984-12-14 1984-12-14 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS61141156A true JPS61141156A (en) 1986-06-28

Family

ID=17380752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59262798A Pending JPS61141156A (en) 1984-12-14 1984-12-14 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS61141156A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4902157A (en) * 1986-09-19 1990-02-20 Jidosha Denki Kogyo Kabushiki Kaisha Sealing structure for a ball joint of a wiper link mechanism
KR20030081172A (en) * 2002-04-12 2003-10-17 엔이씨 일렉트로닉스 코포레이션 Semiconductor device and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4902157A (en) * 1986-09-19 1990-02-20 Jidosha Denki Kogyo Kabushiki Kaisha Sealing structure for a ball joint of a wiper link mechanism
KR20030081172A (en) * 2002-04-12 2003-10-17 엔이씨 일렉트로닉스 코포레이션 Semiconductor device and method for fabricating the same

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