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JPH04307944A - Semiconductor element connecting material and semiconductor device - Google Patents

Semiconductor element connecting material and semiconductor device

Info

Publication number
JPH04307944A
JPH04307944A JP7294891A JP7294891A JPH04307944A JP H04307944 A JPH04307944 A JP H04307944A JP 7294891 A JP7294891 A JP 7294891A JP 7294891 A JP7294891 A JP 7294891A JP H04307944 A JPH04307944 A JP H04307944A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
pd
alloy
solder
layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7294891A
Inventor
Hideyuki Akimoto
Toshinori Kogashiwa
Hiroyuki Shigyo
Original Assignee
Tanaka Denshi Kogyo Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions ; Methods of application thereof

Abstract

PURPOSE: To hold down the acceleration of ionization of Ag contained in a solder alloy and to prevent migration from being caused and thereby to provide connection material having a high electric reliability by allowing the solder alloy, mainly composed of Pb, Sn or In, to contain Ag and Pd and by making the ratio of Pd to Ag the specified value or above.
CONSTITUTION: A solder alloy, mainly composed of Pb, Sn or In, is allowed to contain Ag and Pb. The ratio of Pd to Ag [Pd wt% (Ag wt%+Pd wt%)] is 0.1 or above. Such solder alloy is used as connection material. It is preferable that 1-5wt% of Ag should be contained in the solder alloy. A semiconductor element 2 and a substrate 1 are connected with the said connection material 3 to fabricate a semiconductor device. For example, a metallized layer 4 which is constituted of Ti layer, Ni layer and Au layer is formed on the ceramic substrate 1 and the same metallized layer 5 is formed on the semiconductor chip 2 and the connection material 3 is bonded between the two metallized layers 4 and 5.
COPYRIGHT: (C)1992,JPO&Japio
JP7294891A 1991-04-05 1991-04-05 Semiconductor element connecting material and semiconductor device Pending JPH04307944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7294891A JPH04307944A (en) 1991-04-05 1991-04-05 Semiconductor element connecting material and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7294891A JPH04307944A (en) 1991-04-05 1991-04-05 Semiconductor element connecting material and semiconductor device

Publications (1)

Publication Number Publication Date
JPH04307944A true true JPH04307944A (en) 1992-10-30

Family

ID=13504117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7294891A Pending JPH04307944A (en) 1991-04-05 1991-04-05 Semiconductor element connecting material and semiconductor device

Country Status (1)

Country Link
JP (1) JPH04307944A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508562A (en) * 1992-12-08 1996-04-16 Murata Manufacturing Co., Ltd. Outer electrode structure for a chip type electronic part appropriate for reflow soldering
US6187114B1 (en) 1996-10-17 2001-02-13 Matsushita Electric Industrial Co. Ltd. Solder material and electronic part using the same
US6436730B1 (en) * 1993-10-04 2002-08-20 Motorola, Inc. Microelectronic package comprising tin copper solder bump interconnections and method for forming same
US6821814B2 (en) * 1994-01-31 2004-11-23 International Business Machines Corporation Method for joining a semiconductor chip to a chip carrier substrate and resulting chip package
US8115307B2 (en) * 2006-03-31 2012-02-14 Intel Corporation Embedding device in substrate cavity

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508562A (en) * 1992-12-08 1996-04-16 Murata Manufacturing Co., Ltd. Outer electrode structure for a chip type electronic part appropriate for reflow soldering
US6436730B1 (en) * 1993-10-04 2002-08-20 Motorola, Inc. Microelectronic package comprising tin copper solder bump interconnections and method for forming same
US6821814B2 (en) * 1994-01-31 2004-11-23 International Business Machines Corporation Method for joining a semiconductor chip to a chip carrier substrate and resulting chip package
US6187114B1 (en) 1996-10-17 2001-02-13 Matsushita Electric Industrial Co. Ltd. Solder material and electronic part using the same
US8115307B2 (en) * 2006-03-31 2012-02-14 Intel Corporation Embedding device in substrate cavity

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