JPH0620083B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0620083B2 JPH0620083B2 JP61024797A JP2479786A JPH0620083B2 JP H0620083 B2 JPH0620083 B2 JP H0620083B2 JP 61024797 A JP61024797 A JP 61024797A JP 2479786 A JP2479786 A JP 2479786A JP H0620083 B2 JPH0620083 B2 JP H0620083B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode plate
- plate
- plating
- substrate
- metal substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
Landscapes
- Chemically Coating (AREA)
- Die Bonding (AREA)
Description
本発明は、半導体基板の一面が半導体材料に近い熱膨張
係数を有する金属よりなる電極板を介して熱良導性の金
属基板に固定される半導体素子の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor element in which one surface of a semiconductor substrate is fixed to a metal substrate having good thermal conductivity via an electrode plate made of metal having a thermal expansion coefficient close to that of a semiconductor material.
半導体基板と金属基板の間に挿入される電極板は、半導
体基板に熱応力を与えないために熱膨張係数が半導体基
板に近く、また半導体基板とのろう付け部の熱抵抗を低
くするために表面のろう付け性の良好なことが望まれ
る。第2図に示す半導体素子における電極板としては、
シリコン板1に熱膨張係数が近いMo板4にNi層3をクラ
ッドしたものが用いられ、このMo板をCu基板5とろう6
によって固着したのち、シリコン板1がNi層3の面とは
んだ2によってろう付けされる。しかしこのような電極
板は、Mo板4の側面がはんだで濡れないので、はんだ2
の厚さが厚くなり、内部に気泡ができやすくまた熱抵抗
が大きくなる。第3図に示す半導体素子においては、Mo
板4を予めCu基板5にろう6を用いて固着した複合電極
にまず電気Cuめっき層7が1〜2μmの厚さに被覆さ
れ、次いで2〜5μmの厚さの電気Niめっき層8,最後
にはんだ付け性改良のための無電解Niめっき層9が積層
されている。この場合はめっき作業を3回も繰り返さね
ばならず、常に一定の品質を保つには管理項目が多く、
時間を要する欠点がある。第4図では、Cuめっき層7の
上にセンダイジングアクチベート処理をして直接無電解
Niめっき層9が被覆されている。しかしこの方法では、
Niめっき層の付着力が低く、加熱処理を施さねばならな
いのではんだの濡れ性が損なわれる。The electrode plate inserted between the semiconductor substrate and the metal substrate has a thermal expansion coefficient close to that of the semiconductor substrate in order to prevent thermal stress from being applied to the semiconductor substrate, and to reduce the thermal resistance of the brazed portion with the semiconductor substrate. Good brazing properties of the surface are desired. As the electrode plate in the semiconductor element shown in FIG.
A silicon plate 1 having a thermal expansion coefficient close to that of a Mo plate 4 clad with a Ni layer 3 is used.
After being fixed by soldering, the silicon plate 1 is brazed to the surface of the Ni layer 3 by the solder 2. However, in such an electrode plate, since the side surface of the Mo plate 4 is not wet by the solder, the solder 2
Becomes thicker, air bubbles tend to form inside, and the thermal resistance increases. In the semiconductor device shown in FIG. 3, Mo
The composite electrode, in which the plate 4 is previously fixed to the Cu substrate 5 using the braze 6, is first coated with the electric Cu plating layer 7 to a thickness of 1 to 2 μm, and then the electric Ni plating layer 8 having a thickness of 2 to 5 μm, An electroless Ni plating layer 9 for improving the solderability is laminated on. In this case, the plating work must be repeated three times, and there are many control items to maintain constant quality.
It has the drawback of requiring time. In FIG. 4, the Cu plating layer 7 is directly electrolessly processed by the sendizing activator treatment.
The Ni plating layer 9 is covered. But this way,
Since the adhesion of the Ni plating layer is low and heat treatment must be applied, the wettability of the solder is impaired.
本発明は、上述の問題を解決して半導体基板と電極板と
の間の熱抵抗が小さく、しかも電極板の表面処理に多く
の時間を要しない半導体素子の製造方法を提供すること
を目的とする。An object of the present invention is to solve the above problems and to provide a method for manufacturing a semiconductor element in which the thermal resistance between a semiconductor substrate and an electrode plate is small, and moreover, the surface treatment of the electrode plate does not require a lot of time. To do.
本発明によれば、予め熱良導性の銅よりなる金属基板に
半導体材料に近い熱膨張係数を有するモリブデンのみか
らなるまたはタングステンのみからなる電極板を固着
し、該固着した電極板と金属基板とを無電解ニッケルめ
っき液中に浸漬し、該電極板と金属基板とを陰極として
6〜24V,0.5A以下の電流を長し、該電極板と金
属基板の表面をニッケル層によって被覆したのち、電極
板上に半導体基板の一面をはんだによってろう付けする
ことにより、めっき作業が1回で済み、電極板側面もNi
層で被覆されるのでろう付時に余分なはんだが含有ガス
と共に電極板側面に流れ出し、はんだ膜中の気泡がなく
なり、均一な薄いはんだ膜が生じて熱抵抗が低下するの
で上記の目的を達成することができる。According to the present invention, an electrode plate made of only molybdenum or tungsten having a coefficient of thermal expansion close to that of a semiconductor material is fixed to a metal substrate made of copper having good thermal conductivity in advance, and the fixed electrode plate and metal substrate are fixed. Was immersed in an electroless nickel plating solution, the electrode plate and the metal substrate were used as cathodes, and a current of 6 to 24 V, 0.5 A or less was lengthened to coat the surfaces of the electrode plate and the metal substrate with a nickel layer. After that, by soldering one surface of the semiconductor substrate onto the electrode plate with solder, the plating work is completed only once, and the side surface of the electrode plate is also Ni.
Since it is covered with a layer, excess solder flows out to the side surface of the electrode plate along with the contained gas at the time of brazing, air bubbles in the solder film disappear, a uniform thin solder film is formed, and the thermal resistance decreases, thus achieving the above object. be able to.
第1図は本発明の実施例により製造された半導体素子の
構造を示し、Mo板4とCu基板5からなる複合電極上にCu
めっきを施すことなく直接Ni層10が被覆されている。こ
のような複合電極にシリコン板1をろう付けする際に
は、はんだ2はMo板4の側面上のNi層10にも濡れるの
で、シリコン板1との間の接着のために必要な量以外の
はんだはMo板4の側面に流れ出し、均一で薄いはんだ膜
2が生じ、またはんだ中に含まれるガスも一緒に流れ出
るため気泡もなくなる。Mo板4およびCu基板5上の直接
のNiめっきは次の例のようにして形成することができ
る。 実施例1: 酸性無電解ニッケルりんめっき浴中に、複合電極4,5
を入れ、複合電極を陰極として6V,0.5Aの電流を流
し、5μmの厚さのNi−Pめっき膜を形成した。酸性Ni
−Pめっき浴の組成は次の通りである。 硫酸ニッケル 30g/ 次亜りん酸ナトリウム 10g/ 酢酸ナトリウム 10g/ pH 4〜6 温度 90℃ 実施例2: アルカリ性無電解Ni−Pめっき浴中に12V,0.3Aの電
流を流し、3μmの厚さのNi−Pめっき膜を複合電極
4,5上に形成した。めっき浴の組成は次の通りであ
る。 塩化ニッケル 45g/ 次亜りん酸ナトリウム 11g/ くえん酸ナトリウム 100g/ 塩化アンモニウム 50g/ pH 8.5〜9.5 温度 90〜100℃ 実施例3: 無電解ニッケルほう素浴中に24V,0.5Aの電流を流
し、2.5μmの厚さのNi−Bめっき膜を複合電極4,5
上に形成した。めっき浴の組成は次の通りである。 硫酸ニッケル 20g/ 酒石酸カリウムナトリウム 40g/ 水素化ほう素酸ナトリウム 2.3g/ pH 12.5 温度 40〜50℃ 比較のため、比較例1〜3の半導体素子を試料として作
成した。 比較例1: 第2図に示したように1〜2μmのNi層3,クラッドし
たMo板4を打抜き、Cu基板5を接着した複合電極上にSi
板1をろう付けした。 比較例2: 第3図に したようにMo板4,Cu基板5からなる複合電
極上に電気Cuめっき層7を1〜2μmの厚さに形成し、
次いで電気Niめっき層8を1〜2μm,無電解Niめっき
層9を5〜8μmの厚さに積層した上にSi板1をろう付
けした。電気Cuめっき浴の組成は次の通りである。 シアン化銅 65〜90g/ シアン化ナトリウム 80〜155g/ ロッカル塩 40〜70g/ ロダンナトリウム 10〜15g/ pH 10.5〜11.0 温度 50〜70℃ 電流密度 1〜3A/dm2 電気Niめっき浴の組成は次の通りである。 硫酸ニッケル 240g/ 塩化ニッケル 45g/ ほう酸 30g/ pH 4.0〜5.5 温度 40〜55℃ 電流密度 1〜6A/dm2 無電解Niめっき浴の組成は次の通りである。 塩化ニッケル 10g/ 次亜りん酸ナトリウム 24g/ こはく酸ナトリウム 16g/ りんご酸 18g/ pH 5.6 温度 100℃ 比較例3: 第4図に示した構成であるが、Cu基板4とMo板5に代わ
ってW板からなる複合電極に比較例2の場合と同様な条
件で1〜2μmの厚さの電気Cuめっき層7,5μmの
厚さの無電解ニッケル層9を形成した上にシリコン板1
をろう付けした。 実施例1〜3および比較例1〜3によって作成された半
導体素子の熱抵抗評価および電極製作原価の比較を第1
表に示す。熱抵抗値は電流10A通電に必要な電圧値で表
わす。 第1表からわかるように、本発明による素子においては
シリコン板1とCu基板5との間の熱抵抗が大幅に改善
し、さらに製造原価も電極製作において大幅に低減され
ている。 なお、実施例で述べたMo電極板の代わりにW電極板を用
いたときも同様の効果が得られた。FIG. 1 shows the structure of a semiconductor device manufactured according to an embodiment of the present invention, in which Cu is formed on a composite electrode composed of a Mo plate 4 and a Cu substrate 5.
The Ni layer 10 is directly coated without plating. When the silicon plate 1 is brazed to such a composite electrode, the solder 2 also wets the Ni layer 10 on the side surface of the Mo plate 4, so the amount other than the amount necessary for adhesion with the silicon plate 1 is excluded. Of the solder flows out to the side surface of the Mo plate 4 to form a uniform and thin solder film 2, or the gas contained in the solder flows out together, so that the bubbles disappear. Direct Ni plating on the Mo plate 4 and the Cu substrate 5 can be formed as in the following example. Example 1: Composite electrodes 4,5 in an acidic electroless nickel-phosphorus plating bath
Then, a composite electrode was used as a cathode, and a current of 6 V and 0.5 A was applied to form a Ni-P plating film having a thickness of 5 μm. Acidic Ni
The composition of the -P plating bath is as follows. Nickel sulfate 30 g / sodium hypophosphite 10 g / sodium acetate 10 g / pH 4-6 temperature 90 ° C. Example 2: A current of 12 V, 0.3 A was applied to an alkaline electroless Ni-P plating bath to give a thickness of 3 μm. A Ni-P plating film was formed on the composite electrodes 4 and 5. The composition of the plating bath is as follows. Nickel chloride 45 g / sodium hypophosphite 11 g / sodium citrate 100 g / ammonium chloride 50 g / pH 8.5 to 9.5 temperature 90 to 100 ° C. Example 3: An electric current of 24 V and 0.5 A is applied to an electroless nickel boron bath, Ni-B plating film with a thickness of 2.5 μm is used for composite electrodes 4, 5
Formed on. The composition of the plating bath is as follows. Nickel sulfate 20 g / potassium sodium tartrate 40 g / sodium borohydride 2.3 g / pH 12.5 temperature 40 to 50 ° C. For comparison, semiconductor devices of Comparative Examples 1 to 3 were prepared as samples. Comparative Example 1: As shown in FIG. 2, a Ni layer 3 having a thickness of 1 to 2 μm 3, a clad Mo plate 4 were punched out, and a Cu substrate 5 was adhered to the composite electrode to bond Si.
Plate 1 was brazed. Comparative Example 2: As shown in FIG. 3, an electric Cu plating layer 7 having a thickness of 1 to 2 μm was formed on a composite electrode composed of a Mo plate 4 and a Cu substrate 5.
Then, the electric Ni plating layer 8 was laminated to a thickness of 1 to 2 μm, and the electroless Ni plating layer 9 was laminated to a thickness of 5 to 8 μm, and the Si plate 1 was brazed. The composition of the electric Cu plating bath is as follows. Copper cyanide 65-90g / Sodium cyanide 80-155g / Roccal salt 40-70g / Rhodan sodium 10-15g / pH 10.5-11.0 Temperature 50-70 ° C Current density 1-3A / dm 2 The composition of electric Ni plating bath is It is as follows. Nickel sulfate 240 g / nickel chloride 45 g / boric acid 30 g / pH 4.0 to 5.5 Temperature 40 to 55 ° C. Current density 1 to 6 A / dm 2 The composition of the electroless Ni plating bath is as follows. Nickel chloride 10 g / sodium hypophosphite 24 g / sodium succinate 16 g / malic acid 18 g / pH 5.6 Temperature 100 ° C. Comparative Example 3: The structure shown in FIG. 4 is used, but the Cu substrate 4 and the Mo plate 5 are replaced. Under the same conditions as in Comparative Example 2, an electric Cu plating layer 7 having a thickness of 1 to 2 μm and an electroless nickel layer 9 having a thickness of 5 μm were formed on the composite electrode made of a W plate, and then the silicon plate 1 was formed.
Brazed First, the thermal resistance evaluation and the electrode manufacturing cost comparison of the semiconductor devices prepared in Examples 1 to 3 and Comparative Examples 1 to 3 are compared.
Shown in the table. The thermal resistance value is expressed as the voltage value required to pass a current of 10A. As can be seen from Table 1, in the device according to the present invention, the thermal resistance between the silicon plate 1 and the Cu substrate 5 is significantly improved, and the manufacturing cost is also significantly reduced in the electrode manufacturing. Similar effects were obtained when a W electrode plate was used instead of the Mo electrode plate described in the examples.
本発明は、半導体基板とろう付けされる電極板及び金属
基板の表面を、無電解ニッケルめっき浴に電流を通電す
ることによってCuめっき層を介しないで直接付着性のよ
いNi層によって側面まで被覆するもので、めっき作業が
1回で済み、電極板の表面処理に多くの時間を要するこ
とがない、また半導体基板ろう付け時に余分のはんだお
よびはんだ中のガスが電極板側面のNi層に引張られるた
め、半導体基板と電極板の間には薄く、均一で健全なは
んだ膜が介在することになり、熱抵抗が低下し、信頼性
の高い半導体素子を低い原価で製造することが可能にな
る。The present invention covers the surfaces of an electrode plate and a metal substrate to be brazed with a semiconductor substrate to a side surface by a Ni layer having good adhesion directly without passing through a Cu plating layer by passing a current through an electroless nickel plating bath. It does not require much time for the surface treatment of the electrode plate because the plating work is done only once, and extra solder and the gas in the solder are pulled to the Ni layer on the side surface of the electrode plate when brazing the semiconductor substrate. Therefore, a thin, uniform and sound solder film is interposed between the semiconductor substrate and the electrode plate, the thermal resistance is lowered, and a highly reliable semiconductor element can be manufactured at a low cost.
第1図は本発明の一実施例の半導体素子の要部断面図、
第2図は比較例1の素子の要部断面図、第3図は比較例
2の素子の要部断面図、第4図は比較例3と同様な素子
の要部断面図である。 1:シリコン板、2:はんだ、4:Mo板、5:Cu基板、
10:Niめっき層。FIG. 1 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention,
2 is a cross-sectional view of an essential part of an element of Comparative Example 1, FIG. 3 is a cross-sectional view of an essential part of an element of Comparative Example 2, and FIG. 4 is a cross-sectional view of an essential part of an element similar to Comparative Example 3. 1: Silicon plate, 2: Solder, 4: Mo plate, 5: Cu substrate,
10: Ni plating layer.
Claims (1)
体材料に近い熱膨張係数を有するモリブデンのみからな
るまたはタングステンのみからなる電極板を固着し、該
固着した電極板と金属基板とを無電解ニッケルめっき液
中に浸漬し、該電極板と金属基板とを陰極として6〜2
4V,0.5A以下の電流を流し、外電極板と金属基板
の表面をニッケル層によって被覆したのち、電極板上に
半導体基板の一面をはんだによってろう付けすることを
特徴とする半導体素子の製造方法。1. An electrode plate made of only molybdenum or tungsten having a coefficient of thermal expansion close to that of a semiconductor material is fixed to a metal substrate made of copper having good thermal conductivity in advance, and the fixed electrode plate and the metal substrate are bonded together. Is immersed in an electroless nickel plating solution, and the electrode plate and the metal substrate are used as a cathode for 6 to 2
Manufacturing a semiconductor device characterized in that a current of 4 V or less and 0.5 A or less is applied, the surfaces of the outer electrode plate and the metal substrate are covered with a nickel layer, and then one surface of the semiconductor substrate is brazed onto the electrode plate by soldering. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61024797A JPH0620083B2 (en) | 1986-02-06 | 1986-02-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61024797A JPH0620083B2 (en) | 1986-02-06 | 1986-02-06 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62183132A JPS62183132A (en) | 1987-08-11 |
JPH0620083B2 true JPH0620083B2 (en) | 1994-03-16 |
Family
ID=12148179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61024797A Expired - Lifetime JPH0620083B2 (en) | 1986-02-06 | 1986-02-06 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0620083B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2609252C (en) | 2005-05-23 | 2012-01-10 | Neomax Materials Co., Ltd. | Cu-mo substrate and method for producing same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5199473A (en) * | 1975-02-28 | 1976-09-02 | Hitachi Ltd | RIIDOFUREEMU |
JPS6033312B2 (en) * | 1979-02-15 | 1985-08-02 | 株式会社東芝 | semiconductor equipment |
JPS58157957A (en) * | 1982-03-16 | 1983-09-20 | Suzuki Motor Co Ltd | Plating method of nickel |
-
1986
- 1986-02-06 JP JP61024797A patent/JPH0620083B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS62183132A (en) | 1987-08-11 |
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