JPS6027988B2 - keyboard instrument performance practice device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a keyboard instrument training device that divides a played practice piece into ranges and allows performance practice results to be evaluated within each of the divided ranges.

To practice playing a keyboard instrument, a student operates the keyboard based on a musical score containing an etude, and repeatedly practices so as to reproduce the music expressed in the musical score as faithfully as possible.

The teacher who instructs this keyboard performance listens to the music played by the student, points out the weak parts, and teaches concretely through model performances, etc., and evaluates the student's performance based on the teacher's subjective opinion. It is something to do. However, this type of performance training is very effective in private lessons where the teacher and student are in a one-on-one situation, but when there are multiple students to one teacher, In the case of group lessons, the teacher does not give sufficient guidance to each student,
This makes it difficult for teachers to appropriately judge each student's performance status and provide guidance. This invention has been developed in view of the above points, and it not only makes it possible to judge the state of each student's practice performance appropriately and objectively, but also
To provide a keyboard instrument practice device which can discriminate and evaluate the performance practice state of each part of one practice piece and facilitates more effective and objective instruction.

That is, the practice device according to the present invention compares the model performance information with the performance information from the practice keyboard, performs scoring and evaluation based on the correctly pressed key discrimination information at each specified timing,
In addition to storing settings, the stored scoring results for each timing are displayed. An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows its configuration. The model performance information is obtained from the teacher's keyboard 11 set in the parent device of the group performance training device or from the storage device 12. Accompanying the operation, performance information corresponding to the operation key is retrieved. Also, the storage device 12
In this storage device 1, the information of each note expressing the performance song is set and written in sequential address.
2 is configured to sequentially read out the performance information by a readout control section 14 driven by the readout information and the tempo signal from the tempo oscillator 13.
Then, this read performance information is stored in the UK latch storage unit 1.
5, the information from the keyboard 11 is selectively used as model performance information. in this case,
The performance information stored in the storage device 12 consists of pitch (UK) information and note length information, which will be described in detail later, and is controlled to be read out from the storage device 12 at time intervals corresponding to the note length information. (UK) information is latched and stored in the latch storage section 15. Here, the information written to the storage device 12 is recorded in the magnetic storage section 16a set in the corresponding musical score 16 as appropriate, and for example, the reading device 17 provided corresponding to the music stand on which this musical score 16 is set. The recorded information is read and written to the storage device 12 for storage. Performance information obtained in response to performance operations on the keyboard 11 is transmitted to the master musical tone forming circuit 1.
8 to form a musical tone signal, which is appropriately amplified by an amplifier 19 and supplied to two speakers.
Make it possible to obtain sample performance sounds by the teacher.

The model performance information obtained from the teacher's keyboard 11 or the UK latch storage section 15 is taken out via the gate circuit 21 and supplied to the musical tone forming circuit 22, which forms a musical tone signal based on the model performance information. The level of the signal is appropriately controlled using a tone volume or the like, and the signal is coupled to a sound system 23 including a speaker.

By opening the gate of the gate circuit 21 with the switch 21a, the model performance sound can be heard.The model performance sound obtained from this sound system 23 is sufficient for students to listen to for reference. Preferably at a small level. In addition, the above model performance information is
The signal is supplied to the correctly pressed key determination circuit 24.

This discrimination circuit 24 includes a keyboard 2 operated by a student for practice.
Performance information corresponding to the key operations from step 5 is also supplied, and this performance information is compared with the above model performance information, and based on the match, the correct key press is determined, and the results of the determination are accumulated as appropriate and scored. The circuit 26 performs scoring and evaluation. The scoring results of the scoring circuit 26 are stored in the scoring memory circuit 27, and the stored information is displayed on the display 28.
In this case, the scoring circuit 26 and the memory circuit 27 are supplied with a specific number of timing signals for each measure from an automatic rhythm generator 29, which will be described later, and are scored for each timing signal and sequentially set addresses. The score is written and set in the memory circuit 27, and the display 28 is configured to display the scoring results at each timing. The automatic rhythm generator 29 includes a counter 29a that generates multi-bit binary count value information for counting a tempo clock signal obtained by dividing the oscillation signal from the tempo oscillator 13 by a frequency dividing circuit 30. The specified bar unit signal is extracted and used as a timing signal for the scoring circuit 26 and storage device 27.

The bit information of the binary count value of the counter 29a is as follows:
The bit information is supplied to the rhythm pattern memory 29b, and this bit information is combined to form rhythm pattern signals corresponding to various rhythms.

The rhythm pattern memory 29b outputs a rhythm pattern signal of the rhythm type selected by the rhythm selector 29c, drives the rhythm sound source 29d, and generates an automatic rhythm sound source signal. This automatic rhythm sound source signal is sent to the sound system 23 via the tone volume as appropriate.
and is produced as an automatic rhythm player. Here, the counter 29a is given a start signal from the readout control section 14, and activated in response to a start command for reading performance information from the storage device 12, so that automatic rhythm performance is started. Although not shown in the figure, if the model performance information is retrieved from the teacher's keyboard 11 and the information is not read from the storage device 12, a start command can be given to the automatic rhythm generator 21 using another switch means. Bye. Performance information associated with key operations on the practice keyboard 25 is further supplied to a musical tone forming circuit 31 to generate a musical tone signal, and this musical tone signal is also supplied to the sound system 23, so that the student can listen to his or her own performer. Make it audible. FIG. 2 shows in detail the readout control section 14 of model performance information related to the above-mentioned counterfeit device, especially the storage device 12. Memory information is read out in response to address information from 14a.

Here, the information stored in the storage device 12 is, as described above, note information consisting of a combination of pitch (UK) information and note length information, which is stored and set by address setting in note order. , the format of the stored information is, for example, as shown in FIG. 3, UK information, note length information, UK information,
The note length information is stored and set in this order.

In this case, phrase mark information is set to be inserted for each specific bar as necessary, and a FINISH code is inserted when the full note length information is complete. The UK information, note length information, phrase mark, and end code stored in the storage device 12 are each composed of, for example, 8-bit information as shown in A to D in FIG. 4, and the first two bits are It should be used as a UK mark, note length mark, etc. In the case of UK information, the remaining 6 bits represent a key code indicating the pitch, and in the case of note length information, the remaining 6 bits constitute numerical information indicating the note length. In addition, U
In the case of K information, it is generated in response to a rest as well as a musical note, and the key code for a rest is expressed as all "0".

In addition, as shown in Figures C and D, the phrase mark and end code are expressed by the same mark "11", but the remaining 6 bits are all "0" or all "0".
This is determined by expressing it as ``1''.

That is, from the storage device 12, the address counter 14a
In response to the address designation, the stored information shown in the format of FIG.

The storage unit 15 includes a latch circuit 15a and a UK mark detection circuit 15b that detects the UK mark from read information, and a detection signal from the UK mark detection circuit 15b gives a latch storage command to the latch circuit 15a. That is, when the UK information is read from the storage device 12, pitch information corresponding to the key code is latched and stored in the latch circuit 15a. In addition, storage device 1
The read information from V2 is also provided to the latch circuit 14b, note length mark detection circuit 14c, and end code detection circuit 14d.
When the note length information is read out from the storage device 12,
The output of the note length mark detection circuit 14c causes the latch circuit 14b to latch and store the note length information.

Then, an end signal is generated from the end code detection circuit 14d in response to reading of the end code detection signal. The memory code length information of the latch circuit 14b is stored in the comparison circuit 1
At step 4e, the counted value of the note length counter 14f is compared.

The note length counter 14f is driven by the tempo clock signal from the tempo oscillator 13 described above, and IJ is set by the detection signal from the note length mark detection circuit 14c every time the note length information is read. That is, note length counter 14
f counts the tempo clock signal from the time the note length information is read out, and when the time corresponding to the note length stored in the latch circuit 14b has elapsed, the equal signal EQ is generated from the comparison circuit 14e. . This comparison circuit 14
The equal signal generated at e is detected by a differentiating circuit 14g and sent to the flip-flop circuit 1 via an OR circuit 14h.
Give a set command to 4i. When set, this flip-flop circuit 14i gives a gate signal to the AND circuit 14i, takes out the system clock ◇, and supplies it to the address counter 14a as an address increment command. The flip-flop circuit 14i is reset by a detection signal from the note length mark detection circuit 14c. Further, this device is provided with a start switch 14k.

This switch 14k is configured to be a self-resetting type, and when operated, generates a signal 11 and takes out a start signal STRT from the differentiating circuit 141. This signal STRT is used as an initial setting signal as appropriate. , the OR circuit 14h' is supplied, and the OR circuit 14m is supplied.
A reset command is given to the address counter 14a via the address counter 14a, and the flip-flop circuit 14n is also reset.
This flip-flop circuit 14n is set by a signal from the end code detection circuit 14d, and when it is set, it gives a signal to the OR circuit 14m and outputs a signal to the address counter 1.
4a is reset and held, and a start operation command is given to the automatic rhythm generator 29 in the reset state. That is, when the start switch 14k is operated to issue a start command, the address counter 14a is reset and confirmed, the flip-flop circuit 14n is reset, and the automatic rhythm generator 29 is started.

At the same time, the flip-flop circuit 1 is connected via the OR circuit 14n.
4i is set, and a gate signal is given to the AND circuit 14j to increment the address counter 14a and read the stored information from the storage device 12 from the first address. That is, the first UK information is first read out from the storage device 12, latched into the latch circuit 15a, and the stored information is used as pitch information of the model performance information. Then, as the address counter 4a increments, the storage device 1
When the next note length information is read from 2, the latch circuit 14b responds to the detection signal from the note length mark detection circuit 14c.
The note length information is latched and stored in the note length counter 4f.
The flip-flop circuit 14i is reset, the gate of the AND circuit 14j is closed, and the address counter 14
Stop the progress of a.

The note length counter 4f starts counting tempo clock signals from the time when the note length mark is detected, and when a time period corresponding to the note length information stored in the latch circuit 14b has elapsed since the start of counting, the note length counter 4f starts counting the tempo clock signal from the comparison circuit 14e. - a signal EQ is generated.

That is, from the differentiating circuit 14g to the flip-flop circuit 1
4i is given a set command, the gate of AND circuit 14j is opened, address counter 14a is incremented again, and the subsequent UK information is read from storage device 12. That is, the UK information is read out from the storage device 12 at time intervals corresponding to each corresponding note length information, stored in the latch circuit 15a, and taken out as UK information for model performance. , all information is read out,
When the end code is finally read out, the flip-flop circuit 14n is set by the output signal of the end code detection circuit 14d, and the end is controlled.

FIG. 5 shows the configuration of the scoring evaluation section when the read information from the storage device 12 is used as model performance information. The output signal from the mark detection circuit 15b is converted into a pulse signal by a one-shot circuit 35, taken out via a delay circuit 36 consisting of a delayed flip-flop driven by a clock TCL, and used as a signal AΔ1.

Further, the OR circuit 37 detects that the input UK information is not all "0", that is, it corresponds to a musical note, and the output signal from the OR circuit 37 is the output signal from the UK mark detection circuit 15b. AND circuit 38
supply to. That is, an output signal is obtained from this AND circuit 38 every time UK information corresponding to a note other than a rest mark is read, and this signal is converted into a pulse signal by a one-shot circuit 39, and a delay pulse signal driven by a clock TCL is obtained. The signal is taken out via the circuit 40 as a signal AΔ2. That is, if the UK information shown by musical notes and rest marks in FIG.
A signal A△1 is generated in response to the information, and a signal A△2 is generated in response to only the note.When expressed by key operations corresponding to a model performance, the signal A△2 corresponds to a key press, and the signal A△ 1 is the first key-off and key-on signal corresponding to the scale key.

The signal AΔ2, which is the first key-on signal, is counted by a first counter 26a forming the scoring circuit 26. Performance information associated with performance operations on the keyboard 25 is supplied to the comparison circuit 41 as comparison information A, and is also supplied to the comparison circuit 41 as information B via the delay circuit 42.

Therefore, when a new key is pressed on the keyboard 25 or a previously pressed key is released and the performance information changes,
The comparison circuit 41 outputs this “A sheep B” state.
≠B”, an output signal is generated. This comparison circuit 41
The output signal from the key-off signal MΔ1 corresponds to the signal AΔ1. Furthermore, the OR circuit 43 detects that the performance information is associated with a key press, and the output signal from the OR circuit 43 is supplied to the AND circuit 44 together with the output signal from the comparison circuit 41. therefore,
The AND circuit 44 generates a second key-on signal MΔ2 corresponding to the signal AΔ2. therefore,
Assuming that accurate key operations are performed on the keyboard 25 that match the model performance information, the signals M△1 and M△2 are synchronized with the signals A△1 and A△2 as shown in FIG. generated.

The UK information stored in the latch circuit 19 is compared in pitch with performance information associated with key depression operations on the keyboard 25 in a comparison circuit 45 . Therefore, when the correct* key of the pitch corresponding to the UK information is operated on the keyboard 25, an equal signal EQ is obtained from the comparison circuit 45, and this signal is sent to the flip-flop circuit via the delay circuit 46 driven by the clock TCL. Set 47. The flip-flop circuit 47 is reset with the signal AΔ1 before the output from the delay circuit 46 is generated, and the flip-flop circuit 47 is set and inverted every time the correct pitch key is operated. The set power signal of the flip-flop circuit 47 is supplied to the latch circuit 49 via the delay circuit 48, and the correct pitch key press is latched and stored in response to the generation of the next signal A△1. let Signals AΔ2 and AAI corresponding to the model performance information are supplied to shift registers 50 and 51, respectively, which are driven by the clock TCL.

The shift register 50 consists of 4-bit digits, one of which is
Take out the signal from the bit and send it to the flip-flop circuit 5
Set 2. Further, the signal from the output end of the shift register 50 is sent to the OR circuit 53 along with the start signal STRT.
The flip-flop circuit 52 is reset by the output of the OR circuit 53. Therefore, the flip-flop circuit 52 is set with a delay of clocks TCLI from the rising edge of the signal A△2, and
The set current force signal is a signal having a time width corresponding to the signal AΔ2, as shown by FI in FIG. 6. Further, the shift register 51 is composed of 3 bits, and a signal is taken out from its input terminal, and the flip-flop circuit is set with this signal, and the signal from the output terminal of the shift register 51 is sent to an OR circuit 55 together with a start signal STRT. supply,
The flip-flop circuit 54 is reset by the output signal from the OR circuit 55.

That is, the flip-flop circuit 54 is set for three clocks TCL from the rising edge of the signal AΔ1, and the output signal at the time of setting corresponds to the signal AAI, as shown by F2 in FIG. It is considered to be a signal with a time width. Signals M△1 and M△2 corresponding to key press operations on the keyboard 25 are differentiated by differentiating circuits 56 and 57 controlled by a clock 4TCL having a frequency four times that of the clock TCL, and the differentiated pulses are respectively sent to a shift register 58. ,59
Comprehensive information.

The shift registers 58 and 59 are connected to the clock 4, respectively.
Driven by TCL, configured into 8-bit digits and 10-bit digits, and receives signals KOFF and KON from its output terminals, respectively.
Output. That is, the signals KOFF and KON
As shown in FIG. 6, the signals MΔ1 and MA2 are delayed from the rising edge of the signals MΔ1 and MA2 by a period corresponding to the transmission time of the shift registers 58 and 59, respectively. The output signal KON from the shift register 59 is transmitted to the flip-flop circuit 52.
It is supplied to the AND circuit 60 together with the output signal FI from.

Therefore, when the signal KON corresponding to the depression of the key on the keyboard 25 is generated from the AND circuit 60 during the signal FI having the time width corresponding to the signal A△2, the AN in FIG.
An output signal is generated as shown by D, and the flip-flop circuit 61 is set. This flip-flop circuit 61
is reset by the output of the OR circuit 62 which is supplied with the output signal from the delay circuit 62 which is supplied with the signal KOFF, and the key press timing of the keyboard 25 is a signal based on the signal A△2 based on the model performance information. The flip-flop circuit 61 is set when the signal F2 matches within the allowable range determined by the signal F2. The output signal at the time of setting is F3 in Fig. 6.
It is generated as shown in . A start signal STRT is coupled to the OR circuit 63. flip-flop circuit 6
The set output signal F3 from 1 is supplied to the AND circuit 64 as a gate signal.
Further, the set output signal F2 of the flip-flop circuit 54 and the output signal KOFF from the shift register 69 are supplied. That is, the signal FI corresponding to a key-off with a time interval set by the signal A△1 and the signal KOFF corresponding to a key on the keyboard 25 are compared within the allowable range determined by the signal FI. 6, and under the conditions that the key timing of the keyboard 25 matches the signal FI, the AND circuit 64 generates an output signal shown by LR in FIG. That is, when the keyboard 25 is pressed or released within the allowable time range set in the shift registers 50 and 51 for the note length of the model performance information, the AND circuit is activated. The world power signal LR is generated from 64.

The note length correct signal from the AND circuit 64 is supplied to the AND circuit 65 together with the pitch correct signal from the latch circuit 49, and the AND circuit 65 is supplied with the correct note length signal from the AND circuit 64.
A correct key press signal is generated from 5, and the counter 26b is counted. That is, based on the model performance information, the first counter 26a constituting the scoring circuit 26 calculates the number of pressed keys.
The number of correct key presses is counted by the counter 26b, and by calculating both counts in the arithmetic circuit 26c, the number of correct key presses is obtained.

The calculation by the calculation circuit 26c may be performed by, for example, performing division using the count value of the first counter 26a as a parameter to calculate the Masato rate.
Subtract the count value of the second counter 26b from the count value of a,
The number of erroneous key presses may be calculated directly. In this case, the counters 26a and 26b are given reset commands from the OR circuits 26d and 26e, which are supplied with appropriate measure-by-measure timing signals obtained from the counter 29a of the automatic rhythm generator 29 via the delay circuit 66. It will be done. That is, the counters 26a and 26b perform a counting operation for each appropriately divided phrase unit, and the calculation circuit 26c performs a scoring operation for each phrase unit. A start signal STRT is also supplied with V to the OR circuits 26d and 26e. Scoring information from the calculation circuit 26c that performs scoring calculation for each phrase is supplied to the scoring storage circuit 27.

This memory circuit 27 is constituted of, for example, a RAM, and is addressed by an address counter 67, which is incremented by the timing signal supplied via an OR circuit 68. This timing signal is also supplied to the storage circuit 27 as a write command, and therefore, the scoring results for each phrase calculated by the calculation circuit 26c are sequentially written and stored in the storage circuit 27 by specifying addresses. Become so. Here, the address counter 67 is reset by the output of the OR circuit 70 which is combined with the signal from the reset switch 69 and the start signal STRT.
A signal corresponding to the operation is supplied to the OR circuit 68 so that the address counter 67 can be incremented as appropriate.

That is, there is no timing pulse and the memory circuit 27
By placing the information in the reading state and operating the switch 71, the stored information in the memory circuit 27 is sequentially read out, and the display 28 comes to be displayed. On this display 28, by operating the step switch 71 as described above, the scoring results for each phrase are displayed sequentially, and even in the progress of performance practice, between timing pulses, the score of the previous phrase is displayed. The scoring results are read out from the storage circuit 27 and displayed. In this case, indicator 2
8, a display command is appropriately given by a switch 28a.

That is, according to the device configured in this way, the keyboard 2
In the performance practice process according to 5, the practice status is scored in phrase units that are appropriately divided, and is memorized and displayed in phrase units, and it is possible to analyze, score, and check which parts of the performance song are particularly bad. can do.

Therefore, it is possible to effectively instruct and instruct the content of subsequent keyboard performance practice. In the above-mentioned embodiment, an automatic rhythm generator is used in combination, and the practice piece is divided into phrases based on timing signals from the automatic rhythm generator in units of bars.

However, as shown in Figure 3, in the model performance information,
When a phrase mark is set to be inserted as appropriate, a phrase mark detection circuit 32 is provided as shown by the broken line in FIG. 2, and the phrase detection signal from this detection circuit 32 is sent to the scoring circuit 26.
, may be used as a timing signal for the storage circuit 27 section. Furthermore, in the embodiments of FIGS. 2 and 5,
This shows a case where the model performance information is composed of information read from the storage device 12, but the teacher's keyboard 11
It can be implemented in the same way even when using information from .

However, in this case, it is necessary to form the signals A△1 and A△2 in response to key operations on the keyboard 11;
This forming means is shown in FIG. 5 as a comparison circuit 41, a delay circuit 42,
Signal M△1,M consisting of AND circuit 44, OR circuit 48, etc.
It is sufficient to use the same means as the forming means of Δ2.

As described above, according to the present invention, a student practices keyboard performance in accordance with model performance information, and during the practice process, the key operation state is scored and stored for each appropriately divided phrase unit. It is.

Therefore, for example, it is possible to effectively analyze and check the performance status through the practice piece after the performance has finished.
This allows students to more effectively instruct and instruct students to practice areas they are weak in, and is highly effective in improving the effectiveness of practice.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a configuration diagram illustrating a practice device according to an embodiment of the present invention, FIG. 2 is a diagram showing a portion related to the storage device of the device, and FIG. A diagram showing the format of stored performance information, A to D in FIG. 4 are diagrams each explaining the state of the stored information, and FIG. 5 explains a scoring evaluation section based on information read from the storage device. Configuration diagram, No. 6
The figure is a signal waveform diagram illustrating FIG. 5. 11...Teacher's keyboard, 12...Storage device, 14...Readout control unit, 1 5...UK latch storage unit, 23...Sound system, 24...・
... Correctly pressed key discrimination circuit, 25 ... Keyboard (for practice), 26 ... Scoring circuit, 27 ... Scoring memory circuit, 28 ... Display unit , 29... automatic rhythm generator. Figure 1 Figure N Boat Figure 3 Figure 4 Mountain boat Figure 6

Claims (1)

[Scope of Claims] 1. A model performance information source that sequentially generates performance information at note length intervals, a keyboard for practice playing, performance information corresponding to key operations on this keyboard, and performance information from the model performance information source. a discrimination circuit that discriminates the correct key press by comparison; a scoring circuit that scores the discrimination results of the discrimination circuit at each specified timing;
A keyboard instrument practice device comprising: a scoring storage circuit that stores the scoring results of the scoring circuit at each of the timings described above; and a display that displays the stored scoring information of the scoring storage circuit. 2. The device according to claim 1, wherein the model performance information source is a teacher's keyboard, and the operated key performance information is generated in accordance with key operations on the keyboard. 3. The above-mentioned model performance information source is composed of a storage device that stores note information consisting of a combination of performance information and note length information with addresses set in the order of notes, and is configured to read and control each performance information at note length intervals. The device according to claim 1. 4. The device according to claim 1, wherein the specific timing for scoring is constituted by a signal for each specific bar from an automatic rhythm generator. 5. The apparatus according to claim 3, wherein a phrase mark is set for each specified section of the stored musical note information, and the specific timing for scoring is set in response to reading of the phrase mark.