JPS6027037A - Program tracing system - Google Patents

Abstract

PURPOSE:To perform program tracing with high accuracy with no increment of memory capacity by having the fine program tracing in an address space to be noticed and the rough program tracing in other address spaces. CONSTITUTION:A detecting circuit DET1 detects the instruction fetch which gives access to a memory Memo by an access-based signal given from a CPU and delivers a signal (a) for each access of the instruction fetch. The rises of the signal (a) are counted by a counter circuit COUNTER, and a fixed time signal (c) is delivered every three counts for example. While a detecting circuit DET2 monitors the address information and delivers a signal (b) with a space to be noticed. Thus the fine tracing is carried out in the space to be noticed; while the rough tracing is given in other address spaces. In such a way, the program tracing is possible with high accuracy and with no increment of memory capacity.

Description

Detailed Description of the Invention (a) 9 Technical Fields of the Invention The present invention relates to a program trace method, and in particular to the Progera J...1-lace which can perform coarse-grained tracing and fine-grained 1-lace at the same time. It is related to the method.

(b) Problems with the Prior Art A program trace device is a device that records the running status of a created program to facilitate program debugging.

FIG. 1 is a block diagram showing an embodiment of a conventional program tracing device.

In the figure, CPU is a central processing unit, MEMO is a storage device, and T
RACE is a program tracer.

Program with the above configuration ・1-The race device has the following information from the access type signal sent by the central processing unit CPLI.
．． A method of extracting an instruction fetch that accesses the 0 device MEMO, and inputting and recording its address to a program trace device TRA CL': for each instruction fetch;
There is a method in which the address of the instruction fetch is input to the ACE using the program l race device 'r+ and recorded at every fixed period.

In the former case, the status of the address in the instruction running state can be determined in detail, but it has the drawback of increasing the storage capacity, and in the case of 1 & 2, the address of the instruction fetch is checked at regular intervals, so it is difficult to trace. The grain of the wood is coarse, so there is a risk that the necessary emotion (・I) may be missing.

(C)9 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art;
By monitoring the address space that consists of the program, executing a detailed program trace within that space, and performing a rough program trace outside that space,
Highly accurate programs and programs without increasing storage capacity
The purpose is to provide a method that allows tracing to be performed every time.

(d) 1 Configuration of the Invention"--According to the present invention, the object described in 1. is a central processing unit.
Connect to the data processing system consisting of α equipment,
a first detection circuit for detecting instruction fetch accesses in a device that receives a number of accesses to the storage device from the central processing unit and performs a program trace; a first detection circuit for detecting instruction fetch accesses; a counter circuit that sends an output signal when the count value reaches a certain value, and a second detection circuit that monitors address information of the instruction fetch and detects the instruction fetch to predetermined address information. , and storing the address information of the instruction fetch 1. a circuit, the instruction fetch outside the address space stores address information in the storage circuit by the output of the counting circuit, and the instruction fetch within the address space stores address information for each instruction fetch in the storage circuit. This is achieved by providing a program-one-race method that is characterized by being stored in a circuit.

(e) 1 Embodiment of the Invention The present invention separates the address space into an address space that should be focused on in a program/trace operation and an address space that does not need to be focused on. In this case, each Q instruction 4U instruction fetch/
address f? f Plf is loose, and in the case of address spaces other than that, instruction fetches are thinned out at regular intervals. be.

FIG. 1 is a diagram 11172 which does not show one embodiment of the present invention.

In the figure, DETl is the detection circuit 1DIF, and T2 is the detection circuit ■
, COU N TE R is a counting circuit, Mt>mo L is a memory circuit 1. G1, G2 are people Anne 1: Game 1, G3
is or game l-.

Figure 3 is time chart 1 to explain the operation of Figure 2.
− is.

(1) in FIG. 3 shows the output (aυa) of the detection circuit IDETI.

(2) in Fig. 3 shows the output signal for the counting circuit COU N i''I.
TE R is the output signal C when counting the output signal a three times.
issue.

(3) in FIG. 3 shows the output of the detection circuit II I)E'F2 (t"+";'b is not shown).

(4) in FIG. 3 shows the write signal d.

The iIl shelf of the present invention will be explained below according to the drawings.

The detection circuit IDETI detects an instruction fetch that accesses the memory device MEMO from the access type signal from the central processing unit CPU, and outputs a signal l+a when the instruction FENOCI accesses.

The counting circuit COUNTER counts the rising edge of the signal a, and when a certain number is counted (three times in (2) of FIG. 3), it outputs the signal C for a certain period of time. As a result, the AND gate 1-GL outputs the write signal d via the OR gate G3 under the AND condition of the input/death a and the signal C, and stores and writes the address information into the memory circuit Memo.

On the other hand, the detection circuit 11DET2 monitors the address information, and outputs a signal if it is within the address space where the address Irf information is generated. Similarly at this time, the AND gate G2 outputs the write signal d via the OR gate G3 under the AND condition of the signals a, signals, and b, and writes the address information of the instruction into the memory circuit IVIemo.

As described above, according to the present invention, it is possible to record all of 11,1 including address information in the address space which is a program instruction, and to record it at fixed time intervals when the address information is not included.

(f) 9 Effects of the Invention As explained in detail above, according to the present invention, a program/1-race is executed within the address space consisting of 1-race, and a coarse program/1-race is executed outside the address space. ) per
Highly accurate programs and programs without increasing storage capacity
This has the great effect of being able to perform tracing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a conventional program transfer device. FIG. 2 is a block diagram showing one embodiment of the present invention. FIG. 3 is a time chart for explaining the operation of FIG. 2. In the figure, cpu is a central processing unit, and MEMO is a storage device.
I” RA CE Program 1 ~ Race device, DE
TI is detection circuit i, DET2 is detection circuit II, C0UN
TER is a counting circuit, Memo is a memory circuit, G1 and G2 are respective gates, and G3 is an OR gate. Fu (Zugun 2 days + (he) Ka 褥

Claims (1)

[Claims] Consisting of a central processing unit and a storage device 1'1. connects to the data processing system t, receives access information to the storage device from the central processing unit i''C,
- In a racing device, the first detection circuit detects access to one command, counts the number of accesses to the command, and a count value is reached - Sends an output signal when it reaches a fixed value Counting times 1. +7;,, a second detection circuit that monitors the address information of the instruction fetch and detects the instruction fetch to predetermined address information; The instruction fetch from outside the address space stores 1 reality information in the storage circuit at the output of the B1 number circuit, and the instruction fetch from outside the address space stores Instruction fetch is a program trace method whose η-characteristic is to store address information for each instruction fetch in the 1.σ circuit.